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| Patent # | Description |
|---|---|
| US-8,981,837 |
System and method for reduction of bottom plate parasitic capacitance in
charge pumps A system for providing a load current at a specific output voltage to a circuit block of an integrated circuit (IC) includes a supply node at a supply voltage,... |
| US-8,981,821 |
Interference mitigation output frequency determined by division factors
selected randomly Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering... |
| US-8,981,702 |
Automated motor control Input-output linearization (IOL) and extended state observer (ESO) techniques are applied to a Field Oriented Control (FOC) for Permanent Magnet Synchronous... |
| US-8,981,490 |
Transistor with deep Nwell implanted through the gate A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate... |
| US-8,981,445 |
Analog floating-gate memory with N-channel and P-channel MOS transistors An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The... |
| US-8,980,723 |
Multiple depth vias in an integrated circuit An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with... |
| US-8,978,146 |
Wireless communications system communicating secyre SIM and IMEI between
processors An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By... |
| US-8,978,017 |
Profiling operating context At least some of the illustrative embodiments are a computer-readable medium storing a program that, when executed by a processor, causes the processor to... |
| US-8,977,920 |
DDR circuitry data and control buses connected to test circuitry A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The... |
| US-8,977,919 |
Scan, test, and control circuits coupled to IC surfaces contacts A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals... |
| US-8,977,918 |
IC with connections between linking module and test access ports An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test... |
| US-8,977,916 |
Using data watchpoints to detect unitialized memory reads A method of detecting uninitialized memory reads is shown where either all or a subset of a random access memory system is initialized to a know value. One or... |
| US-8,977,915 |
pBIST engine with reduced SRAM testing bus width A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not... |
| US-8,977,884 |
Shared-PLL audio clock recovery in multimedia interfaces A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock... |
| US-8,977,878 |
Reducing current leakage in L1 program memory An embodiment of the invention provides a method for decreasing power in an L1 program memory of a multi-level memory system. The power is decreased by enabling... |
| US-8,977,821 |
Parallel processing of multiple block coherence operations A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation... |
| US-8,977,819 |
Prefetch stream filter with FIFO allocation and stream direction
prediction A prefetch filter receives a memory read request having an associated address for accessing data that is stored in a line of memory. An address window is... |
| US-8,976,980 |
Modulation of audio signals in a parametric speaker Methods and systems for amplitude modulation in a parametric speaker system are provided that perform truncated double sideband (TDSB) frequency modulation of... |
| US-8,976,914 |
Multi-tap IQ imbalance estimation and correction circuit and method A system for correcting gain imbalance and phase imbalance between first (I.sub.OUT) and second (Q.sub.OUT) signals which are 90.degree. out of phase, including... |
| US-8,976,860 |
Method and apparatus for determination of motion estimation search window
area utilizing adaptive sliding... A method and apparatus for motion estimation utilizing adaptive sliding window algorithm, the method includes estimating motion estimation search window size,... |
| US-8,976,292 |
Perceptual video quality improvement for videos containing black bars A method of improving the perceptual video quality of video sequences containing black bars. Horizontal or vertical black bars caused by a missmatch between the... |
| US-8,976,273 |
Multiplexed read-out architecture for CMOS image sensors This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel V.sub.N level instead of... |
| US-8,975,964 |
BEMF monitor gain calibration stage in hard disk drive servo integrated
circuit A high performance digitalized Programmable Gain Amplifier (PGA). In prior art circuit, a dual-ladder DAC is employed for gain control, the back gate leakage of... |
| US-8,975,963 |
Offset reduction for analog front-ends A circuit includes a first amplifier configured to amplify an input signal to generate an output signal. An offset sensor is configured to sense DC offset based... |
| US-8,975,961 |
Power amplifier control circuits Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter... |
| US-8,975,948 |
Wide common mode range transmission gate A transmission gate self-biases its transistors to provide a constant gate biasing that provides a consistent path for an input signal to be cleanly passed to... |
| US-8,975,886 |
Charging and distribution control A system configured for charging and distribution control is provided. The system includes a switching regulator, a control circuit and a first converter. The... |
| US-8,975,722 |
MEMS device and method of manufacture A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and... |
| US-8,975,135 |
Analog floating-gate capacitor with improved data retention in a silicided
integrated circuit An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The... |
| US-8,972,821 |
Encode and multiplex, register, and decode and error correction circuitry An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the... |
| US-8,972,810 |
I/O circuitry free of test clock coupled with destination/source circuitry The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication... |
| US-8,972,809 |
Test messaging and control circuitry coupled to power pad The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device.... |
| US-8,972,807 |
Integrated circuits capable of generating test mode control signals for
scan tests Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an... |
| US-8,971,634 |
Approximate pyramidal search for fast displacement matching A method for approximate pyramidal search for displacement matching is provided that includes performing a complete window-based search at a coarsest resolution... |
| US-8,971,464 |
Crest factor reduction for signals with dynamic power and frequency
distribution A method to form a CFR cancellation filter for signals with dynamic power and frequency distribution by estimating the filter at the rate required by the input... |
| US-8,971,455 |
Near-integer channel spur mitigation in a phase-locked loop A method includes relocating, to a frequency outside a cut-off frequency of a phase-locked loop, a spur frequency component at an input of the phase-locked loop... |
| US-8,971,448 |
Layer mapping for up link single user multiple input multiple output
wireless telephony This invention is a method and an apparatus to up link transmission of data from a user equipment to a base station for single user multiple input, multiple... |
| US-8,971,138 |
Method of screening static random access memory cells for positive bias
temperature instability A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory... |
| US-8,971,084 |
Context protection for a column interleaved memory A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set... |
| US-8,971,075 |
Method and apparatus for generating an adaptive switching frequency for
operating power factor correction circuit A method of operating a power factor correction (PFC) circuit and a corresponding power factor correction circuit include determining an adaptive switching... |
| US-8,970,459 |
System and method for timing color presentation of an image display system In accordance with the teachings of the present disclosure, a method and system for the timing color of an image display are provided. In one embodiment, a... |
| US-8,970,411 |
Pipelined continuous-time sigma delta modulator Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating... |
| US-8,970,300 |
Apparatus and method for transimpedance amplifiers with wide input current
ranges Improved preamplifier circuits for converting single-ended input current signals to differential output voltage signals, including first and second... |
| US-8,970,292 |
Universal filter implementing second-order transfer function An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and... |
| US-8,970,267 |
Asynchronous clock dividers to reduce on-chip variations of clock timing This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an... |
| US-8,970,199 |
Electronic device and method for DC-DC conversion with variable bias
current The invention relates to an electronic device and a method for DC-DC conversion using a comparator for generating an output signal for driving a power switch of... |
| US-8,970,162 |
System and method for balancing electrical energy storage devices via
differential power bus and capacitive... System and method are provided for transferring electrical energy among multiple electrical energy storage devices via multiple differential power buses and... |
| US-8,970,151 |
Detection of back EMF in two terminal actuator Back-emf for a motor is measured by measuring a voltage across the input terminals for a two terminal input actuator or motor when a high frequency driver... |
| US-8,966,647 |
Comparing central time stamp bits from bus and client circuitry This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined... |
| US-8,966,346 |
Apparatus and method for processing a physical layer convergence protocol
header Apparatus and method for processing a physical layer protocol convergence (PLCP) header. In one embodiment, a wireless device includes a PLCP header processor.... |
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