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Searching: texas instruments
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| Patent # | Description |
|---|---|
| US-9,306,458 |
Adaptive boost driver charging circuit A power circuit combination includes a series capacitor buck converter including a first half-bridge including a first high side power switch (HSA), first low... |
| US-9,306,263 |
Interface between an integrated circuit and a dielectric waveguide using a
dipole antenna and a reflector An electronic device has a multilayer substrate that has an interface surface configured for interfacing to a dielectric waveguide. A conductive layer on the... |
| US-9,306,259 |
Horn antenna for launching electromagnetic signal from microstrip to
dielectric waveguide A horn antenna is formed within a multilayer substrate and has a generally trapezoidal shaped top plate and bottom plate formed in different layers of the... |
| US-9,306,013 |
Method of forming a gate shield in an ED-CMOS transistor and a base of a
bipolar transistor using BICMOS... A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a... |
| US-9,305,998 |
Adhesion of ferroelectric material to underlying conductive capacitor
plate Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit.... |
| US-9,305,971 |
Integrated piezoelectric resonator and additional active circuit A semiconductor device comprises a semiconductor wafer; a piezoelectric resonator formed on the wafer, and an active circuit also formed on the wafer. The... |
| US-9,305,872 |
DC-DC converter having terminals of semiconductor chips directly
attachable to circuit board A power supply system has a QFN leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline... |
| US-9,305,871 |
High pin count, small packages having heat-dissipating pad A plastic package for high power has a pair of oblong metal pins exposed from a surface of the plastic, the pins straddling a corner of the package; each pin... |
| US-9,305,869 |
Packaged semiconductor device having leadframe features as pressure valves
against delamination A packaged semiconductor device (100) comprising a leadframe having a pad (101) with an assembled semiconductor chip (110), a plurality of straps (102)... |
| US-9,305,852 |
Silicon package for embedded electronic system having stacked
semiconductor chips An electronic system comprises a first chip (101) of single-crystalline semiconductor including a first electronic device embedded in a second chip (102) of... |
| US-9,305,848 |
Elongated contacts using litho-freeze-litho-etch process A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which... |
| US-9,305,812 |
Die eject assembly for die bonder Disclosed herein is a die eject assembly for a die bonder that may include a poker pin having an elongate shaft portion with a first end and a second end. The... |
| US-9,305,688 |
Single photomask high precision thin film resistor An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of... |
| US-9,305,664 |
Memory repair categorization tracking An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion... |
| US-9,305,184 |
Packet-processing scheduler, security context, authentication, packet
header, air cipher subsystem An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least... |
| US-9,304,954 |
Multi processor bridge with mixed Endian mode support An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each... |
| US-9,304,925 |
Distributed data return buffer for coherence system with speculative
address support The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or... |
| US-9,304,890 |
Method for throttling trace data streams A method of managing a debug trace data stream by detecting conditions where the trace data generated exceeds the available transmission bandwidth, and... |
| US-9,304,283 |
Bond-pad integration scheme for improved moisture barrier and electrical
contact An apparatus includes first and second electrodes separated by an insulative material (such as a piezoelectric material). The apparatus also includes a... |
| US-9,303,986 |
Navigation assistance based on visual codes Visual codes are scanned to assist navigation. The visual code may be a Quick Response (QR) code that contains information useful to calibrating a variety of... |
| US-9,303,953 |
Digital system for the detection of variations in operating conditions of
an integrated circuit A system for detecting tamper events in a digital circuit by having a Critical Path Replica (CPR) circuit operable in parallel with the circuit being monitored,... |
| US-9,300,975 |
Concurrent access shared buffer in a video encoder A video encoder includes a buffer, a DMA engine, a motion estimator and a motion compensator. The buffer includes four pages where macroblocks are stored. The... |
| US-9,300,361 |
Enabling co-existence among power line communication (PLC) technologies Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC... |
| US-9,300,247 |
RC oscillator with additional inverter in series with capacitor In an electronic device, an RC oscillator generally includes a resistor, a capacitor and at least one inverter. The resistor and capacitor generate a... |
| US-9,300,222 |
Three-dimensional power supply module with passive stacked over cavity A power converter sub-assembly/module includes a power switching assemblage defining a cavity within which can be mounted a driver IC. The power switching... |
| US-9,300,025 |
Interface between an integrated circuit and a dielectric waveguide using a
carrier substrate with a dipole... A system includes an integrated circuit that has a substrate with a top surface and a bottom surface. Semiconductor circuitry is including a radio frequency... |
| US-9,300,024 |
Interface between an integrated circuit and a dielectric waveguide using a
dipole antenna, a reflector and a... A system includes an electronic device coupled to a mating end of a dielectric wave guide (DWG). The electronic device has a multilayer substrate that has an... |
| US-9,299,832 |
High voltage lateral DMOS transistor with optimized source-side blocking
capability An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an... |
| US-9,299,830 |
Multiple shielding trench gate fet A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The... |
| US-9,299,697 |
High breakdown voltage microelectronic device isolation structure with
improved reliability A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low... |
| US-9,298,665 |
Multicore, multibank, fully concurrent coherence controller This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The... |
| US-9,298,643 |
Performance and power improvement on DMA writes to level two combined
cache/SRAM that is cached in level one... This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two... |
| US-9,294,346 |
Proxy pair identification communication though separate proxy devices and
paths In one form of invention a process of operating a host computer coupled to a communications network including: determining whether a diversity flag is set, when... |
| US-9,294,316 |
Scrambling sequences for wireless networks An integrated circuit includes logic configured to generate scrambling sequences, each based on a different scrambling seed, for a smart-utility-network data... |
| US-9,294,170 |
Efficient rank and precoding matrix feedback for MIMO systems The present disclosure provides a receiver, a transmitter and methods of operating a receiver or a transmitter. In one embodiment, the receiver includes a... |
| US-9,294,153 |
Systems and methods of wireless power transfer with interference detection Systems and methods of wireless power transfer system with interference detection disclosed herein detects possible excessive energy transfer associated with... |
| US-9,294,138 |
Mixer sequence design for N-path filters A bandpass filter includes a plurality of parallel paths, each receiving the input signal to the bandpass filter. Each path includes a first mixer, a low-pass... |
| US-9,294,116 |
Digital to analog converter discharge circuit and associated method for
analog to digital converter circuits A circuit includes an amplifier circuit that receives a residue voltage from an output capacitor connected to an output of a digital to analog converter (DAC).... |
| US-9,294,082 |
Circuit for current sensing in high-voltage transistor An integrated circuit including a high-voltage n-channel MOS power transistor, a high-voltage n-channel MOS blocking transistor, a high-voltage n-channel MOS... |
| US-9,294,061 |
Low power, low out-of-band harmonic content radio A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer... |
| US-9,294,000 |
Direct conversion output driver A circuit and method for providing a fully integrated differential boost converter and amplifier. A first half bridge circuit has a first output node and a... |
| US-9,293,460 |
ESD protection device with improved bipolar gain using cutout in the body
well An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base... |
| US-9,293,422 |
Optoelectronic packages having magnetic field cancelation A stacked optoelectronic packaged device includes a bottom die having a top surface including bottom electrical traces and a light source die coupled to... |
| US-9,293,357 |
Sinker with a reduced width The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation... |
| US-9,293,254 |
Heated capacitor and method of forming the heated capacitor A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an... |
| US-9,292,721 |
NFC receiver architecture with improved power sensitivity An electronic communication device includes an antenna configured to receive a radio frequency (RF) signal and generate a differential current signal at a first... |
| US-9,292,038 |
Synchronization circuit A synchronization circuit receives an external clock input. The circuit includes an internal oscillator; a clock detection circuit, coupled to the external... |
| US-9,291,819 |
Multi-focus heads-up display using single picture generator unit Apparatus and methods are described for creating multiple different heads-up display (HUD) images at different apparent distances from a viewer using a single... |
| US-9,291,675 |
Boundary control scan cells, data cells, resynchronization memories, and
multiplexers An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a... |
| US-9,291,648 |
Hybrid closed-loop/open-loop magnetic current sensor Hybrid magnetic current sensors and sensing apparatus are presented with closed-loop and open-loop circuitry employs first and second integrated magnetic... |
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