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Patent # Description
US-8,581,317 SOI MuGFETs having single gate electrode level
A silicon on insulator (SOI) multi-gate field effect transistor electrically Programmable Read-Only Memory (MuFET EPROM) includes a substrate having a...
US-8,581,233 Variable capacitor single-electron transistor including a P-N junction gate electrode
The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a...
US-8,580,685 Integrated circuit having interleaved gridded features, mask set, and method for printing
A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the...
US-8,580,675 Two-track cross-connect in double-patterned structure using rectangular via
An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect...
US-8,580,663 Formation of shallow junctions by diffusion from a dielectronic doped by cluster or molecular ion beams
A process for forming diffused region less than 20 nanometers deep with an average doping dose above 10.sup.14 cm.sup.-2 in an IC substrate, particularly LDD...
US-8,580,650 Lateral superjunction extended drain MOS transistor
An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF...
US-8,580,631 High sheet resistor in CMOS flow
An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with...
US-8,578,225 One agumentation instruction register coupled to plural TAP instruction registers
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
US-8,578,224 High density flip-flop with asynchronous reset
A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to...
US-8,576,604 Identifying and correcting a bit error in a FRAM storage unit of a semiconductor device
An embodiment of semiconductor device including a control unit and an FRAM storage unit is disclosed. The FRAM storage unit contains FRAM cells. The control...
US-8,576,596 Systems and methods for off-time control in a voltage converter
Various embodiments of the present invention provide voltage converters and methods for using such. As one example, a voltage converter is disclosed that...
US-8,576,487 Spoke light recapture for the spoke between a color of a wheel and its neutral density complement
Disclosed is a video display system comprising a spatial light modulator, such as a DMD modulator. The system uses a light source and color-wheel filter that is...
US-8,576,007 High speed amplifier
For high speed amplifiers, the parasitic capacitances from the differential input pair introduce a zero that can affect performance. Here, a neutralization...
US-8,575,903 Voltage regulator that can operate with or without an external power transistor
A voltage regulator, according to the present invention, can operate with or without an external power transistor to generate a regulated output voltage. The...
US-8,575,845 Method and apparatus to measure light intensity
A method for controlling a light emitting diode (LED) is provided. Initially, the LED, which had been active, is deactivated, and a voltage for a current that...
US-8,575,758 Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies
A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second...
US-8,575,752 Modulated deposition process for stress control in thick TiN films
A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are...
US-8,575,020 Pattern-split decomposition strategy for double-patterned lithography process
An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, and forming a second...
US-8,575,015 Lateral trench mosfet having a field plate
One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes...
US-8,575,014 Semiconductor device fabricated using a metal microstructure control process
The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the...
US-8,574,980 Method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate...
A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of...
US-8,574,979 Method for integrating silicon germanium and carbon doped silicon with source/drain regions in a strained CMOS...
The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment,...
US-8,574,967 Method for fabricating array-molded package-on-package
An improved semiconductor device package is manufactured by attaching semiconductor chips (130) on an insulating substrate (101) having contact pads (103). A...
US-8,574,931 Singulation and strip testing of no-lead integrated circuit packages without tape frame
Strip testing is applied to a plurality of integrated circuit dies that are each encapsulated in an encapsulant, that each have a set of externally accessible...
US-8,572,541 Method and system for adaptive physical design
A method is provided that includes performing a free placement of a system design comprising a plurality of power domains, wherein the power domains are not...
US-8,572,446 Output circuitry with tri-state buffer and comparator circuitry
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
US-8,572,433 JTAG IC with commandable circuit controlling data register control router
The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to...
US-8,572,154 Reduced-level two's complement arithmetic unit
A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the "1" to the...
US-8,571,611 System and method for wirelessly providing multimedia
System and method for wirelessly providing multimedia. A system includes a headset and a wireless communications device. The wireless communications device...
US-8,571,120 Transmission of acknowledge/not acknowledge (ACK/NACK) bits and their embedding in the reference signal
Transmitting a acknowledge/not acknowledge (ACK/NACK) response in a wireless cellular network by mapping the data value into a cyclic shifted version of a...
US-8,571,092 Interconnect coding method and apparatus
A computer program that is embodied on a storage medium for execution on a processor is provided. With this computer program, A current cost is calculated for...
US-8,570,946 RF and baseband means buffering data until after demodulating control
System and method for signaling control information in a multi-carrier communications system to transmit data. A preferred embodiment comprises demodulating a...
US-8,570,812 Method of reading a ferroelectric memory cell
A method of reading a memory cell. The method includes the step of connecting (708) a reference voltage generator (600) to a first bitline (/BL). The first...
US-8,570,414 Multiplexed read-out architecture for CMOS image sensors
This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel V.sub.N level instead of...
US-8,570,411 Solid state image pickup device and driving method therefore selecting a first signal or a sequentally output...
The objective of this invention is to provide a solid-state image pickup device and its driving method that has a minimum circuit area and a wide dynamic range....
US-8,570,205 Analog to digital converter with leakage current correction circuit
An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch...
US-8,570,012 Diode for use in a switched mode power supply
A tunable depletion diode is provided. Within this depletion diode, there is a depletion mode transistor that is coupled to the anode terminal at its gate and...
US-8,569,838 Control of local environment for polysilicon conductors in integrated circuits
A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin...
US-8,569,813 Inductive load driving circuit
The objective of this invention is to provide a photodiode which has high sensitivity even to light with a wavelength in the blue region while maintaining the...
US-8,569,082 Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame
Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material...
US-8,566,659 Generator and compactor adaptor for low power divided scan path
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-8,566,621 Method for implementing thermal management in a processor and/or apparatus and/or system employing the same
A method for detecting temperature associated with a processor, results of the detecting being used for controlling power dissipation associated with the...
US-8,564,724 Ghosting artifact reduction in temporal noise filtering
A method of noise filtering of a digital video sequence to reduce ghosting artifacts, the method including computing motion values for pixels in a frame of the...
US-8,564,351 Clock phase compensation for adjusted voltage circuits
Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input...
US-8,302,047 Statistical static timing analysis in non-linear regions
A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic...
US-8,301,946 Inverted TCK access port selector with normal TCK data flip-flop
The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The...
US-8,301,944 State machine select inputs coupled to TDI, TCK, and TMS
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-8,301,928 Automatic wakeup handling on access in shared memory controller
A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered....
US-8,301,431 Apparatus and method for accelerating simulations and designing integrated circuits and other systems
A method of accelerating a Monte Carlo (MC) simulation for a system including a first component having a first input parameter and a second component having a...
US-8,301,105 Receiver front end
A low-power receiver front-end includes a transconductance amplifier that produces a single-ended current signal in response to a single-ended voltage signal....
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