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Patent # Description
US-8,574,979 Method for integrating silicon germanium and carbon doped silicon with source/drain regions in a strained CMOS...
The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment,...
US-8,574,967 Method for fabricating array-molded package-on-package
An improved semiconductor device package is manufactured by attaching semiconductor chips (130) on an insulating substrate (101) having contact pads (103). A...
US-8,574,931 Singulation and strip testing of no-lead integrated circuit packages without tape frame
Strip testing is applied to a plurality of integrated circuit dies that are each encapsulated in an encapsulant, that each have a set of externally accessible...
US-8,572,541 Method and system for adaptive physical design
A method is provided that includes performing a free placement of a system design comprising a plurality of power domains, wherein the power domains are not...
US-8,572,446 Output circuitry with tri-state buffer and comparator circuitry
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
US-8,572,433 JTAG IC with commandable circuit controlling data register control router
The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to...
US-8,572,154 Reduced-level two's complement arithmetic unit
A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the "1" to the...
US-8,571,611 System and method for wirelessly providing multimedia
System and method for wirelessly providing multimedia. A system includes a headset and a wireless communications device. The wireless communications device...
US-8,571,120 Transmission of acknowledge/not acknowledge (ACK/NACK) bits and their embedding in the reference signal
Transmitting a acknowledge/not acknowledge (ACK/NACK) response in a wireless cellular network by mapping the data value into a cyclic shifted version of a...
US-8,571,092 Interconnect coding method and apparatus
A computer program that is embodied on a storage medium for execution on a processor is provided. With this computer program, A current cost is calculated for...
US-8,570,946 RF and baseband means buffering data until after demodulating control
System and method for signaling control information in a multi-carrier communications system to transmit data. A preferred embodiment comprises demodulating a...
US-8,570,812 Method of reading a ferroelectric memory cell
A method of reading a memory cell. The method includes the step of connecting (708) a reference voltage generator (600) to a first bitline (/BL). The first...
US-8,570,414 Multiplexed read-out architecture for CMOS image sensors
This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel V.sub.N level instead of...
US-8,570,411 Solid state image pickup device and driving method therefore selecting a first signal or a sequentally output...
The objective of this invention is to provide a solid-state image pickup device and its driving method that has a minimum circuit area and a wide dynamic range....
US-8,570,205 Analog to digital converter with leakage current correction circuit
An analog to digital converter includes leakage current correction circuitry to cancel leakage current injected by a reset switch employing a dummy PMOS switch...
US-8,570,012 Diode for use in a switched mode power supply
A tunable depletion diode is provided. Within this depletion diode, there is a depletion mode transistor that is coupled to the anode terminal at its gate and...
US-8,569,838 Control of local environment for polysilicon conductors in integrated circuits
A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin...
US-8,569,813 Inductive load driving circuit
The objective of this invention is to provide a photodiode which has high sensitivity even to light with a wavelength in the blue region while maintaining the...
US-8,569,082 Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame
Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material...
US-8,566,659 Generator and compactor adaptor for low power divided scan path
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-8,566,621 Method for implementing thermal management in a processor and/or apparatus and/or system employing the same
A method for detecting temperature associated with a processor, results of the detecting being used for controlling power dissipation associated with the...
US-8,564,724 Ghosting artifact reduction in temporal noise filtering
A method of noise filtering of a digital video sequence to reduce ghosting artifacts, the method including computing motion values for pixels in a frame of the...
US-8,564,351 Clock phase compensation for adjusted voltage circuits
Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input...
US-8,302,047 Statistical static timing analysis in non-linear regions
A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic...
US-8,301,946 Inverted TCK access port selector with normal TCK data flip-flop
The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The...
US-8,301,944 State machine select inputs coupled to TDI, TCK, and TMS
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-8,301,928 Automatic wakeup handling on access in shared memory controller
A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered....
US-8,301,431 Apparatus and method for accelerating simulations and designing integrated circuits and other systems
A method of accelerating a Monte Carlo (MC) simulation for a system including a first component having a first input parameter and a second component having a...
US-8,301,105 Receiver front end
A low-power receiver front-end includes a transconductance amplifier that produces a single-ended current signal in response to a single-ended voltage signal....
US-8,300,703 System and method for adaptively allocating resources in a transcoder
An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of...
US-8,300,561 Methods and apparatus for canceling distortion in full-duplex transceivers
Methods and apparatus for canceling distortion in full-duplex transceivers are disclosed. Some example methods to reduce distortion in a full-duplex transceiver...
US-8,300,510 Laser diode write driver
A laser diode write driver is described. This laser diode write driver comprises: a feedback loop coupled for receiving an input current signal, the feedback...
US-8,300,451 Two word line SRAM cell with strong-side word line boost for write provided by weak-side word line
An integrated circuit having a static random access memory (SRAM) includes an array of SRAM cells arranged in rows and columns having a write word line and a...
US-8,300,446 Ferroelectric random access memory with single plate line pulse during read
A ferroelectric random access memory (FRAM) with reduced cycle time. During a read cycle, plate line voltages are boosted to a voltage to both transfer charge...
US-8,299,827 High-speed frequency divider and a phase locked loop that uses the high-speed frequency divider
A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a...
US-8,299,612 IC devices having TSVS including protruding tips having IMC blocking tip ends
A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve, an inner metal core and protruding TSV tips including...
US-8,299,588 Structure and method for uniform current distribution in power supply module
A synchronous Buck converter in a molded package (thickness 101 between 0.8 and 1.0 mm) has vertically assembled control (110) and sync (120) power FET chips...
US-8,299,464 Comparator receiving expected and mask data from circuit pads
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the...
US-8,298,947 Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external...
US-8,298,944 Warpage control for die with protruding TSV tips during thermo-compressive bonding
A method of fabricating through silicon via (TSV) die includes depositing a first dielectric layer on a substrate that includes a plurality of TSV die. The TSV...
US-8,298,874 Packaged electronic devices having die attach regions with selective thin dielectric layer
A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least...
US-8,298,870 Method for connecting integrated circuit chip to power and ground circuits
In a method for transferring at least one of power and ground signal between a die and a package base of a semiconductor device, a connector is formed there...
US-8,298,863 TCE compensation for package substrates for reduced die warpage assembly
A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite...
US-8,298,854 Method of manufacturing PIN photodiode
The objective of this invention is to provide a type of photodiode and the method of manufacturing the photodiode characterized by the fact that it has a higher...
US-8,297,472 Pellet loader with pellet separator for molding IC devices
A pellet loading apparatus includes a tablet pusher including a support surfaces including a pusher mechanism coupled thereto for vertical movement upon...
US-8,296,714 System and method for checking analog circuit with digital checker
Aspects of the present invention provide a system and method for checking a portion of an analog circuit using a digital checker. The method includes...
US-8,296,701 Method for designing a semiconductor device based on leakage current estimation
A method of designing a semiconductor device includes preparing a first design for a semiconductor device and estimating leakage current for the first design....
US-8,296,628 Data path read/write sequencing for reduced power consumption
A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The...
US-8,296,614 Moving data through test control register with state machine states
Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these...
US-8,296,607 Serialization module separating pipelined trace-worthy event and sync packet data
A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor...
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