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Patent # Description
US-8,994,154 Proximity sensor having light blocking structure in leadframe
A semiconductor proximity sensor (100) has a flat leadframe (110) with a first (110a) and a second (110b) surface, the second surface being solderable; the...
US-8,993,412 Method for reducing backside die damage during die separation process
In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing...
US-8,990,650 TCA with scan paths, decompressor, compressor, and output shift register
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access...
US-8,990,649 Access port selector for access port and compliant access port
The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The...
US-8,989,447 Dynamic focus for computational imaging
A method for all-in-focus image reconstruction and depth map generation in an imaging device is provided that includes capturing a multi-focus image by the...
US-8,988,667 Halogen gas sensor comprising cobalt
A method of halogen gas monitoring includes contacting room air to be monitored with a halogen sensor including a cobalt or cobalt alloy layer. The halogen...
US-8,988,531 Method and apparatus for sub-picture based raster scanning coding order
A method and apparatus for sub-picture based raster scanning coding order. The method includes dividing an image into even sub-pictures, and encoding parallel...
US-8,988,266 Asynchronous sampling using dynamically configurable voltage polling levels
A method, comprising: receiving an analog input; determining an upper outer rail and a lower outer rail as polling values to be used by voltage comparators;...
US-8,988,131 Transistor switch including independent control of turn-on and slew rate
The disclosed transistor switching methodology enables independent control of transistor turn-on delay and slew rate, including charging, during a pre-charge...
US-8,987,748 Drain induced barrier lowering with anti-punch-through implant
An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer...
US-8,984,359 Base, IC, and coupling interposer with boundary scan register
The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement...
US-8,984,358 IC TAP with address, state monitor, and state decode circuitry
The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a...
US-8,984,357 Wrapper selector data register having control outputs and SELECTAM input
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard...
US-8,984,356 Circuitry selectively coupling scan circuitry to test data out lead
An integrated circuit has controller circuitry having inputs coupled to a test clock lead and to a test mode select lead, and having state outputs indicating...
US-8,984,319 Adapter power up circuitry forcing tap states and decoupling tap
A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and...
US-8,984,246 Method, system and computer program product for reading a decision tree
In response to a query of a decision tree, a first packed node of the decision tree is copied from a system memory into a direct memory access ("DMA") memory....
US-8,983,218 Virtual boundary processing simplification for adaptive loop filtering (ALF) in video coding
Virtual boundary processing in adaptive loop filtering (ALF) requires that padded values be substituted for unavailable pixel rows outside the virtual...
US-8,983,080 Method and system for temperature protection of a speaker
For protecting a speaker, an input signal is received and filtered into component signals. A sum of the component signals is approximately equal to the input...
US-8,983,012 Receive timing manager
A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition...
US-8,982,517 Electrostatic discharge protection apparatus
An electrostatic discharge (ESD)-triggered protection apparatus includes a first circuit and a second circuit. The first circuit includes an ESD trigger circuit...
US-8,981,984 Asynchronous to synchronous sampling using an augmented least squares solver
A method, comprising: receiving a plurality of 2-tuples of asynchronously sampled inputs at an asynchronous to synchronous reconstructor; performing a coarse...
US-8,981,837 System and method for reduction of bottom plate parasitic capacitance in charge pumps
A system for providing a load current at a specific output voltage to a circuit block of an integrated circuit (IC) includes a supply node at a supply voltage,...
US-8,981,821 Interference mitigation output frequency determined by division factors selected randomly
Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering...
US-8,981,702 Automated motor control
Input-output linearization (IOL) and extended state observer (ESO) techniques are applied to a Field Oriented Control (FOC) for Permanent Magnet Synchronous...
US-8,981,490 Transistor with deep Nwell implanted through the gate
A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate...
US-8,981,445 Analog floating-gate memory with N-channel and P-channel MOS transistors
An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The...
US-8,980,723 Multiple depth vias in an integrated circuit
An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with...
US-8,978,146 Wireless communications system communicating secyre SIM and IMEI between processors
An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By...
US-8,978,017 Profiling operating context
At least some of the illustrative embodiments are a computer-readable medium storing a program that, when executed by a processor, causes the processor to...
US-8,977,920 DDR circuitry data and control buses connected to test circuitry
A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The...
US-8,977,919 Scan, test, and control circuits coupled to IC surfaces contacts
A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals...
US-8,977,918 IC with connections between linking module and test access ports
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
US-8,977,916 Using data watchpoints to detect unitialized memory reads
A method of detecting uninitialized memory reads is shown where either all or a subset of a random access memory system is initialized to a know value. One or...
US-8,977,915 pBIST engine with reduced SRAM testing bus width
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not...
US-8,977,884 Shared-PLL audio clock recovery in multimedia interfaces
A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock...
US-8,977,878 Reducing current leakage in L1 program memory
An embodiment of the invention provides a method for decreasing power in an L1 program memory of a multi-level memory system. The power is decreased by enabling...
US-8,977,821 Parallel processing of multiple block coherence operations
A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation...
US-8,977,819 Prefetch stream filter with FIFO allocation and stream direction prediction
A prefetch filter receives a memory read request having an associated address for accessing data that is stored in a line of memory. An address window is...
US-8,976,980 Modulation of audio signals in a parametric speaker
Methods and systems for amplitude modulation in a parametric speaker system are provided that perform truncated double sideband (TDSB) frequency modulation of...
US-8,976,914 Multi-tap IQ imbalance estimation and correction circuit and method
A system for correcting gain imbalance and phase imbalance between first (I.sub.OUT) and second (Q.sub.OUT) signals which are 90.degree. out of phase, including...
US-8,976,860 Method and apparatus for determination of motion estimation search window area utilizing adaptive sliding...
A method and apparatus for motion estimation utilizing adaptive sliding window algorithm, the method includes estimating motion estimation search window size,...
US-8,976,292 Perceptual video quality improvement for videos containing black bars
A method of improving the perceptual video quality of video sequences containing black bars. Horizontal or vertical black bars caused by a missmatch between the...
US-8,976,273 Multiplexed read-out architecture for CMOS image sensors
This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel V.sub.N level instead of...
US-8,975,964 BEMF monitor gain calibration stage in hard disk drive servo integrated circuit
A high performance digitalized Programmable Gain Amplifier (PGA). In prior art circuit, a dual-ladder DAC is employed for gain control, the back gate leakage of...
US-8,975,963 Offset reduction for analog front-ends
A circuit includes a first amplifier configured to amplify an input signal to generate an output signal. An offset sensor is configured to sense DC offset based...
US-8,975,961 Power amplifier control circuits
Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter...
US-8,975,948 Wide common mode range transmission gate
A transmission gate self-biases its transistors to provide a constant gate biasing that provides a consistent path for an input signal to be cleanly passed to...
US-8,975,886 Charging and distribution control
A system configured for charging and distribution control is provided. The system includes a switching regulator, a control circuit and a first converter. The...
US-8,975,722 MEMS device and method of manufacture
A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and...
US-8,975,135 Analog floating-gate capacitor with improved data retention in a silicided integrated circuit
An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The...
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