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Method and apparatus for diminishing mismatch effects between switched
A circuit for diminishing mismatch effects between at least two switched signals includes at least three processing circuits configured to receive at least two...
Radio frequency built-in self test for quality monitoring of local
oscillator and transmitter
A system and method for low-cost performance and compliance testing of local oscillators and transmitters for wireless RF applications. A preferred embodiment...
Voltage compensated tracking circuit in SRAM
Supply voltage compensated tracking circuit in a split-rail static random access memory (SRAM). The circuit includes a tracking circuit for tracking a delay...
Active rectifier and method for energy harvesting power management circuit
An active rectifier (12) couples a first input voltage (Vin1) to a first electrode of a first transistor (M3) having a second electrode coupled to an output (4)...
Electrostatic discharge (ESD) protection circuit and related apparatus and
An electrostatic discharge (ESD) protection circuit includes a control circuit configured to generate a signal indicating whether an input voltage on an...
Pipelined continuous-time sigma delta modulator
Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating...
Capacitor nonlinearity correction
A sample-and-hold (S/H) circuit is provided. The S/H circuit generally comprises a sampling switch, a sampling capacitor, and a correction network. The sampling...
Boost regulator with pulse frequency mode of operation having
substantially constant percentage output ripple...
A method includes receiving an input voltage at a voltage regulator and generating an output voltage using the voltage regulator, which includes an inductor....
Scan paths, stimulus, and header circuitry with command/frame marker
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test...
Ammonia pre-treatment in the fabrication of a memory cell
A method of manufacturing a memory cell 200. The method comprises forming a memory stack 215. Forming the memory stack includes pre-treating an insulating layer...
Partitioning features of a single IC layer onto multiple photolithographic
One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is...
Device address port circuitry with local, group, and global outputs
The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without...
Scan path switch testing of output buffer with ESD
The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
System and method for managing radio link failures
A wireless transmit/receive unit (WTRU) (152) in a wireless communications system includes a transceiver (153) for transmitting and receiving data from a...
System and method for tuning FM synthesizer
A device is provided for dividing a clock signal by even and odd integers. The device includes a divider, a delay portion and a duty cycle corrector. The...
Noise robust contrast-enhancement engine employing IIR filters
A noise robust contrast-enhancement engine utilizes low-pass infinite-impulse-response filters for enhancing the contrast while preventing noise amplification...
System and method for setting bias for MR head
A device for setting a bias for a magneto-resistive (MR) head can include a counter configured to provide a count value that varies incrementally from a first...
LED driving element, backlight device, and backlight device driving method
An LED driving element that can perform black line insertion display without increasing the clock frequency. LED driving element 11 has first and second shift...
Enhancement of power management using dynamic voltage and frequency
scaling and digital phase lock loop high...
An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop,...
Auto-tuning power supply
An apparatus for and method of automatically tuning a voltage regulation control loop for a digitally controlled switch mode power supply is provided. The...
Adaptive rectifier architecture and method for switching regulators
An adjustable compensation offset voltage is applied to a comparator to vary turn-off timing of a synchronous rectifier. A comparator output indicates when...
Lateral insulated gate bipolar transistor
Current density in an insulated gate bipolar transistor (L-IGBT) may be increased by adding a second gate, and the corresponding MOS transistors, to the source...
Combined metallic bonding and molding for electronic assemblies including
A method for forming electronic assemblies includes providing a plurality of IC die each having IC bonding conductors and a workpiece having workpiece bonding...
System and method for production of high purity silicon solids and solids
Systems and methods and resulting compositions of matter including silicon solids from a mixture of silicon and water. The mixture is collected at a collection...
Scan distributor and parallel scan paths with controlled output buffer
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing...
Method and system for estimating frequency and amplitude change of
Methods, digital systems, and computer readable media are provided for estimating change of amplitude and frequency in a digital audio signal by transforming a...
At very high frequencies, generally above 100 GHz, the performance of traditional radio frequency (RF) circuitry begins to significantly limit performance. An...
Fast macroblock structure decision using SAD discrepancy and its
The present invention is a method to accelerate the frame/field decision by estimating more suitable structure using SAD (sum of absolute difference) between...
Laser diode read driver
A first transistor produces a first voltage in response to a first current signal. A first resistor is coupled between the first transistor and a low voltage...
System and method for displaying stereoscopic digital motion picture
In accordance with the teachings of the present invention, a system and method for displaying stereoscopic digital motion picture images are provided. In a...
Semiconductor chip package assembly with deflection-resistant leadfingers
The invention relates to leadframes and semiconductor chip package assemblies using leadframes, and to methods for their assembly. A disclosed embodiment of the...
Isolation trench with rounded corners for BiCMOS process
A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the...
Method to attain low defectivity fully silicided gates
A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is...
Integrated high voltage capacitor having capacitance uniformity structures
and a method of manufacture therefor
The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The...
By-die-exposure for patterning of holes in edge die
In accordance with the invention, there are semiconductor devices and methods of making semiconductor devices and holes. The method of making a semiconductor...
LED package having improved light coupling efficiency for an optical
system and method of manufacture thereof
One aspect of an LED package, which is covered by this disclosure, includes at least two LED emitters located on a substrate wherein each of the at least two...
Multiplexer with serial and scan data inputs for scan path
The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and...
Link instruction register with resynchronization register
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing...
Shared error resiliency path through coefficient reordering
The method, system, and apparatus of a shared error resiliency path through coefficient reordering is disclosed. In on embodiment, determining that an input...
Reduced calculations in determining intra-prediction type method and
The method, system, and apparatus of source statistics based intra prediction type is disclosed. In one embodiment, a method includes classifying a four-pixel...
Higher order multiple input, multiple output extension
A method of multiple input multiple output downlink communications including mapping complex-valued modulation symbols onto one or more transmission layers by...
Adaptive transmissions in wireless networks
A network includes an access point and a station. The station transmits to the access point a current clear-to-send packet at a current time during a current...
5-wire resistive touch screen pressure measurement circuit and method
A 5-wire touch screen system includes a touch screen (10) including a wiper (11) and a resistive layer (16) aligned with the wiper and first (UL), second (UR),...
Pipelined ADC having a three-level DAC elements
In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state...
Systems and methods of ripple reduction in a DC/DC converter
Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous...
Timing skew error correction apparatus and methods
Apparatus and methods disclosed herein operate to compensate for skew between inverse phases (e.g., differential phases) of an analog signal appearing at the...
Class DH amplifier
A class DH amplifier is provided. The amplifier is generally comprised of a tracking power supply, a class D amplifier section, and a carrier generator. The...
Light-emitting diode controller
Light-emitting diode controller 10 contains voltage source circuit 33 for feeding voltage to the anode of light-emitting diode 13, current source circuit 34...
IC die including RDL capture pads with notch having bonding connectors or
its UBM pad over the notch
An IC die includes active circuitry and I/O nodes tied together in first net and at least a second net. A first die pad and a second die pad adjacent thereto...
Alignment mark for opaque layer
An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark...