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Patent # Description
US-8,295,396 System and method for power control in a wireless transmitter
A system and method for power control in a wireless transmitter. A power control loop includes a feed forward unit coupled to a data source, the feed forward...
US-8,295,262 Uplink reference signal for time and frequency scheduling of transmissions
A method for multiplexing reference signal (RS) transmissions from user equipments (UEs), with the RS having a bandwidth larger than the data signal bandwidth...
US-8,294,473 Cable detector
A cable detector includes one or more peak detectors that detect when a termination impedance is missing from the output of a line driver. A peak detection...
US-8,294,451 Smart sensors for solar panels
A solar panel smart sensor system is disclosed. The sensor system permits solar power system owners and operators to monitor the voltage of individual panels in...
US-8,294,388 Driving system with inductor pre-charging for LED systems with PWM dimming control or other loads
A method includes receiving a control signal associated with a load, where the control signal is to cause a load change from a perspective of a switching-mode...
US-8,294,261 Protruding TSV tips for enhanced heat dissipation for IC devices
An integrated circuit (IC) device includes a substrate having a top surface including substrate pads, and a through substrate via (TSV) die including a...
US-8,294,243 Lateral bipolar transistor with compensated well regions
Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar...
US-8,294,218 Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate...
An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor...
US-8,294,210 High voltage channel diode
A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.
US-8,293,573 Microarray package with plated contact pedestals
A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically...
US-8,291,435 JEK class loader notification
A method and system for performing class loader notification. At least some of the illustrative embodiments are methods comprising raising a notification during...
US-8,291,354 Merging sub-resolution assist features of a photolithographic mask
Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature...
US-8,291,254 High speed digital bit stream automatic rate sense detection
As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are supported,...
US-8,290,492 Handover for DVB-H
A method of wireless handover in a broadcast network (FIGS. 5 and 8) is disclosed. A wireless receiver (FIG. 4) receives a first signal (N) from a first...
US-8,290,113 Frequency synthesizer prescaler scrambling
Various apparatuses, methods and systems for frequency dividing a clock signal are disclosed herein. For example, some embodiments of the present invention...
US-8,290,098 Closed loop multiple transmit, multiple receive antenna wireless communication system
A wireless receiver (74) for receiving signals from a transmitter (72). The transmitter comprises a plurality of transmit antennas (TAT.sub.1', TAT.sub.2') for...
US-8,290,084 Space time transmit diversity for TDD/WCDMA systems
A circuit is designed with a matched filter circuit including a plurality of fingers (700, 702, 704) coupled to receive a data symbol. Each finger corresponds...
US-8,290,024 Methods and apparatus to facilitate improved code division multiple access receivers
Methods and apparatus to facilitate improve code division multiple access (CDMA) receivers are disclosed. An example method disclosed herein comprises:...
US-8,289,832 Input signal processing system
An input signal processing system is described. It comprises a first transconductance device having a first input, second input, and an output, wherein the...
US-8,289,651 Apparatus to control heat dissipation in hard-disk drives
Methods and apparatus to control heat dissipation in hard-disk drives (HDDs) are disclosed. A disclosed example apparatus comprises a semiconductor die, a...
US-8,289,257 Reduced swing differential pre-drive circuit
A circuit for reducing and offsetting the voltage swing of a differential pre-drive circuit. The circuit includes a first H-bridge of transistors receiving a...
US-8,289,205 Reacquiring satellite signals quickly
Embodiments of the invention provide a method of reacquiring satellite signals quickly. A pseudorange of at least one satellite is estimated. A user's position...
US-8,289,198 Low power bit switches and method for high-voltage input SAR ADC
A switched capacitor circuit, which may be an SAR ADC, includes a plurality of bit switching circuits (33) each including a high-voltage sampling switch circuit...
US-8,289,183 System and method for solar panel array analysis
A system and method for monitoring performance of one or more solar panels in a photovoltaic array. The system and method includes a number of sensors are...
US-8,289,009 Low dropout (LDO) regulator with ultra-low quiescent current
An apparatus includes at least one filter configured to filter a reference voltage to generate a filtered reference voltage. The apparatus also includes an...
US-8,288,953 Buck constant average current regulation of light emitting diodes
An apparatus includes pulse width modulation (PWM) circuitry configured to generate a PWM signal based on a feedback voltage associated with current flowing...
US-8,288,849 Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory...
US-8,288,834 Semiconductor wafer and die that include an integrated circuit and two or more different MEMS-based...
Various semiconductor devices can be formed at the end of a common fabrication process, thereby significantly improving manufacturing flexibility, by...
US-8,288,820 High voltage power integrated circuit
A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS...
US-8,288,805 Semiconductor device with gate-undercutting recessed region
A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a...
US-8,288,283 Aluminum enhanced palladium CMP process
A process of forming an integrated circuit using a palladium CMP operation in which 25 to 125 ppm aluminum is added to the CMP slurry, allowing a palladium...
US-8,288,243 Method for fabricating through substrate microchannels
A method of forming large microchannels in an integrated circuit by etching an enclosed trench into the substrate and later thinning the backside to expose the...
US-8,286,929 Clam shell two-pin wafer holder for metal plating
A clam shell wafer holder includes a base and a lid pivotally connected with the base by an integral hinge. The base includes a rotatable wafer support, and the...
US-8,286,042 On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost...
This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state...
US-8,284,963 Method and apparatus for diminishing mismatch effects between switched signals
A circuit for diminishing mismatch effects between at least two switched signals includes at least three processing circuits configured to receive at least two...
US-8,284,886 Radio frequency built-in self test for quality monitoring of local oscillator and transmitter
A system and method for low-cost performance and compliance testing of local oscillators and transmitters for wireless RF applications. A preferred embodiment...
US-8,284,626 Voltage compensated tracking circuit in SRAM
Supply voltage compensated tracking circuit in a split-rail static random access memory (SRAM). The circuit includes a tracking circuit for tracking a delay...
US-8,284,581 Active rectifier and method for energy harvesting power management circuit
An active rectifier (12) couples a first input voltage (Vin1) to a first electrode of a first transistor (M3) having a second electrode coupled to an output (4)...
US-8,284,530 Electrostatic discharge (ESD) protection circuit and related apparatus and method
An electrostatic discharge (ESD) protection circuit includes a control circuit configured to generate a signal indicating whether an input voltage on an...
US-8,284,085 Pipelined continuous-time sigma delta modulator
Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating...
US-8,283,948 Capacitor nonlinearity correction
A sample-and-hold (S/H) circuit is provided. The S/H circuit generally comprises a sampling switch, a sampling capacitor, and a correction network. The sampling...
US-8,283,907 Boost regulator with pulse frequency mode of operation having substantially constant percentage output ripple...
A method includes receiving an input voltage at a voltage regulator and generating an output voltage using the voltage regulator, which includes an inductor....
US-8,283,665 Scan paths, stimulus, and header circuitry with command/frame marker outputs
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test...
US-8,283,224 Ammonia pre-treatment in the fabrication of a memory cell
A method of manufacturing a memory cell 200. The method comprises forming a memory stack 215. Forming the memory stack includes pre-treating an insulating layer...
US-8,281,262 Partitioning features of a single IC layer onto multiple photolithographic masks
One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is...
US-8,281,196 Device address port circuitry with local, group, and global outputs
The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without...
US-8,281,194 Scan path switch testing of output buffer with ESD
The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
US-8,280,375 System and method for managing radio link failures
A wireless transmit/receive unit (WTRU) (152) in a wireless communications system includes a transceiver (153) for transmitting and receiving data from a...
US-8,280,331 System and method for tuning FM synthesizer
A device is provided for dividing a clock signal by even and odd integers. The device includes a divider, a delay portion and a duty cycle corrector. The...
US-8,280,183 Noise robust contrast-enhancement engine employing IIR filters
A noise robust contrast-enhancement engine utilizes low-pass infinite-impulse-response filters for enhancing the contrast while preventing noise amplification...
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