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Dynamic optimization of overlap-and-add length
A method of performing overlap-and-add length for zero-padded suffixes. The method includes derotating received information symbol samples. The derotated...
Reduced feedback transmit beamforming
A method and system for reduced feedback transmit beamforming computes a matrix of channel transfer function coefficients. The matrix of channel transfer...
Run length encoding in VLIW architecture
A computer implemented method of video data encoding generates a mask having one bit corresponding each spatial frequency coefficient of a block during...
Efficient implementation of H.264 4 by 4 intra prediction on a VLIW
This invention is useful in video compression standards support a rich set of intra prediction modes. This invention a unique table creation and lookup approach...
Method and structure for SRAM cell trip voltage measurement
A parametric test circuit is disclosed (FIG. 6). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor...
Compensated isolated p-well DENMOS devices
An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the...
Low-power predecoding based viterbi decoding
In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes...
Integrated circuit having electrically isolatable test circuitry
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test....
Source and destination data circuitry coupled to bi-directional TMS lead
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication...
Reduced computation for bit-by-bit password verification in mutual
Authentication methods are provided that allow for superior security, power consumption, and resource utilization over existing authentication methods. By...
Media gateway with overlay channels
A network media gateway is disclosed with a processor configured to include a plurality of decoder channels, a plurality of overlay channels, an overlay...
Base station transmitter for use with an OFDM communications system, a
method of dynamically allocating OFDM...
A base station transmitter for use with an orthogonal frequency division multiplexing (OFDM) communications system, a method of dynamically allocating OFDM...
Margin testing of static random access memory cells
A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so...
Reaction control charge pump, capacitor, and transistor to power lead
The objective of this invention is to provide a motor control device, and a disk drive device using the same, in which during emergency operation it is possible...
Processing image frames in different formats with reduced memory
requirements in digital still cameras
In a digital still camera, pixel values representing an image frame in a first format are stored in a memory. The pixel values of the image frame in the first...
Circuitry and method for precision amplitude control in quartz and MEMS
An oscillator includes oscillator circuitry (8) including a transconductance stage (2) and a resonator (3). A comparator (10) produces first (CLK) and second...
High speed fully differential resistor-based level formatter
A level formatter is provided that has differentially coupled closed loop current sources, each configured to precisely establish a current proportional to a...
High voltage latching and DC restoration isolation and level shifting
method and apparatus
A device and method for dc isolation and level shifting includes a driver circuit powered by a first voltage range, a capacitor connected to the driver circuit,...
Deconvolution-based capacitive touch detection circuit and method
A capacitance measuring system includes analog-digital circuitry (15) coupled to row conductors (2i) and column conductors (3i) of a touch screen panel (13A)...
Quantized voltage feed-forward a power factor correction controller
A quantized voltage feed-forward (QVFF) circuit and integrated circuits using this technique. The QVFF circuit includes a plurality of comparators in...
Integrated circuit having TSVS including hillock suppression
A method for fabricating integrated circuit (ICs) having through substrate vias (TSVs) includes forming active circuit elements on a semiconductor wafer and...
Semiconductor package having buss-less substrate
A ball grid array device with an insulating substrate (110) having metal traces (106, for example copper, about 18 .mu.m thick) with sidewalls (108) at right...
IC die having TSV and wafer level underfill and stacked IC devices
comprising a workpiece solder connected to...
A method of forming integrated circuit (IC) die configured for attachment to another die or a package substrate, and stacked IC devices therefrom. At least one...
Dual capillary IC wirebonding
The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual...
Progressively programming flash memory while maintaining constant error
In an embodiment, the invention provides a method for programming flash memory while maintaining a constant error correction term. A data field and forcing bits...
Compare circuit having inputs from scan registers and flip-flops
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device...
Shadow protocol circuit having full and reduced pin select outputs
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced...
An electronic device comprises a processing stage, a JTAG port including a test data input pin (TDI), a test data output pin (TDO), a test mode select pin...
Adaptor detecting sequence on TMS and coupling TAP to TCK
A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and...
Sending packets of CELP and important information from an IC
Packets of real-time information are sent with a source rate greater than zero kilobits per second, and a time or path or combined time/path diversity rate...
Protecting uplink transmissions in coexisting wireless networks
A system and method for protecting a wireless device including co-located network transceivers from uplink starvation are disclosed herein. A wireless device...
One aspect of the invention includes a communication system that includes a tone generator configured to generate a first tone, a second tone, and a third tone....
Controller integrated audio codec for advanced audio distribution profile
audio streaming applications
A novel and useful apparatus for and method of integrating the advanced audio distribution profile (A2DP) audio codec into a Bluetooth controller for audio...
Systems and methods for N-dimensional leaf-node prediction for MIMO
Embodiments achieve favorable performance-complexity trade-offs in MIMO detection for three or more channel inputs. Some embodiments describe systems and...
Wireless communications with efficient channel coding
A data encoding algorithm can be used (120) to generate overhead bits from original data bits, and the original data bits and overhead bits can be transmitted...
Data and control multiplexing in PUSCH in wireless networks
Transmission of information in a wireless network is performed by allocating a channel from a transmitter to a receiver. The channel has at least one time slot...
Surge current detection in a switch by detecting change in a duty cycle
An embodiment of the invention provides a surge current protection circuit. The surge current protection circuit comprises a peak current detector and a current...
Reduced-switching dynamic element matching apparatus and methods
Apparatus and methods disclosed herein operate to reducing switching artifacts associated with dynamic element matching by sorting a set of unit elements to...
INL correction circuitry and method for SAR ADC
INL error in a SAR ADC (10) is reduced by providing correction capacitors (11B) each having a first terminal connected to a conductor (13) which is also...
Low power digital phase lock loop circuit
A digital phase lock loop circuit, where under certain conditions the phase error is derived from phase comparison between a reference clock edge and the next...
Battery end-point voltage detection method and battery end-point voltage
Battery driven display device includes a battery, first and second comparators, non-volatile memory, controller driven by the voltage of the battery, and...
Reference voltage generator with bootstrapping effect
An integrated electronic device for generating a reference voltage. The circuitry has a bias current generator for generating a first bias current, a diode...
Low-power feedback and method for DC-DC converters and voltage regulators
for energy harvesters
A converter (10) for converting a first DC voltage (V.sub.DD) to a second DC voltage (V.sub.OUT) includes an output stage (40) for producing the second DC...
Packaged electronic devices having die attach regions with selective thin
A packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon...
System and method of identifying and preventing security violations within
a computing system
A system and method of identifying and preventing security violations within a computing system. Some exemplary embodiments may be a method comprising...
Secure time/date virtualization
A system is provided that includes a processor and a system memory coupled to the processor, the system memory stores at least one application for execution by...
Budgeting electromigration-related reliability among metal paths in the
design of a circuit
Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter...
TAP state count specifying advanced mode command and command data
A method comprises performing at least one zero-bit scan across an interface link. The at least one zero-bit scan defines a command window. The method further...
Pass/fail scan memory with AND, OR and trinary gates
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
Methods and systems to align wafer signatures
One embodiment relates to a computer method for aligning wafers processed in a semiconductor fabrication facility. In the method, a first arrangement of dies...