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Patent # Description
US-8,959,452 Method, system and computer program product for receiving information from a user
A window is displayed on a display device. The window includes at least first and second portions thereof. In response to a user selecting the first portion of...
US-8,959,396 Commandable data register control router connected to TCK and TDI
The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to...
US-8,959,339 Method and system for preventing unauthorized processor mode switches
A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing...
US-8,959,311 Methods and systems involving secure RAM
A system is provided that includes a processor and a random access memory (RAM) coupled to the processor. The RAM is divided into public RAM and secure RAM. The...
US-8,958,504 Carrier recovery in amplitude and phase modulated systems
A method is provided. A multi-amplitude signal is received and downconverted so as to generate I and Q signals using a local oscillator signal. The I and Q...
US-8,958,464 PHY payload over multiple tone masks using single tone mask PHY header information
A method of powerline communications (PLC) includes compiling a data frame for physical layer (PHY) by a first communications device at a first communications...
US-8,958,356 Routing protocols for power line communications (PLC)
Systems and methods for routing protocols for power line communications (PLC) are described. In some embodiments, a method may include transmitting a one-hop...
US-8,958,254 High performance two-port SRAM architecture using 8T high performance single port bit cell
An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read...
US-8,957,525 3D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
A standard memory chip (150) is vertically assembled with two processor chips (130, 140) of split architecture by means of a small silicon interposer (120)...
US-8,954,809 Method for generating descriptive trace gaps
A method of managing a debug trace data stream by detecting conditions where the trace data generated exceeds the available transmission bandwidth, and...
US-8,953,079 System and method for generating 360 degree video recording using MVC
The present invention provides a system and method for combining asymmetrical camera views from a front racing and a back facing camera. Resizing and quality...
US-8,948,293 Downlink multiple input multiple output enhancements for single-cell with remote radio heads
A base station selects a subset of at least one geographically separated antennas for each of the plurality of user equipments. The base station forms at least...
US-8,948,274 Enabling co-existence among power line communication (PLC) technologies
Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC...
US-8,948,271 Method and apparatus for a low complexity transform unit partitioning structure for HEVC
A method and apparatus for a low complexity transform unit partitioning structure for High Efficiency Video Coding (HEVC). The method includes determining...
US-8,947,475 Spatially multiplexed pulse width modulation
A process of operating a PWM display system wherein some display data bits are assigned substantially equal time weights. Display data codewords are defined for...
US-8,947,118 Defect detection in integrated circuit devices
In a method of testing integrated circuit devices, a parameter, such as initial voltage may first be measured. A low pass filter operation may be applied to the...
US-8,947,057 Inverting buck-boost using single-inductor boost and charge pump with a grounded switch
The disclosed methodology for buck-boost inverted voltage conversion uses a boost stage coupled to a charge pump stage at a switch node controlled by a...
US-8,946,880 Packaged semiconductor device having multilevel leadframes configured as modules
A semiconductor system (100) has a first planar leadframe (101) with first leads (102) and pads (103) having attached electronic components (120), the first...
US-8,946,805 Reduced area single poly EEPROM
A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the...
US-8,945,999 SRAM cell with different crystal orientation than associated logic
An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one...
US-8,945,986 Electronic assembly with three dimensional inkjet printed traces
One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate...
US-RE45,359 Integrated circuit for clock generation for memory devices
A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data...
US-8,943,392 Viterbi butterfly operations
A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer....
US-8,943,376 Position independent testing of circuits
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing...
US-8,943,369 Prioritizing stall/reason data into priority information stream over PC/data trace
An electronic tracing process includes packing both stall (215) and reason (219) data into a single high priority timing information stream. An integrated...
US-8,943,305 Frame structure for medium access in body area networks (BAN)
A system and method for providing a variety of medium access and power management methods are disclosed. A defined frame structure allows a hub and a node to...
US-8,943,248 Method and system for handling discarded and merged events when monitoring a system bus
A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the...
US-8,942,643 Routing for a package antenna
An apparatus is provided. A plurality of transceiver antennas are arranged to form a phased array, where each antenna include a differential transmit antenna...
US-8,942,333 Apparatus and methods for clock alignment for high speed interfaces
Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY...
US-8,942,164 Differential CQI for OFDMA systems
Embodiments of the present disclosure provide a feedback generator, a feedback decoder and methods of operating a feedback generator and decoder. In one...
US-8,942,145 Implant access in the medical implant communications service band
A system and method for providing communications between a hub (medical controller) and a node (an implant) are disclosed. The hub selects an operating channel...
US-8,942,080 Transmission of bundled ACK/NAK bits
This invention is applicable to wireless communication between a user equipment (UE) and a base station using frames where at least one uplink (UL) is assigned...
US-8,942,049 Channel hot carrier tolerant tracking circuit for signal development on a memory SRAM
An embodiment of the invention discloses an electronic device for reducing degradation in NMOS circuits in a tracking circuit. A first multiplexer selects,...
US-8,941,517 Method for calbrating a pipelined continuous-time sigma delta modulator
Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating...
US-8,941,473 Electronic device and method for RFID
An electronic device comprising a first node to be coupled to a first antenna, a second node coupled to a second antenna, a third node to be coupled to a third...
US-8,941,417 Output driver for energy recovery from inductor based sensor
A system for recovering energy from a sensor couples a battery to an inductive device in the sensor for a period of time, such that a current flows through the...
US-8,941,414 Track-and-hold circuit with low distortion
A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input...
US-8,941,400 Parallel scan paths with three bond pads, distributors and collectors
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-8,941,366 DC-DC converter having an output that is a measure of the efficiency of the converter
A DC-DC converter includes efficiency reporting circuitry having an output that is a measure of efficiency. In an example, the DC-DC converter has an input...
US-8,941,365 Methods and apparatus to improve power factor at light-load
Methods and apparatus to improve power factor are disclosed. An example method includes detecting power provided to a power factor corrector; detecting power...
US-8,941,181 Compensated well ESD diodes with reduced capacitance
An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance,...
US-8,941,109 Test output buffer functional output input, test output, enable input
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding...
US-8,940,612 Poly resistor for metal gate integrated circuits
An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in...
US-8,940,598 Low temperature coefficient resistor in CMOS flow
A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of...
US-8,940,593 Enhancement-mode GaN MOSFET with low leakage current and improved reliability
An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO.sub.2/Si.sub.3N.sub.4 gate insulation layer...
US-8,940,093 Method of controlling an epitaxial growth process in an epitaxial reactor
A method of controlling an epitaxial growth process in an epitaxial reactor. The method includes optimizing the thermocouple offset parameter for a second run...
US-8,938,739 Resource sharing aware task partitioning for multiprocessors
A multi processor task allocation method is described that considers task dependencies while performing task allocation in order to avoid blocking of a task's...
US-8,938,652 Addressable tap domain selection circuit with AUXI/O, TDI/TDO, TMS/TRCK leads
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-8,938,651 Blocking the effects of scan chain testing upon a change in scan chain topology
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain...
US-8,938,649 Debug trace stream timestamping using upstream correlation
A method of correlating the timing of multiple interleaved trace data streams. A Time Stamp Trace stream logic monitors the event trace stream for a...
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