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Patent # Description
US-8,207,764 Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high...
An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop,...
US-8,207,559 Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures
In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material,...
US-8,205,145 High-speed add-compare-select (ACS) circuit
A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional...
US-8,205,125 Enhanced control in scan tests of integrated circuits with partitioned scan chains
A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an...
US-8,205,057 Method and system for integrated pipeline write hazard handling using memory attributes
In a system and method for write hazard handling a memory management unit policy is pre-computed for a write request using an address that is at least one clock...
US-8,204,753 Stabilization and glitch minimization for CCITT recommendation G.726 speech CODEC during packet loss scenarios...
This invention decoded encoded speech using alternative parameters upon detection of a lost packet. Upon detection of a first good packet following packet loss,...
US-8,204,470 Predecoding for joint processing coordinated multi-point transmission
This invention is a method of predecoding for joint processing coordinated multi-point transmission. The invention identifies for a particular transmission the...
US-8,203,867 8T SRAM cell with one word line
An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and...
US-8,203,786 Method and system for screen attachment
Methods and apparatus for a display system include a frame and one or more screen panels. Each panel has an inwardly disposed face and an outwardly disposed...
US-8,203,776 Planarity of pixel mirrors
A method of forming an electronic device includes providing a patterned lower metal layer over a substrate and a first sacrificial layer there between. A second...
US-8,203,384 Amplifier
An amplifier has first and second differential outputs connected to first and second ends of one side of a balun. A second side of the balun, inductively...
US-8,203,383 Reducing the effect of bulk leakage currents
A current mirroring circuit is provided. The circuit generally comprises a current source; a first drain extended (DE) MOS transistor, a second DE MOS...
US-8,203,323 Switched mode power supply with current sensing
An electronic device for switched mode DC-DC conversion is provided that includes a stage for sensing an output current causing a voltage difference between a...
US-8,203,197 Thermally enhanced semiconductor devices
Thermal communication of matched transistors formed in lower electrical resistance subregions of first and second active substrate regions is provided by...
US-8,202,773 Engineered oxygen profile in metal gate electrode and nitrided high-k gate dielectrics structure for high...
A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS...
US-8,202,433 Reducing adherence in a MEMS device
In one embodiment, an apparatus for reducing adherence in a micro-electromechanical system (MEMS) device comprises a substrate. A MEMS is disposed outwardly...
US-8,201,036 IC with test and shadow access ports and output circuit
The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform...
US-8,201,004 Entry/exit control to/from a low power state in a complex multi level memory system
An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller...
US-8,200,954 Multi-stage boot pin sampling
In accordance with embodiments, a method for configuring an electronic device during a power-on sequence includes sampling a boot pin state multiple times. The...
US-8,200,479 Method and system for asymmetric independent audio rendering
Methods and mobile devices are provided for asymmetric independent processing of audio streams in a system on a chip (SOC). More specifically, independent audio...
US-8,200,461 Small-signal stability analysis at transient time points of integrated circuit simulation
Simulation method and system for analyzing the stability of a modeled electronic circuit. Simulation of the transient response to a desired input stimulus is...
US-8,199,706 Random access design for high doppler in wireless networks
UE-initiated accesses within a cellular network are optimized to account for Doppler shift. A user equipment (UE) receives information that designates a...
US-8,199,666 Transmission of acknowledge/not-acknowledge with repetition
In ACK/NAK responses with repetition, the ACK/NAK response from the user equipment to a Physical Downlink Shared CHannel (PDSCH) transmission is repeated in...
US-8,199,577 Ripple programming of memory cells in a nonvolatile memory
An electrically erasable programmable read-only memory (EEPROM) with a ripple programming mode. Memory cells in an the EEPROM array include floating-gate...
US-8,199,037 ADC channel selection and conversion
A microcontroller includes a microcontroller core and an analog-to-digital converter ("ADC") coupled to said microcontroller core. The ADC has multiple input...
US-8,198,932 Voltage generating circuit for an attenuator
A circuit includes a digital-to-analog converter (DAC), coupled to a power supply, that provides a first current at a first output terminal of the DAC and a...
US-8,198,918 Capacitor cell supporting circuit operation at higher-voltages while employing capacitors designed for lower...
An integrated circuit (IC) includes a functional circuit and a capacitor cell. The functional circuit may operate with one of two power supply voltages. The...
US-8,198,912 Driver circuit correction arm decoupling resistance in steady state mode
A voltage-mode driver circuit supporting pre-emphasis is implemented to include a driver arm and a correction arm. The driver arm receives an input signal, and...
US-8,198,873 Power converter
This invention relates to a power converter (1) comprising a converter input (3), a converter output, a power factor pre-regulation stage (5), an isolation...
US-8,198,184 Method to maximize nitrogen concentration at the top surface of gate dielectrics
An integrated circuit having a gate dielectric layer (414, 614, 814) having an improved nitrogen profile and a method of fabrication. The gate dielectric layer...
US-8,198,105 Monitor for variation of critical dimensions (CDs) of reticles
The present invention provides a reticle 100 for use in a lithographic process. The reticle, in one embodiment, includes a patterned layer 110 located over a...
US-8,196,076 Optimal flow in designing a circuit operable in multiple timing modes
A design approach provided according to an aspect of the present invention consolidates the constraint files of respective modes into consolidated information...
US-8,195,994 Inverter and TMS clocked flip-flop pairs between TCK and reset
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-8,195,972 Jitter precorrection filter in time-average-frequency clocked systems
Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals....
US-8,195,932 Authentication and encryption for secure data transmission
A system and method for authenticating and encrypting messages for secure transmission is disclosed. A frame to be transmitted between devices comprises a frame...
US-8,195,109 Single ended switched power amplifier with tuned load coupling block
A switched power amplifier contained in a circuit is implemented to receive a single-ended input signal and generate a single-ended output signal, the...
US-8,195,103 Linearization of a transmit amplifier
A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to...
US-8,195,034 Low complexity event detection for video programs
A video processing method for detecting significant events from a video program includes computing short-time sub-band energies in the audio for plural audio...
US-8,195,002 Adaptive post-deringing filter on compressed images
An image filtering method, apparatus and system, wherein the method comprising the steps of detecting at least one portion of an edge, wherein the portion of...
US-8,194,892 Output coupling capacitor free audio power amplifier dynamically configured for speakers and headphones with...
First and second channel bridge amplifiers are dynamically configured to drive either speakers or headphones. The first channel bridge amplifier includes a...
US-8,194,188 Displaying image frames in combination with a subpicture frame
An aspect of the present invention reduces memory accesses while forming combined images of a subpicture frame with each of a sequence of image frames. In an...
US-8,194,141 Method and apparatus for producing sharp frames with less blur
A method and apparatus motion triggered image stabilization. The method includes computing projection vector for at least a portion of a frame of an image using...
US-8,193,980 Doppler and code phase searches in a GNSS receiver
According to an aspect of the present invention, each correlation block in a Global Navigation Satellite System (GNSS) receiver is designed to examine a certain...
US-8,193,958 Signal regenerator
Pulses that are generated from multiple analog input signals are sampled, and signal elements contained in the analog signals are extracted accurately using the...
US-8,193,841 Electronic device for power-on-reset
An electronic device is provided that includes a power-on-reset (POR) circuit. The POR circuit includes a trigger stage configured to change an output if a...
US-8,193,832 Arbiter array using two-dimensional address decoding
A system comprises a plurality of requesting agents and granting agents configured in an array of rows and a plurality of columns. Corresponding to each...
US-8,193,798 Buck regulators with adjustable clock frequency to achieve dropout voltage reduction
A method includes generating a drive signal for a transistor in a switching regulator. The drive signal turns the transistor on and off to generate a regulated...
US-8,193,644 Pop precursor with interposer for top package bond pad pitch compensation
An electronic assembly adapted for forming package on package (PoP) devices includes a package substrate having a molded IC die thereon that defines a mold cap...
US-8,193,603 Semiconductor structure and method of forming the semiconductor structure that provides two individual...
A semiconductor structure is formed in the metal interconnect structure of an integrated circuit in a method that provides either two individual resistors that...
US-8,193,602 Schottky diode with control gate for optimization of the on state resistance, the reverse leakage, and the...
A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated...
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