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Patent # Description
US-8,217,674 Systems and methods to test integrated circuits
Open and short systems and methods for testing integrated circuits are disclosed. An example implementation includes engaging an integrated circuit testing...
US-8,217,636 Circuit and method for reducing output voltage transients in a voltage mode buck converter
A voltage control mode buck converter circuit includes a feedback amplifier providing a comparison signal and a storage circuit in communication with the...
US-8,217,615 Current sensing in a disk-drive spindle motor
One embodiment of the invention includes a disk-drive spindle motor power regulator system. The system includes a switching system comprising at least one power...
US-8,217,586 Apparatus and method for dimming a backlight with pseudo-random phase delay
A method for generating an actuation signal for a light source is provided. A random phase delay for each period of an input signal is generated, where each...
US-8,217,453 Bi-directional DMOS with common drain
A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series...
US-8,217,426 Bipolar transistors with resistors
Complementary MOS (CMOS) integrated circuits include MOS transistors, resistors and bipolar transistors formed on a common substrate. An emitter region of a...
US-8,217,322 Temperature responsive back bias control for integrated circuit
The present invention provides a thermostatic biasing controller for use with an integrated circuit. In one embodiment, the thermostatic biasing controller...
US-8,216,945 Wafer planarity control between pattern levels
A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of...
US-8,216,913 Strain modulation in active areas by controlled incorporation of nitrogen at si-SiO2 interface
Adding nitrogen to the Si--SiO2 interface at STI sidewalls increases carrier mobility in MOS transistors, but control of the amount of nitrogen has been...
US-8,216,903 SRAM cell with asymmetrical pass gate
A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a...
US-8,216,885 Methods and devices for manufacturing cantilever leads in a semiconductor package
A method of manufacturing a semiconductor package includes providing a metallic leadframe having a plurality of cantilever leads and a mounting area for...
US-8,214,705 IC with first and second external register present leads
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test...
US-8,213,865 Methods and apparatus to reduce power consumption in a wireless device
Methods and apparatus to reduce power consumption in a wireless device are disclosed. An example method includes sensing movement of the wireless device via a...
US-8,213,741 Method to generate thumbnails for digital images
This invention generates object-focused thumbnails from input images reflecting the mood and intention of the user, based on the original high-resolution...
US-8,213,695 Device and software for screening the skin
The present invention provides devices for screening the skin of an individual in real time using a region-fusion based segmentation with narrow band graph...
US-8,213,638 Equalizer
Methods and apparatus to provide an equalizer for analog adaptive control are disclosed. An example equalizer described herein includes a high frequency...
US-8,213,622 Binaural sound localization using a formant-type cascade of resonators and anti-resonators
This invention is a method for binaural localization using a cascade of resonators and anti-resonators to implement an HRTF (head-related transfer function)....
US-8,213,555 Methods and apparatus to improve distortion performance and direct current (DC) offset cancellation in receivers
Methods, apparatus, and articles of manufacture are described for improving distortion performance and for direct current offset cancellation in receivers. In...
US-8,213,515 Interpolated skip mode decision in video compression
A video encoding method determines the best video encoding mode for a macroblock in the SKIP mode and comparing this cost with other modes. This avoids...
US-8,213,511 Video encoder software architecture for VLIW cores incorporating inter prediction and intra prediction
This invention is a method of video encoding. The number N macroblocks stored in a temporary buffer depends upon an estimated number of motion vectors. N...
US-8,213,367 Methods for dimensioning the control channel for transmission efficiency in communication systems
Embodiments of the invention provide methods for optimizing the spectral efficiency of control channel transmissions carrying scheduling assignments from a...
US-8,212,720 Detecting lack of movement to aid GNSS receivers
Embodiments of the invention provide a method of detecting movement to aid GNSS receivers. By detecting when the user is stationary, the Doppler frequency...
US-8,212,705 Pipeline ADC
Pipeline analog-to-digital converters (ADCs) are used in many applications, but because of the configuration, components may be idled, which wastes power. Here,...
US-8,212,644 Transformer assembly
The present invention relates to a transformer assembly (1) and a process for manufacturing same. The transformer (1) comprises a primary winding (5) wound on a...
US-8,212,611 Switching core layout
Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local...
US-8,212,606 Apparatus and method for offset drift trimming
An apparatus is provided that includes a drift trimming stage that includes a first current source providing a current with a first temperature dependency and a...
US-8,212,400 Multi-rail power-supply system
A multi-rail power-supply system provides power to circuitry requiring at least one additional rail between a high and a low-voltage rail. The system comprises...
US-8,211,794 Properties of metallic copper diffusion barriers through silicon surface treatments
In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of...
US-8,211,773 SRAM cell with asymmetrical pass gate
A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a...
US-8,209,650 Method and system for entry and verification of parasitic design constraints for analog integrated circuits
A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with...
US-8,209,575 MIMO hybrid-ARQ using basis hopping
A Hybrid Automatic Retransmission Request (H-ARQ) technique is provided for Multi-Input Multi-Output (MIMO) systems. The technique changes the basis (V) upon...
US-8,208,759 Light valve projection of visible image correlated with non-visible image
An image system comprises a light valve and an image capturing unit. The light valve comprises an array of individually addressable pixels capable of generating...
US-8,208,558 Transform domain fast mode search for spatial prediction in advanced video coding
This invention is method for determining direction mode for an image block in intra prediction of video frames. The method calculates a plurality of energy...
US-8,207,831 Transponder demodulator for a low antenna limiter threshold
An RFID transponder having an antenna for receiving an RF signal including an amplitude modulated downlink data signal, and a demodulating stage coupled to the...
US-8,207,764 Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high...
An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop,...
US-8,207,559 Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures
In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material,...
US-8,205,145 High-speed add-compare-select (ACS) circuit
A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional...
US-8,205,125 Enhanced control in scan tests of integrated circuits with partitioned scan chains
A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an...
US-8,205,057 Method and system for integrated pipeline write hazard handling using memory attributes
In a system and method for write hazard handling a memory management unit policy is pre-computed for a write request using an address that is at least one clock...
US-8,204,753 Stabilization and glitch minimization for CCITT recommendation G.726 speech CODEC during packet loss scenarios...
This invention decoded encoded speech using alternative parameters upon detection of a lost packet. Upon detection of a first good packet following packet loss,...
US-8,204,470 Predecoding for joint processing coordinated multi-point transmission
This invention is a method of predecoding for joint processing coordinated multi-point transmission. The invention identifies for a particular transmission the...
US-8,203,867 8T SRAM cell with one word line
An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and...
US-8,203,786 Method and system for screen attachment
Methods and apparatus for a display system include a frame and one or more screen panels. Each panel has an inwardly disposed face and an outwardly disposed...
US-8,203,776 Planarity of pixel mirrors
A method of forming an electronic device includes providing a patterned lower metal layer over a substrate and a first sacrificial layer there between. A second...
US-8,203,384 Amplifier
An amplifier has first and second differential outputs connected to first and second ends of one side of a balun. A second side of the balun, inductively...
US-8,203,383 Reducing the effect of bulk leakage currents
A current mirroring circuit is provided. The circuit generally comprises a current source; a first drain extended (DE) MOS transistor, a second DE MOS...
US-8,203,323 Switched mode power supply with current sensing
An electronic device for switched mode DC-DC conversion is provided that includes a stage for sensing an output current causing a voltage difference between a...
US-8,203,197 Thermally enhanced semiconductor devices
Thermal communication of matched transistors formed in lower electrical resistance subregions of first and second active substrate regions is provided by...
US-8,202,773 Engineered oxygen profile in metal gate electrode and nitrided high-k gate dielectrics structure for high...
A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS...
US-8,202,433 Reducing adherence in a MEMS device
In one embodiment, an apparatus for reducing adherence in a micro-electromechanical system (MEMS) device comprises a substrate. A MEMS is disposed outwardly...
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