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Patent # Description
US-1,006,8631 Dual mode memory array security apparatus, systems and methods
Read-only ("RO") data consisting of a physically unclonable function ("PUF") pattern is written to a ferroelectric random-access memory ("FRAM") memory array....
US-1,006,8512 Modulator for a MUX LCD
A modulator can include a common signal modulator that outputs a predetermined number of common signals to a multiplexer interface liquid crystal display (MUX...
US-1,006,7221 Interference detection in a frequency modulated continuous wave (FMCW) radar system
A frequency modulated continuous wave (FMCW) radar system is provided that includes a receiver configured to generate a digital intermediate frequency (IF)...
US-1,006,7201 Wiring layout to reduce magnetic field
A magnetic sensor has a circuit segment with a quadrupole region. The quadrupole region includes a supply line, a first return line and a second return line,...
US-1,006,7188 Test port, decompressor, compactor with I/O on opposite die surfaces
A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals...
US-1,006,6799 Pixelated projection for automotive headlamp
An automotive headlamp is provided that includes a digital micromirror device (DMD) headlight module, the DMD headlight module including a DMD, a white light...
US-1,006,4218 Channel hopping aware channel access and re-transmission
A method of channel access for a radio device in an asynchronous channel hopping wireless network. A backoff time is set from an Interference Avoidance Delay...
US-1,006,4202 Assigning frequency sub-bands for LTE transmissions to provide improved performance and reduced interference
Disclosed embodiments include a base station. The base station includes a receiver that receives a channel quality report identifying one or more particular...
US-1,006,3871 Saving minimum macroblock data for subsequent encoding of other macroblocks
A video encoder including a first buffer containing a plurality of data values defining a macroblock of pixels of a video frame. The video encoder also includes...
US-1,006,3866 Multi-pass video encoding
Systems, methods and computer readable mediums are presented for encoding a stream of input video frames, in which the input video frames are down sampled and...
US-1,006,3170 Methods and apparatus for robust and efficient stepper motor BEMF measurement
In a described example an apparatus includes: an FET driver circuit configured to supply current to a coil in a stepper motor, the FET driver circuit configured...
US-1,006,3143 Fixed frequency DC-DC converter
In a power converter system, circuitry generates first and second PWM signals during a PWM cycle for controlling application of power to an inductor. Circuitry...
US-1,006,2777 Trench gate trench field plate vertical MOSFET
A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the...
US-1,006,2624 Silicon package for embedded semiconductor chip and power converter
A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second...
US-1,006,2451 Background memory test apparatus and methods
A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus ("BGMTA")) are located on-chip...
US-1,006,2448 Zero bias fuse cell
A circuit includes a fuse cell with a current mirror. The first leg of the current minor includes first and second N-type transistors coupled in series between...
US-1,006,2443 Memory circuit with leakage compensation
A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the...
US-1,006,1675 Streaming engine with deferred exception reporting
This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming...
US-1,006,1028 Time-of-flight (TOF) assisted structured light imaging
A method for computing a depth map of a scene in a structured light imaging system including a time-of-flight (TOF) sensor and a projector is provided that...
US-1,006,1016 Phase noise measurement in a cascaded radar system
A cascaded radar system is provided that includes a master radar system-on-a-chip (SOC) with transmission signal generation circuitry and a slave radar SOC...
US-1,006,1015 Multi-chip transceiver testing in a radar system
A radar system is provided that includes a first radar transceiver integrated circuit (IC) including transmission signal generation circuitry operable to...
US-1,006,0980 Two signal JTAG with TLM, scan domain and diagnostics domain
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-1,006,0979 Generating multiple pseudo static control signals using on-chip JTAG state machine
A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A...
US-1,006,0977 First, second divided scan paths, adaptor, generator and compactor circuitry
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-1,006,0959 Capacitive sensing
A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by...
US-1,006,0956 Detecting power supply sag in an integrated circuit
An integrated circuit is provided with a voltage sag detector (VSD) within the integrated circuit package. The VSD is coupled to a voltage reference and to the...
US-1,006,0881 Surface sensing method for corrosion sensing via magnetic modulation
A method includes pulsating a magnetic field at a first location associated with an external surface of a wall containing magnetic material. The method also...
US-1,006,0864 Multi-sampling in X-ray receiver for noise reduction
The disclosure provides a receiver with reduced noise. The receiver includes a photodiode that generates an input signal in response to received light pulses. A...
US-1,005,7959 Power over ethernet powered device having automatic power signature
In a Power over Ethernet (PoE) system, a Powered Device (PD) having circuitry to measure the load current from a Power Sourcing Equipment (PSE) in the PD....
US-1,005,7745 PHY layer parameters for body area network (BAN) devices
In at least some embodiments, a communication device includes a transceiver with a physical (PHY) layer. The PHY layer is configured for body area network (BAN)...
US-1,005,6911 Continuous coarse-tuned phase locked loop
In some embodiments, a phase-locked loop (PLL) system comprises a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a...
US-1,005,6882 Ultra-low power static state flip flop
At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a...
US-1,005,6830 Control scheme for DC-DC power converters with ultra-fast dynamic response
Methods and apparatus for determining a value of a pulse-width modulation (PWM) signal with which to drive a power stage of a DC-to-DC voltage converter having...
US-1,005,6819 Predicting the timing of current phases of a DC-DC converter
A timing regulation circuit includes a fixed and tunable timer. A current source generates a source current I.sub.1 proportional to an inductor voltage...
US-1,005,6151 Multi-read only memory finite state machine
A multi-read only memory (ROM) state machine circuit includes first and second ROMs (or other memory types), each ROM addressable as a plurality of rows. Each...
US-1,005,5674 Confidence estimation for optical flow
A confidence map for optical flow gradients is constructed calculating a set of gradients for each pixel of an image, filtering said gradients and extracting...
US-1,005,4969 Monolithic reference architecture with burst mode support
A reference circuit may include a bandgap reference stage, a filter stage, and a buffer stage. The reference stage may be configured to generate a reference...
US-1,005,4639 Test access port and TCK inverter for shadow access port
The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform...
US-1,005,4638 TCK, TMS(C) clock, gating circuitry providing selection and deselection outputs
Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path....
US-1,005,4633 Shadow protocol detection, address circuits with command shift, update registers
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced...
US-1,005,4622 Method and apparatus for LRA real time impedance tracking and BEMF extraction
A method, apparatus and a system for a Linear Resonant Actuator (LRA) real time impedance tracking. The method includes extracting the Back Electro-Motive Force...
US-1,005,1450 Bluetooth data forwarding
A Bluetooth (BT) device includes a host processor and a BT controller coupled by a Host Controller Interface (HCI) including a Host Controller Transport Layer...
US-1,005,0878 Network communication system with node energy reduction packet protocol
A method of communicating a packet between a first node and a second node, the packet comprising a data payload and a portion of information preceding the data...
US-1,005,0814 CTLE gear shifting to enable CDR frequency lock in wired communication
A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method...
US-1,005,0636 Methods and apparatus to reduce non-linearity in analog to digital converters
Methods and apparatus for reducing non-linearity in analog to digital converters are disclosed. An example apparatus includes an analog-to-digital converter to...
US-1,005,0632 Counter-based SYSREF implementation
A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be...
US-1,005,0617 On chip redundant system reset for out of context functional safety SoC
A functional safety Power on Reset system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented...
US-1,005,0612 Resistor-capacitor (RC) delay circuit with a precharge mode
A delay circuit includes precharge and discharge transistors configured to receive an input signal. The delay circuit also includes a resistor coupled to the...
US-1,005,0515 Voltage control of flying capacitor in adaptive multilevel converters
In described examples, a DC-DC converter provides electrical power. The converter includes an inductor and a flying capacitor. In response to an input voltage...
US-1,005,0157 Spike implanted Schottky diode
A rectifying diode. The diode comprises a first conductor region and a second conductor region. The diode further comprises a diode conductive path between the...
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