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Patent # Description
US-8,239,673 Methods, apparatus and systems with loadable kernel architecture for processors
A device (200, 2200) for improved security includes a processor (200) and a secure writeable memory (2245) coupled to said processor (200) and including code...
US-8,238,429 Statistically cycle optimized bounding box for high definition video decoding
A method for conserving memory accesses in motion compensation of compressed video gathers a plurality of motion compensation data accesses into a single...
US-8,238,427 Rate distortion optimized adaptive intra refresh for video coding
A method of video coding comprising Intra prediction coding at least a predetermined constant M macroblocks within an ordinary frame. These M macroblocks...
US-8,238,406 Time-hopping sequence for burst mode communications
A method consisting of determining, by a symbol mapper, whether a previous burst position is below a threshold, wherein the previous burst position defines a...
US-8,238,158 Programming of memory cells in a nonvolatile memory using an active transition control
An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of...
US-8,238,061 Printed circuit cable assembly with stiffener portions and flexible portions
A printed circuit cable assembly (PCCA) for a hard disk drive (HDD) is disclosed. The PCCA includes a stiffener portion having an elongated shape that includes...
US-8,238,010 MEMS device for producing a lemniscate pattern to counter zigzag effect
A MEMS device, a printer and a method of printing is presented including providing a light source producing a modulated beam of light, positioning a mirror with...
US-8,237,779 Coding scheme for digital video signals and an image architecture using the same
Video signals in a video stream are encoded by inserting reference signals in the video stream such that the encoded video stream carry both reference signals...
US-8,237,731 System and method for grouped pixel addressing
In accordance with the teachings of the present disclosure, a system and method for displaying an image are provided. In one embodiment, the method includes...
US-8,237,385 Systems and methods for detecting position for a brushless DC motor
A system for determining a commutation state for a brushless DC motor includes a controller configured to control current that is applied to drive each of a...
US-8,236,703 Methods for removing contaminants from aluminum-comprising bond pads and integrated circuits therefrom
Methods for removing contaminants from a semiconductor device that includes a plurality of aluminum-comprising bond pads on a semiconductor surface of a...
US-8,235,532 Color splitting method for light sources
A system comprises two or more light sources comprising a first light source and a second light source, each light source of the two or more light sources...
US-8,234,529 HTMLS with first and second select outputs and enable inputs
An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these...
US-8,234,430 Apparatus and method with controlled switch method
An embedded microcontroller system comprises a central processing unit, a system controller for receiving and handling an interrupt, a register having storage...
US-8,233,573 Dynamic optimization of overlap-and-add length
A method of performing overlap-and-add length for zero-padded suffixes. The method includes derotating received information symbol samples. The derotated...
US-8,233,556 Reduced feedback transmit beamforming
A method and system for reduced feedback transmit beamforming computes a matrix of channel transfer function coefficients. The matrix of channel transfer...
US-8,233,545 Run length encoding in VLIW architecture
A computer implemented method of video data encoding generates a mask having one bit corresponding each spatial frequency coefficient of a block during...
US-8,233,537 Efficient implementation of H.264 4 by 4 intra prediction on a VLIW processor
This invention is useful in video compression standards support a rich set of intra prediction modes. This invention a unique table creation and lookup approach...
US-8,233,341 Method and structure for SRAM cell trip voltage measurement
A parametric test circuit is disclosed (FIG. 6). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor...
US-8,232,158 Compensated isolated p-well DENMOS devices
An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the...
US-8,230,313 Low-power predecoding based viterbi decoding
In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes...
US-8,230,284 Integrated circuit having electrically isolatable test circuitry
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test....
US-8,230,280 Source and destination data circuitry coupled to bi-directional TMS lead
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication...
US-8,230,219 Reduced computation for bit-by-bit password verification in mutual authentication
Authentication methods are provided that allow for superior security, power consumption, and resource utilization over existing authentication methods. By...
US-8,228,980 Media gateway with overlay channels
A network media gateway is disclosed with a processor configured to include a plurality of decoder channels, a plurality of overlay channels, an overlay...
US-8,228,783 Base station transmitter for use with an OFDM communications system, a method of dynamically allocating OFDM...
A base station transmitter for use with an orthogonal frequency division multiplexing (OFDM) communications system, a method of dynamically allocating OFDM...
US-8,228,749 Margin testing of static random access memory cells
A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so...
US-8,228,629 Reaction control charge pump, capacitor, and transistor to power lead
The objective of this invention is to provide a motor control device, and a disk drive device using the same, in which during emergency operation it is possible...
US-8,228,395 Processing image frames in different formats with reduced memory requirements in digital still cameras
In a digital still camera, pixel values representing an image frame in a first format are stored in a memory. The pixel values of the image frame in the first...
US-8,228,130 Circuitry and method for precision amplitude control in quartz and MEMS oscillators
An oscillator includes oscillator circuitry (8) including a transconductance stage (2) and a resonator (3). A comparator (10) produces first (CLK) and second...
US-8,228,108 High speed fully differential resistor-based level formatter
A level formatter is provided that has differentially coupled closed loop current sources, each configured to precisely establish a current proportional to a...
US-8,228,092 High voltage latching and DC restoration isolation and level shifting method and apparatus
A device and method for dc isolation and level shifting includes a driver circuit powered by a first voltage range, a capacitor connected to the driver circuit,...
US-8,228,076 Deconvolution-based capacitive touch detection circuit and method
A capacitance measuring system includes analog-digital circuitry (15) coupled to row conductors (2i) and column conductors (3i) of a touch screen panel (13A)...
US-8,228,045 Quantized voltage feed-forward a power factor correction controller
A quantized voltage feed-forward (QVFF) circuit and integrated circuits using this technique. The QVFF circuit includes a plurality of comparators in...
US-8,227,839 Integrated circuit having TSVS including hillock suppression
A method for fabricating integrated circuit (ICs) having through substrate vias (TSVs) includes forming active circuit elements on a semiconductor wafer and...
US-8,227,298 Semiconductor package having buss-less substrate
A ball grid array device with an insulating substrate (110) having metal traces (106, for example copper, about 18 .mu.m thick) with sidewalls (108) at right...
US-8,227,295 IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to...
A method of forming integrated circuit (IC) die configured for attachment to another die or a package substrate, and stacked IC devices therefrom. At least one...
US-8,225,982 Dual capillary IC wirebonding
The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual...
US-8,225,177 Progressively programming flash memory while maintaining constant error correction codes
In an embodiment, the invention provides a method for programming flash memory while maintaining a constant error correction term. A data field and forcing bits...
US-8,225,158 Compare circuit having inputs from scan registers and flip-flops
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device...
US-8,225,157 Shadow protocol circuit having full and reduced pin select outputs
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced...
US-8,225,155 JTAG mailbox
An electronic device comprises a processing stage, a JTAG port including a test data input pin (TDI), a test data output pin (TDO), a test mode select pin...
US-8,225,126 Adaptor detecting sequence on TMS and coupling TAP to TCK
A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and...
US-8,224,643 Sending packets of CELP and important information from an IC
Packets of real-time information are sent with a source rate greater than zero kilobits per second, and a time or path or combined time/path diversity rate...
US-8,224,378 Protecting uplink transmissions in coexisting wireless networks
A system and method for protecting a wireless device including co-located network transceivers from uplink starvation are disclosed herein. A wireless device...
US-8,224,268 Transmitter linearization
One aspect of the invention includes a communication system that includes a tone generator configured to generate a first tone, a second tone, and a third tone....
US-8,224,247 Controller integrated audio codec for advanced audio distribution profile audio streaming applications
A novel and useful apparatus for and method of integrating the advanced audio distribution profile (A2DP) audio codec into a Bluetooth controller for audio...
US-8,223,870 Systems and methods for N-dimensional leaf-node prediction for MIMO detection
Embodiments achieve favorable performance-complexity trade-offs in MIMO detection for three or more channel inputs. Some embodiments describe systems and...
US-8,223,867 Wireless communications with efficient channel coding
A data encoding algorithm can be used (120) to generate overhead bits from original data bits, and the original data bits and overhead bits can be transmitted...
US-8,223,808 Data and control multiplexing in PUSCH in wireless networks
Transmission of information in a wireless network is performed by allocating a channel from a transmitter to a receiver. The channel has at least one time slot...
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