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Patent # Description
US-8,143,955 Oscillator circuit for radio frequency transceivers
Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a...
US-8,143,944 Method and apparatus for sensing a current for varying impedance loads
Recently, there has been an increased desire to measure load currents of class-D amplifiers to improve performance. The traditional solution has been to include...
US-8,143,812 Clamp to enable low voltage switching for high voltage terminal applications
An output stage for an LED driver is provided. In particular, a low voltage clamp, which uses several cascode circuits, is provided to protect low voltage...
US-8,143,704 Electronic assemblies including mechanically secured protruding bonding conductor joints
An electronic assembly includes an IC die including a semiconductor top surface having active circuitry thereon and a bottom surface, and at least one...
US-8,141,786 Thin smart card module having strap on carrier
A Smart Card module with flip-assembled chip (101) on a metallic strap (112) adhering to an insulating substrate (111). Chip (101) is in the gap (122) of a...
US-8,140,944 Interleaver design with unequal error protection for control information
For transmission of a block of control information within a wireless network, the control information is interleaved to form an ordered set of control bits,...
US-8,140,926 Die selectively connecting TAP leads to second die
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP...
US-8,140,924 Selectively accessing test access ports in a multiple test access port environment
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-8,140,881 Circuitry and method for detection of network node aging in communication networks
The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a...
US-8,140,095 Resolving encoding dependencies for data bursts
A system comprises a receiver and a transmitter in wireless communication with the receiver. The receiver receives from the transmitter multiple bursts of data...
US-8,140,031 Transmitter built-in production line testing utilizing digital gain calibration
A novel and useful self-calibration based production line testing mechanism utilizing built-in closed loop measurements in the radio to calibrate the output...
US-8,140,027 Automatic frequency tuning system and method for an FM-band transmit power amplifier
An automatic frequency tuning system and method for a transmit power amplifier. The transmit power amplifier has an antenna feed line including a series...
US-8,139,871 Circuit and method for adaptive, lossless compression of successive digital data
An image compression and decompression method compresses data based upon the data states, and decompresses the compressed data based upon the codes generated...
US-8,139,851 System and method for local value adjustment
In accordance with the teachings of the present invention, a system and method for local value adjustment are provided. In one embodiment, the method includes...
US-8,139,678 High data rate closed loop MIMO scheme combining transmit diversity and data multiplexing
Closed loop multiple-antenna wireless communications system with antenna weights determined by maximizing a composite channel signal-to-interference-plus-noise...
US-8,139,431 Structure and methods for measuring margins in an SRAM bit
Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array...
US-8,139,284 Digital micromirror device having wavelength-dependent modulation structure and method of manufacturing the same
A digital micromirror device (DMD), a method of manufacturing the DMD and an optical processor incorporating a DMD. In one embodiment, the DMD includes: (1) a...
US-8,139,078 Method and system for emulating a display
In accordance with one embodiment, a method for emulating the color performance of a display system includes determining an expected first color gamut of the...
US-8,139,077 Enhanced alpha blending
A system including storage comprising a first graphical pixel and a second graphical pixel. Each of the first and second graphical pixels is associated with...
US-8,138,833 Common-mode feedback amplifier
A circuit is provided for use with a reference voltage. The circuit includes a voltage source, a common-mode feedback amplifier and a feedback impedance...
US-8,138,829 Segmented power amplifier with varying segment activation
Various apparatuses and methods for varying segment activation in a segmented power amplifier are disclosed herein. For example, some embodiments provide a...
US-8,138,828 Active mute scheme for an amplifier
Conventional muting circuitry for amplifiers (which usually uses clamps) generally has about 20-30 dB of attenuation. Here, an integrated circuit or IC is...
US-8,138,806 Driver circuit for high voltage differential signaling
Driver circuit for high voltage differential signaling. The circuit includes a first positive driver that generates a first positive transition at a first...
US-8,138,735 Low-voltage start up circuit and method for DC-DC boost converter
A start up circuit (4-1) for a boost circuit (10) includes an adjustable-duty-cycle oscillator (1-2) that turns on a switch transistor (M.sub.SW) connected to...
US-8,138,588 Package stiffener and a packaged device using the same
A package frame for use in packaging microelectromechanical devices and/or spatial light modulators comprises a frame, a stiffener, and a heat dissipater.
US-8,138,532 Pin photodiode and manufacturing method of same
The objective of this invention is to provide a semiconductor device containing a photodiode and having stable, high sensitivity with respect to short...
US-8,138,521 Thyristor semiconductor device and switching method thereof
The objective of this invention is to provide a semiconductor device having a thyristor that can shorten the turn-off time. A first electroconductive type first...
US-8,138,074 ICs with end gates having adjacent electrically connected field poly
A method of forming an IC includes forming a first and a second gate portion using a poly mask. The first portion includes a first active poly gate having a...
US-8,138,045 Method of forming sidewall spacers to reduce formation of recesses in the substrate and increase dopant...
A method of forming sidewall spacers for a gate in a semiconductor device includes depositing a gate oxide layer over a gate and source/drain regions, and using...
US-8,138,035 Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels
A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal...
US-8,138,026 Low cost lead-free preplated leadframe having improved adhesion and solderability
A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a...
US-8,136,003 JTAG debug test system adapter with three sets of leads
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to...
US-8,136,002 Communication between controller and addressed target devices over data signal
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and...
US-8,135,563 Apparatus and method for evaluating the performance of systems having time-varying output characteristics
An apparatus for evaluating a system. The apparatus can include a storage element for receiving at least one time-varying output characteristic of the system,...
US-8,135,057 Reconfigurable chip level equalizer architecture
A reconfigurable chip level equalizer having circuitry that restores signal orthogonality and eliminates channel interference for a wireless transmitted signal....
US-8,134,996 Downlink synchronization for a cellular OFDM communication system
The present invention provides a method of operating a base station transmitter. In one embodiment, the method includes providing a cellular downlink...
US-8,134,897 Current gain control system
A current gain control system is described and comprises first and second gain blocks respectively associated with the first and second input channels, wherein...
US-8,134,850 Systems and methods for frequency control of a voltage converter
Various embodiments of the present invention provide voltage converters and methods for using such. As one example, a voltage converter is disclosed that...
US-8,134,807 Thermally enhanced disk drive
A disk drive data storage system. The system comprises a data storage disk, a movable member positioned near the data storage disk, and a sensor assembly,...
US-8,134,792 Preamplifier and method for synchronization with bit patterned media
A preamplifier and method writes data synchronized with the passing of a write head in a magnetic storage device over bit islands in discrete patterned...
US-8,134,710 Particulate detector system
A particulate detector system is provided that can sense particulates (such as smoke in the air). The system employs a reflected light system that generally...
US-8,134,411 Computation spreading utilizing dithering for spur reduction in a digital phase lock loop
A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A...
US-8,134,401 Systems and methods of low offset switched capacitor comparators
The disclosed systems and methods of low offset switched capacitor comparator reduce settling errors. The system operates in two major phases. During a first...
US-8,134,382 Semiconductor wafer having scribe line test modules including matching portions from subcircuits on active die
A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at...
US-8,134,318 System and method of current shaping control for retract
A system for implementing current shaping for retract of a voice coil motor (VCM) includes drive circuitry coupled to drive the VCM according to a logic state...
US-8,134,212 Implanted well breakdown in high voltage devices
An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed...
US-8,134,204 DEMOS transistors with STI and compensated well in drain
A drain extended MOS (DEMOS) transistor with an element of field oxide separating the drain contact from the gate, and a compensation region of opposite...
US-8,133,763 Method for semiconductor leadframes in low volume and rapid turnaround
A method for fabricating a leadframe for a QFN/SON semiconductor device by selecting (301) a strip of a first metal as the leadframe core, then plating (302) a...
US-8,133,761 Packaged system of semiconductor chips having a semiconductor interposer
A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to...
US-8,132,459 System and method to determine mechanical resonance of an accelerometer
Systems and methods are provided for determining mechanical resonance of a sensor. In one embodiment, a system is provided that comprises a bias voltage source...
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