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Patent # Description
US-8,223,465 Surge current detection in a switch by detecting change in a duty cycle
An embodiment of the invention provides a surge current protection circuit. The surge current protection circuit comprises a peak current detector and a current...
US-8,223,055 Reduced-switching dynamic element matching apparatus and methods
Apparatus and methods disclosed herein operate to reducing switching artifacts associated with dynamic element matching by sorting a set of unit elements to...
US-8,223,044 INL correction circuitry and method for SAR ADC
INL error in a SAR ADC (10) is reduced by providing correction capacitors (11B) each having a first terminal connected to a conductor (13) which is also...
US-8,222,933 Low power digital phase lock loop circuit
A digital phase lock loop circuit, where under certain conditions the phase error is derived from phase comparison between a reference clock edge and the next...
US-8,222,904 Battery end-point voltage detection method and battery end-point voltage detection system
Battery driven display device includes a battery, first and second comparators, non-volatile memory, controller driven by the voltage of the battery, and...
US-8,222,884 Reference voltage generator with bootstrapping effect
An integrated electronic device for generating a reference voltage. The circuitry has a bias current generator for generating a first bias current, a diode...
US-8,222,881 Low-power feedback and method for DC-DC converters and voltage regulators for energy harvesters
A converter (10) for converting a first DC voltage (V.sub.DD) to a second DC voltage (V.sub.OUT) includes an output stage (40) for producing the second DC...
US-8,222,748 Packaged electronic devices having die attach regions with selective thin dielectric layer
A packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon...
US-8,220,045 System and method of identifying and preventing security violations within a computing system
A system and method of identifying and preventing security violations within a computing system. Some exemplary embodiments may be a method comprising...
US-8,220,031 Secure time/date virtualization
A system is provided that includes a processor and a system memory coupled to the processor, the system memory stores at least one application for execution by...
US-8,219,953 Budgeting electromigration-related reliability among metal paths in the design of a circuit
Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter...
US-8,219,863 TAP state count specifying advanced mode command and command data
A method comprises performing at least one zero-bit scan across an interface link. The at least one zero-bit scan defines a command window. The method further...
US-8,219,862 Pass/fail scan memory with AND, OR and trinary gates
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
US-8,219,351 Methods and systems to align wafer signatures
One embodiment relates to a computer method for aligning wafers processed in a semiconductor fabrication facility. In the method, a first arrangement of dies...
US-8,219,331 Electronic device and method for evaluating a variable capacitance
An apparatus is provided. The apparatus comprises a digital signal generator, an analog filter, an amplitude modulator, and an analog-to-digital converter...
US-8,218,676 System and method for training pre-inverse of nonlinear system
A circuit for use with an amplification circuit having a predistortion datapath portion, a power amplifier portion and a gain portion. The predistortion...
US-8,218,672 Differential data transceiver and method with reversed-wire immunity
A polarity independent differential data transceiver receives a differential voltage signal and outputs a first logic state when the differential voltage signal...
US-8,218,663 Reference signal resource allocation for single user MIMO
Transmission with multiple antennas in a wireless network is performed by transmitting a plurality of reference sequences (RS) from a UE. A first RS s1[k] is...
US-8,218,526 Uplink synchronization maintenance principles in wireless networks
A cell within cellular network includes user equipments (UEs) that transmit data to a base station (eNB). UEs are synchronized to the eNB upon entry to the...
US-8,218,500 Pre-synchronization method for hard handovers in wireless networks
A pre-synchronization method in which the source cell chooses a signature for the user equipment (mobile) to use in the target cell for RACH access, and...
US-8,218,496 Random access cyclic prefix dimensioning in wireless networks
User equipment (UE)-initiated accesses within a cellular network include non-synchronized random access requests when the UE is not synchronized with a base...
US-8,218,487 System and method of adaptive frequency hopping with look ahead interference prediction
A novel and useful adaptive frequency hopping scheme for wireless devices and networks operating in a congested environment of similar devices, where capacity...
US-8,218,376 Reduced power consumption in retain-till-accessed static memories
Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each...
US-8,218,259 High-speed, low-power driver system
A reduced power driver is described. This reduced power driver comprises: an input current driver for transmitting a current signal that is a fraction of a DC...
US-8,218,257 Disk drive with multiple level power reduction during write
A disk drive data storage system comprising at least one data storage disk and a sensor assembly proximate the data storage disk. The sensor assembly further...
US-8,218,044 Solid-state imaging device
The objective of this invention is to provide a solid-state imaging device and drive method with which sampling before the output values from pixels have...
US-8,217,816 Sigma-delta modulator
A Sigma-Delta Modulator (SDM) has a summing junction that receives an input signal and a feedback signal, a multi-level analog-to-digital converter (ADC) that...
US-8,217,723 Low noise amplifier circuit
Low noise amplifier circuit. The low noise amplifier circuit includes an amplifier that amplifies an input to provide an output. The amplifier is coupled to an...
US-8,217,711 Charge pump with self-timing and method
With conventional charge pumps, significant noise is present due at least in part to large changes in the supply current. To combat this problem, a charge pump...
US-8,217,691 Low power clocking scheme for a pipelined ADC
Delay locked loops or DLLs are oftentimes employed in pipelined analog-to-digital converters (ADCs). Conventional DLLs, though, can consume an excessive amount...
US-8,217,674 Systems and methods to test integrated circuits
Open and short systems and methods for testing integrated circuits are disclosed. An example implementation includes engaging an integrated circuit testing...
US-8,217,636 Circuit and method for reducing output voltage transients in a voltage mode buck converter
A voltage control mode buck converter circuit includes a feedback amplifier providing a comparison signal and a storage circuit in communication with the...
US-8,217,615 Current sensing in a disk-drive spindle motor
One embodiment of the invention includes a disk-drive spindle motor power regulator system. The system includes a switching system comprising at least one power...
US-8,217,586 Apparatus and method for dimming a backlight with pseudo-random phase delay
A method for generating an actuation signal for a light source is provided. A random phase delay for each period of an input signal is generated, where each...
US-8,217,453 Bi-directional DMOS with common drain
A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series...
US-8,217,426 Bipolar transistors with resistors
Complementary MOS (CMOS) integrated circuits include MOS transistors, resistors and bipolar transistors formed on a common substrate. An emitter region of a...
US-8,217,322 Temperature responsive back bias control for integrated circuit
The present invention provides a thermostatic biasing controller for use with an integrated circuit. In one embodiment, the thermostatic biasing controller...
US-8,216,945 Wafer planarity control between pattern levels
A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of...
US-8,216,913 Strain modulation in active areas by controlled incorporation of nitrogen at si-SiO2 interface
Adding nitrogen to the Si--SiO2 interface at STI sidewalls increases carrier mobility in MOS transistors, but control of the amount of nitrogen has been...
US-8,216,903 SRAM cell with asymmetrical pass gate
A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a...
US-8,216,885 Methods and devices for manufacturing cantilever leads in a semiconductor package
A method of manufacturing a semiconductor package includes providing a metallic leadframe having a plurality of cantilever leads and a mounting area for...
US-8,214,705 IC with first and second external register present leads
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test...
US-8,213,865 Methods and apparatus to reduce power consumption in a wireless device
Methods and apparatus to reduce power consumption in a wireless device are disclosed. An example method includes sensing movement of the wireless device via a...
US-8,213,741 Method to generate thumbnails for digital images
This invention generates object-focused thumbnails from input images reflecting the mood and intention of the user, based on the original high-resolution...
US-8,213,695 Device and software for screening the skin
The present invention provides devices for screening the skin of an individual in real time using a region-fusion based segmentation with narrow band graph...
US-8,213,638 Equalizer
Methods and apparatus to provide an equalizer for analog adaptive control are disclosed. An example equalizer described herein includes a high frequency...
US-8,213,622 Binaural sound localization using a formant-type cascade of resonators and anti-resonators
This invention is a method for binaural localization using a cascade of resonators and anti-resonators to implement an HRTF (head-related transfer function)....
US-8,213,555 Methods and apparatus to improve distortion performance and direct current (DC) offset cancellation in receivers
Methods, apparatus, and articles of manufacture are described for improving distortion performance and for direct current offset cancellation in receivers. In...
US-8,213,515 Interpolated skip mode decision in video compression
A video encoding method determines the best video encoding mode for a macroblock in the SKIP mode and comparing this cost with other modes. This avoids...
US-8,213,511 Video encoder software architecture for VLIW cores incorporating inter prediction and intra prediction
This invention is a method of video encoding. The number N macroblocks stored in a temporary buffer depends upon an estimated number of motion vectors. N...
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