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Searching: texas instruments
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| Patent # | Description |
|---|---|
| US-8,299,612 |
IC devices having TSVS including protruding tips having IMC blocking tip
ends A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve, an inner metal core and protruding TSV tips including... |
| US-8,299,588 |
Structure and method for uniform current distribution in power supply
module A synchronous Buck converter in a molded package (thickness 101 between 0.8 and 1.0 mm) has vertically assembled control (110) and sync (120) power FET chips... |
| US-8,299,464 |
Comparator receiving expected and mask data from circuit pads Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the... |
| US-8,298,947 |
Semiconductor device having solder-free gold bump contacts for stability
in repeated temperature cycles A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external... |
| US-8,298,944 |
Warpage control for die with protruding TSV tips during thermo-compressive
bonding A method of fabricating through silicon via (TSV) die includes depositing a first dielectric layer on a substrate that includes a plurality of TSV die. The TSV... |
| US-8,298,874 |
Packaged electronic devices having die attach regions with selective thin
dielectric layer A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least... |
| US-8,298,870 |
Method for connecting integrated circuit chip to power and ground circuits In a method for transferring at least one of power and ground signal between a die and a package base of a semiconductor device, a connector is formed there... |
| US-8,298,863 |
TCE compensation for package substrates for reduced die warpage assembly A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite... |
| US-8,298,854 |
Method of manufacturing PIN photodiode The objective of this invention is to provide a type of photodiode and the method of manufacturing the photodiode characterized by the fact that it has a higher... |
| US-8,297,472 |
Pellet loader with pellet separator for molding IC devices A pellet loading apparatus includes a tablet pusher including a support surfaces including a pusher mechanism coupled thereto for vertical movement upon... |
| US-8,296,714 |
System and method for checking analog circuit with digital checker Aspects of the present invention provide a system and method for checking a portion of an analog circuit using a digital checker. The method includes... |
| US-8,296,701 |
Method for designing a semiconductor device based on leakage current
estimation A method of designing a semiconductor device includes preparing a first design for a semiconductor device and estimating leakage current for the first design.... |
| US-8,296,628 |
Data path read/write sequencing for reduced power consumption A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The... |
| US-8,296,614 |
Moving data through test control register with state machine states Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these... |
| US-8,296,607 |
Serialization module separating pipelined trace-worthy event and sync
packet data A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor... |
| US-8,295,396 |
System and method for power control in a wireless transmitter A system and method for power control in a wireless transmitter. A power control loop includes a feed forward unit coupled to a data source, the feed forward... |
| US-8,295,262 |
Uplink reference signal for time and frequency scheduling of transmissions A method for multiplexing reference signal (RS) transmissions from user equipments (UEs), with the RS having a bandwidth larger than the data signal bandwidth... |
| US-8,294,473 |
Cable detector A cable detector includes one or more peak detectors that detect when a termination impedance is missing from the output of a line driver. A peak detection... |
| US-8,294,451 |
Smart sensors for solar panels A solar panel smart sensor system is disclosed. The sensor system permits solar power system owners and operators to monitor the voltage of individual panels in... |
| US-8,294,388 |
Driving system with inductor pre-charging for LED systems with PWM dimming
control or other loads A method includes receiving a control signal associated with a load, where the control signal is to cause a load change from a perspective of a switching-mode... |
| US-8,294,261 |
Protruding TSV tips for enhanced heat dissipation for IC devices An integrated circuit (IC) device includes a substrate having a top surface including substrate pads, and a through substrate via (TSV) die including a... |
| US-8,294,243 |
Lateral bipolar transistor with compensated well regions Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar... |
| US-8,294,218 |
Method of fabricating an integrated circuit with gate self-protection, and
an integrated circuit with gate... An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor... |
| US-8,294,210 |
High voltage channel diode A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming. |
| US-8,293,573 |
Microarray package with plated contact pedestals A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically... |
| US-8,291,435 |
JEK class loader notification A method and system for performing class loader notification. At least some of the illustrative embodiments are methods comprising raising a notification during... |
| US-8,291,354 |
Merging sub-resolution assist features of a photolithographic mask Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature... |
| US-8,291,254 |
High speed digital bit stream automatic rate sense detection As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are supported,... |
| US-8,290,492 |
Handover for DVB-H A method of wireless handover in a broadcast network (FIGS. 5 and 8) is disclosed. A wireless receiver (FIG. 4) receives a first signal (N) from a first... |
| US-8,290,113 |
Frequency synthesizer prescaler scrambling Various apparatuses, methods and systems for frequency dividing a clock signal are disclosed herein. For example, some embodiments of the present invention... |
| US-8,290,098 |
Closed loop multiple transmit, multiple receive antenna wireless
communication system A wireless receiver (74) for receiving signals from a transmitter (72). The transmitter comprises a plurality of transmit antennas (TAT.sub.1', TAT.sub.2') for... |
| US-8,290,084 |
Space time transmit diversity for TDD/WCDMA systems A circuit is designed with a matched filter circuit including a plurality of fingers (700, 702, 704) coupled to receive a data symbol. Each finger corresponds... |
| US-8,290,024 |
Methods and apparatus to facilitate improved code division multiple access
receivers Methods and apparatus to facilitate improve code division multiple access (CDMA) receivers are disclosed. An example method disclosed herein comprises:... |
| US-8,289,832 |
Input signal processing system An input signal processing system is described. It comprises a first transconductance device having a first input, second input, and an output, wherein the... |
| US-8,289,651 |
Apparatus to control heat dissipation in hard-disk drives Methods and apparatus to control heat dissipation in hard-disk drives (HDDs) are disclosed. A disclosed example apparatus comprises a semiconductor die, a... |
| US-8,289,257 |
Reduced swing differential pre-drive circuit A circuit for reducing and offsetting the voltage swing of a differential pre-drive circuit. The circuit includes a first H-bridge of transistors receiving a... |
| US-8,289,205 |
Reacquiring satellite signals quickly Embodiments of the invention provide a method of reacquiring satellite signals quickly. A pseudorange of at least one satellite is estimated. A user's position... |
| US-8,289,198 |
Low power bit switches and method for high-voltage input SAR ADC A switched capacitor circuit, which may be an SAR ADC, includes a plurality of bit switching circuits (33) each including a high-voltage sampling switch circuit... |
| US-8,289,183 |
System and method for solar panel array analysis A system and method for monitoring performance of one or more solar panels in a photovoltaic array. The system and method includes a number of sensors are... |
| US-8,289,009 |
Low dropout (LDO) regulator with ultra-low quiescent current An apparatus includes at least one filter configured to filter a reference voltage to generate a filtered reference voltage. The apparatus also includes an... |
| US-8,288,953 |
Buck constant average current regulation of light emitting diodes An apparatus includes pulse width modulation (PWM) circuitry configured to generate a PWM signal based on a feedback voltage associated with current flowing... |
| US-8,288,849 |
Method for attaching wide bus memory and serial memory to a processor
within a chip scale package footprint A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory... |
| US-8,288,834 |
Semiconductor wafer and die that include an integrated circuit and two or
more different MEMS-based... Various semiconductor devices can be formed at the end of a common fabrication process, thereby significantly improving manufacturing flexibility, by... |
| US-8,288,820 |
High voltage power integrated circuit A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS... |
| US-8,288,805 |
Semiconductor device with gate-undercutting recessed region A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a... |
| US-8,288,283 |
Aluminum enhanced palladium CMP process A process of forming an integrated circuit using a palladium CMP operation in which 25 to 125 ppm aluminum is added to the CMP slurry, allowing a palladium... |
| US-8,288,243 |
Method for fabricating through substrate microchannels A method of forming large microchannels in an integrated circuit by etching an enclosed trench into the substrate and later thinning the backside to expose the... |
| US-8,286,929 |
Clam shell two-pin wafer holder for metal plating A clam shell wafer holder includes a base and a lid pivotally connected with the base by an integral hinge. The base includes a rotatable wafer support, and the... |
| US-8,286,042 |
On-chip seed generation using boolean functions for LFSR re-seeding based
logic BIST techniques for low cost... This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state... |
| US-8,284,963 |
Method and apparatus for diminishing mismatch effects between switched
signals A circuit for diminishing mismatch effects between at least two switched signals includes at least three processing circuits configured to receive at least two... |
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