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Searching: texas instruments
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| Patent # | Description |
|---|---|
| US-8,947,475 |
Spatially multiplexed pulse width modulation A process of operating a PWM display system wherein some display data bits are assigned substantially equal time weights. Display data codewords are defined for... |
| US-8,947,118 |
Defect detection in integrated circuit devices In a method of testing integrated circuit devices, a parameter, such as initial voltage may first be measured. A low pass filter operation may be applied to the... |
| US-8,947,057 |
Inverting buck-boost using single-inductor boost and charge pump with a
grounded switch The disclosed methodology for buck-boost inverted voltage conversion uses a boost stage coupled to a charge pump stage at a switch node controlled by a... |
| US-8,946,880 |
Packaged semiconductor device having multilevel leadframes configured as
modules A semiconductor system (100) has a first planar leadframe (101) with first leads (102) and pads (103) having attached electronic components (120), the first... |
| US-8,946,805 |
Reduced area single poly EEPROM A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the... |
| US-8,945,999 |
SRAM cell with different crystal orientation than associated logic An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one... |
| US-8,945,986 |
Electronic assembly with three dimensional inkjet printed traces One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate... |
| US-RE45,359 |
Integrated circuit for clock generation for memory devices A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data... |
| US-8,943,392 |
Viterbi butterfly operations A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer.... |
| US-8,943,376 |
Position independent testing of circuits Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing... |
| US-8,943,369 |
Prioritizing stall/reason data into priority information stream over
PC/data trace An electronic tracing process includes packing both stall (215) and reason (219) data into a single high priority timing information stream. An integrated... |
| US-8,943,305 |
Frame structure for medium access in body area networks (BAN) A system and method for providing a variety of medium access and power management methods are disclosed. A defined frame structure allows a hub and a node to... |
| US-8,943,248 |
Method and system for handling discarded and merged events when monitoring
a system bus A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the... |
| US-8,942,643 |
Routing for a package antenna An apparatus is provided. A plurality of transceiver antennas are arranged to form a phased array, where each antenna include a differential transmit antenna... |
| US-8,942,333 |
Apparatus and methods for clock alignment for high speed interfaces Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY... |
| US-8,942,164 |
Differential CQI for OFDMA systems Embodiments of the present disclosure provide a feedback generator, a feedback decoder and methods of operating a feedback generator and decoder. In one... |
| US-8,942,145 |
Implant access in the medical implant communications service band A system and method for providing communications between a hub (medical controller) and a node (an implant) are disclosed. The hub selects an operating channel... |
| US-8,942,080 |
Transmission of bundled ACK/NAK bits This invention is applicable to wireless communication between a user equipment (UE) and a base station using frames where at least one uplink (UL) is assigned... |
| US-8,942,049 |
Channel hot carrier tolerant tracking circuit for signal development on a
memory SRAM An embodiment of the invention discloses an electronic device for reducing degradation in NMOS circuits in a tracking circuit. A first multiplexer selects,... |
| US-8,941,517 |
Method for calbrating a pipelined continuous-time sigma delta modulator Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating... |
| US-8,941,473 |
Electronic device and method for RFID An electronic device comprising a first node to be coupled to a first antenna, a second node coupled to a second antenna, a third node to be coupled to a third... |
| US-8,941,417 |
Output driver for energy recovery from inductor based sensor A system for recovering energy from a sensor couples a battery to an inductive device in the sensor for a period of time, such that a current flows through the... |
| US-8,941,414 |
Track-and-hold circuit with low distortion A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input... |
| US-8,941,400 |
Parallel scan paths with three bond pads, distributors and collectors An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)... |
| US-8,941,366 |
DC-DC converter having an output that is a measure of the efficiency of
the converter A DC-DC converter includes efficiency reporting circuitry having an output that is a measure of efficiency. In an example, the DC-DC converter has an input... |
| US-8,941,365 |
Methods and apparatus to improve power factor at light-load Methods and apparatus to improve power factor are disclosed. An example method includes detecting power provided to a power factor corrector; detecting power... |
| US-8,941,181 |
Compensated well ESD diodes with reduced capacitance An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance,... |
| US-8,941,109 |
Test output buffer functional output input, test output, enable input Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding... |
| US-8,940,612 |
Poly resistor for metal gate integrated circuits An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in... |
| US-8,940,598 |
Low temperature coefficient resistor in CMOS flow A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of... |
| US-8,940,593 |
Enhancement-mode GaN MOSFET with low leakage current and improved
reliability An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO.sub.2/Si.sub.3N.sub.4 gate insulation layer... |
| US-8,940,093 |
Method of controlling an epitaxial growth process in an epitaxial reactor A method of controlling an epitaxial growth process in an epitaxial reactor. The method includes optimizing the thermocouple offset parameter for a second run... |
| US-8,938,739 |
Resource sharing aware task partitioning for multiprocessors A multi processor task allocation method is described that considers task dependencies while performing task allocation in order to avoid blocking of a task's... |
| US-8,938,652 |
Addressable tap domain selection circuit with AUXI/O, TDI/TDO, TMS/TRCK
leads This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial... |
| US-8,938,651 |
Blocking the effects of scan chain testing upon a change in scan chain
topology A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain... |
| US-8,938,649 |
Debug trace stream timestamping using upstream correlation A method of correlating the timing of multiple interleaved trace data streams. A Time Stamp Trace stream logic monitors the event trace stream for a... |
| US-8,935,597 |
Receivers, circuits, and methods to improve GNSS time-to-fix and other
performances An electronic circuit (2250) for a satellite receiver (100, 2200). The electronic circuit (2250) includes a correlator circuit (2310) operable to supply a data... |
| US-8,935,585 |
Tap controller having TMS, TCK, enable inputs and control outputs An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these... |
| US-8,934,890 |
Transmission of data bursts on a constant data rate channel A system and method for transmitting data bursts over a constant data rate link that transmits a continuous stream of data is disclosed. A transmitter node... |
| US-8,934,729 |
Method and apparatus for frame coding in vertical raster scan order for
HEVC A method and apparatus for frame coding in adaptive raster scan order. The method includes encoding at least one of image or video utilizing input frames and at... |
| US-8,934,522 |
Circuits, devices, and processes for improved positioning satellite
reception and other spread spectrum reception An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit (120, 210, 220) operable... |
| US-8,933,657 |
Closed loop startup control for a sensorless, brushless DC motor A method for driving a brushless direct current (DC) motor is provided. The brushless DC motor has a first phase that is coupled between a first terminal and a... |
| US-8,933,510 |
DEMOS formed with a through gate implant An integrated circuit containing a MOS transistor and a DEMOS transistor of a same polarity may be formed by implanting dopants of a same conductivity type as... |
| US-8,933,461 |
III-nitride enhancement mode transistors with tunable and high gate-source
voltage rating A semiconductor device includes an enhancement mode GaN FET with a depletion mode GaN FET electrically coupled in series between a gate node of the enhancement... |
| US-8,932,942 |
Method of forming an electrical contact between a support wafer and the
surface of a top silicon layer of a... Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises... |
| US-8,930,783 |
pBIST read only memory image compression A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are... |
| US-8,930,136 |
Static heading detection in personal navigation device A personal navigation device configured to determine heading readings continuously using data from a sensor in the personal navigation device. Heading readings... |
| US-8,929,500 |
Clock data recovery with out-of-lock detection The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. Out-of-lock detection is accomplished by sampling... |
| US-8,929,398 |
Data frame for PLC having destination address in the PHY header A method of powerline communications including a first node and at least a second node on a PLC channel in a PLC network. The first node sends a physical layer... |
| US-8,929,121 |
Reference and read OTP sensors The present disclosure provides a reference one time programmable (OTP) cell, wherein the reference OTP cell can generate a reference bias current in at least a... |
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