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| Patent # | Description |
|---|---|
| US-9,001,448 |
Pre-amplifier output stage with integrated test buffer Disk drive pre-amplifier output stage circuitry is presented including a high pass input filter for removing DC offsets from differential read data signals and... |
| US-9,000,980 |
GNSS receiver correlating doppler derotation samples with code phases A GNSS receiver includes at least one buffer and at least one correlator block. The at least one buffer stores a plurality of samples corresponding to a... |
| US-9,000,904 |
Tire pressure monitoring using half duplex transponder frequency shift A tire pressure sensor has an RFID (radio frequency identification) device having a parallel resonant circuit including an inductor and a first capacitor for... |
| US-9,000,897 |
Systems and methods for implementing application profiles and device
classes in power line communication (PLC)... Systems and methods for application profiles and device classes in power line communications (PLCs) are described. In some embodiments, a PLC device may include... |
| US-9,000,844 |
Power efficient transconductance amplifier apparatus and systems Embodiments and methods herein operate as two-stage voltage controlled current sources (i.e., dynamic current sources) operating in class AB mode. Phase-delayed... |
| US-9,000,799 |
Method to achieve true fail safe compliance and ultra low pin current
during power-up sequencing for mobile... An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage... |
| US-9,000,697 |
System and method for driving three-phase motor The present invention provides a method for driving a three-phase motor with a driver. The driver can provide a pulse-width modulated driving signal and a... |
| US-9,000,690 |
Driver for capacitive loads A method for driving a piezoelectric transducer is provided. An input signal is received. At least one of a plurality of modes is selected for a buck-boost... |
| US-9,000,539 |
Metal-gate MOS transistor and method of forming the transistor with
reduced gate-to-source and gate-to-drain... The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k... |
| US-9,000,505 |
Quantum electro-optical device using CMOS transistor with reverse polarity
drain implant A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region.... |
| US-8,996,848 |
Less-secure processors, integrated circuits, wireless communications
apparatus, methods and processes of making An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile... |
| US-8,995,580 |
Pseudorandom sequence generation for OFDM cellular systems In one embodiment, a transmitter includes a binary sequence generator unit configured to provide a sequence of reference signal bits, wherein the sequence is an... |
| US-8,995,535 |
Signaling signed band offset values for sample adaptive offset (SAO)
filtering in video coding A method for signaling sample adaptive offset (SAO) band offset syntax elements in a video encoder is provided that includes receiving a plurality of band... |
| US-8,995,532 |
Low complexity large transform Methods of encoding a video stream in a video encoder and decoding an encoded video stream in a video decoder using a low complexity large transform are... |
| US-8,995,461 |
Channel selection in power line communications Systems and methods for channel selection in power line communications (PLC) are described. In some embodiments, a method may include defining a plurality of... |
| US-8,995,437 |
Transmission of segmented frames in power line communication Segmented frames of data may be transmitted from a transmitting device using conflict free slots (CFS) within a carrier sense multiple access with collision... |
| US-8,995,430 |
IC processor reconstucting two consecutive lost packets from secondary
information A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice... |
| US-8,995,380 |
Scheduling in a multi-hop wireless network Various techniques are disclosed for assigning timeslots in a multihop wireless network. One such method includes, for each node for uplink timeslot... |
| US-8,995,164 |
High-performance scalable read-only-memory cell A two-bit read-only-memory (ROM) cell and method of sensing its data state. Each ROM cell in an array includes a single n-channel metal-oxide-semiconductor... |
| US-8,994,585 |
Fine grained duty cycling and timing control for pulsed radar A method is provided. A first edge on a first gating signal is generated, and a local oscillator and a shared clocking circuit with the first edge on the first... |
| US-8,994,435 |
Switching core layout Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local... |
| US-8,994,397 |
Thermal pad shorts test for wire bonded strip testing A method of testing a packaged semiconductor device under test (DUT) including a leadframe having a plurality of pins and at least one thermal pad with a... |
| US-8,994,154 |
Proximity sensor having light blocking structure in leadframe A semiconductor proximity sensor (100) has a flat leadframe (110) with a first (110a) and a second (110b) surface, the second surface being solderable; the... |
| US-8,993,412 |
Method for reducing backside die damage during die separation process In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing... |
| US-8,990,650 |
TCA with scan paths, decompressor, compressor, and output shift register The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access... |
| US-8,990,649 |
Access port selector for access port and compliant access port The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The... |
| US-8,989,447 |
Dynamic focus for computational imaging A method for all-in-focus image reconstruction and depth map generation in an imaging device is provided that includes capturing a multi-focus image by the... |
| US-8,988,667 |
Halogen gas sensor comprising cobalt A method of halogen gas monitoring includes contacting room air to be monitored with a halogen sensor including a cobalt or cobalt alloy layer. The halogen... |
| US-8,988,531 |
Method and apparatus for sub-picture based raster scanning coding order A method and apparatus for sub-picture based raster scanning coding order. The method includes dividing an image into even sub-pictures, and encoding parallel... |
| US-8,988,266 |
Asynchronous sampling using dynamically configurable voltage polling
levels A method, comprising: receiving an analog input; determining an upper outer rail and a lower outer rail as polling values to be used by voltage comparators;... |
| US-8,988,131 |
Transistor switch including independent control of turn-on and slew rate The disclosed transistor switching methodology enables independent control of transistor turn-on delay and slew rate, including charging, during a pre-charge... |
| US-8,987,748 |
Drain induced barrier lowering with anti-punch-through implant An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer... |
| US-8,984,359 |
Base, IC, and coupling interposer with boundary scan register The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement... |
| US-8,984,358 |
IC TAP with address, state monitor, and state decode circuitry The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a... |
| US-8,984,357 |
Wrapper selector data register having control outputs and SELECTAM input A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard... |
| US-8,984,356 |
Circuitry selectively coupling scan circuitry to test data out lead An integrated circuit has controller circuitry having inputs coupled to a test clock lead and to a test mode select lead, and having state outputs indicating... |
| US-8,984,319 |
Adapter power up circuitry forcing tap states and decoupling tap A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and... |
| US-8,984,246 |
Method, system and computer program product for reading a decision tree In response to a query of a decision tree, a first packed node of the decision tree is copied from a system memory into a direct memory access ("DMA") memory.... |
| US-8,983,218 |
Virtual boundary processing simplification for adaptive loop filtering
(ALF) in video coding Virtual boundary processing in adaptive loop filtering (ALF) requires that padded values be substituted for unavailable pixel rows outside the virtual... |
| US-8,983,080 |
Method and system for temperature protection of a speaker For protecting a speaker, an input signal is received and filtered into component signals. A sum of the component signals is approximately equal to the input... |
| US-8,983,012 |
Receive timing manager A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition... |
| US-8,982,517 |
Electrostatic discharge protection apparatus An electrostatic discharge (ESD)-triggered protection apparatus includes a first circuit and a second circuit. The first circuit includes an ESD trigger circuit... |
| US-8,981,984 |
Asynchronous to synchronous sampling using an augmented least squares
solver A method, comprising: receiving a plurality of 2-tuples of asynchronously sampled inputs at an asynchronous to synchronous reconstructor; performing a coarse... |
| US-8,981,837 |
System and method for reduction of bottom plate parasitic capacitance in
charge pumps A system for providing a load current at a specific output voltage to a circuit block of an integrated circuit (IC) includes a supply node at a supply voltage,... |
| US-8,981,821 |
Interference mitigation output frequency determined by division factors
selected randomly Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering... |
| US-8,981,702 |
Automated motor control Input-output linearization (IOL) and extended state observer (ESO) techniques are applied to a Field Oriented Control (FOC) for Permanent Magnet Synchronous... |
| US-8,981,490 |
Transistor with deep Nwell implanted through the gate A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate... |
| US-8,981,445 |
Analog floating-gate memory with N-channel and P-channel MOS transistors An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The... |
| US-8,980,723 |
Multiple depth vias in an integrated circuit An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with... |
| US-8,978,146 |
Wireless communications system communicating secyre SIM and IMEI between
processors An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By... |
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