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| Patent # | Description |
|---|---|
| US-9,124,532 |
Multiple rank CQI feedback for cellular networks Single user and multiuser MIMO transmission in a cellular network may be performed by a base station (eNB) transmitting either one, two, or more transmission... |
| US-9,124,463 |
Communication device with sleep state indicator and state machine control A device with an autonomous sleep characteristic, which is in communication with a host, is described. The device includes one or more communication subsystems.... |
| US-9,124,462 |
Flexible PRBS architecture for a transceiver An apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, a first bus, a second bus, and a transceiver that is coupled... |
| US-9,124,359 |
Mitigation of interference between wireless networks A system and method for minimizing or preventing interference between wireless networks is disclosed. A network hub broadcasts a beacon signal within repeating... |
| US-9,124,324 |
Dual loop digital predistortion for power amplifiers A method of predistorting an input signal (902) for an amplifier is disclosed (FIG. 9). The method includes predistorting the input signal with a first set of... |
| US-9,124,263 |
Body bias coordinator, method of coordinating a body bias and sub-circuit
power supply employing the same A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit... |
| US-9,124,177 |
Systems and methods of smooth light load operation in a DC/DC converter Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction... |
| US-9,123,802 |
Vertical trench MOSFET device in integrated power technologies A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift... |
| US-9,123,737 |
Chip to dielectric waveguide interface for sub-millimeter wave
communications link In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue.... |
| US-9,123,626 |
Integrated passive flip chip package A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the... |
| US-9,123,570 |
Integration scheme for changing crystal orientation in hybrid orientation
technology (HOT) using direct silicon... Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such... |
| US-9,123,562 |
Layout method to minimize context effects and die area An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region... |
| US-9,123,404 |
Self clocking for data extraction A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is... |
| US-9,123,300 |
Electrophoretic display with software recognizing first and second
operating formats Electrophoretic displays (EPDs) and methods for controlling EPDs are disclosed herein. An embodiment of an EPD includes a first operating format, wherein pixels... |
| US-9,122,609 |
Caching method and system for video coding A method of caching reference data in a reference data cache is provided that includes receiving an address of a reference data block in the reference data... |
| US-9,122,354 |
Detecting wave gestures near an illuminated surface A method for wave gesture detection performed by a touch processor in an optical touch detection system is provided. The method includes receiving a sequence of... |
| US-9,121,906 |
Semiconductor test system and method A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response... |
| US-9,121,905 |
TAP with commandable data register control router and routing circuit The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to... |
| US-9,121,904 |
Tap linking module test access port controller with enable input An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these... |
| US-9,121,903 |
Parallel scan path distributor/collector controller having serial and
control inputs Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these... |
| US-9,121,767 |
System clock counter counting ring oscillator pulses during programmed
value A method of programming a ring oscillator for use as a temperature sensor comprises selecting an initial number of delay elements for use in a ring oscillator.... |
| US-9,121,714 |
Attitude estimation for pedestrian navigation using low cost MEMS
accelerometer in mobile applications, and... A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor... |
| US-9,121,106 |
Method of forming a laminated magnetic core with sputter deposited and
electroplated layers A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between... |
| US-9,119,321 |
Assembly method for converting the precursors to capacitors A method of assembling a packaged semiconductor device includes dropping a pre-formed capacitor precursor and an integrated circuit on a surface of a substrate.... |
| US-9,118,342 |
Low power excess loop delay compensation technique for delta-sigma
modulators A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog... |
| US-9,118,315 |
Scheme to improve the performance and reliability in high voltage IO
circuits designed using low voltage devices A high voltage input/output (IO) circuit designed using low voltage devices. The IO circuit receives a first bias voltage and a second bias voltage. The IO... |
| US-9,118,259 |
Phase-shifted dual-bridge DC/DC converter with wide-range ZVS and zero
circulating current Disclosed is a family of new DC/DC converters and a new control method. The converter comprises two bridge inverters, two full-wave rectification circuits and a... |
| US-9,118,239 |
Power supply control method for constant current constant power control A digital power supply and power supply controller are presented, including a voltage control loop and a current control loop, with a controller for pulse width... |
| US-9,117,775 |
Alignment to multiple layers A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a... |
| US-9,117,691 |
Low cost transistors An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the... |
| US-9,117,687 |
High voltage CMOS with triple gate oxide An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a... |
| US-9,117,535 |
Single sided bit line restore for power reduction A memory circuit to reduce active power is disclosed (FIG. 7). The circuit includes a sense amplifier (600). A first bit line (BL) is coupled to a memory array.... |
| US-9,117,106 |
Use of three-dimensional top-down views for business analytics A method of analyzing a depth image in a digital system is provided that includes detecting a foreground object in a depth image, wherein the depth image is a... |
| US-9,116,830 |
Method to extend data retention for flash based storage in a real time
device processed on generic... This invention is a method to extend data retention for FLASH based storage in a real time device embodied in generic semiconductor technology. This invention... |
| US-9,116,769 |
ASIP with reconfigurable circuitry implementing atomic operations of a PLL A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit... |
| US-9,116,590 |
5-wire resistive touch screen pressure measurement circuit and method A 5-wire touch screen system includes a touch screen (10) including a wiper (11) and a resistive layer (16) aligned with the wiper and first (UL), second (UR),... |
| US-9,116,209 |
Gating WSP update and TAP updatedr with TAP IR enable In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture,... |
| US-9,116,208 |
Address and command port with tap and master controller circuitry An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI... |
| US-9,116,207 |
IC gating selection on first/second and deselection on second/third counts Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path.... |
| US-9,114,995 |
Separating Metallic and Semiconductor SWNTS with sinusoidal
dipole-inducing magnetic fields A process of sorting metallic single wall carbon nanotubes (SWNTs) from semiconducting types by disposing the SWNTs in a dilute fluid, exposing the SWNTs to a... |
| US-9,113,470 |
Systems and methods for network coding using maximum distance separable
(MDS) linear network codes A method for network coding includes generating a message matrix, where each column of the message matrix corresponds to one of K message packets and each... |
| US-9,113,460 |
Mapping between logical and physical uplink control resource blocks in
wireless networks A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations on an uplink channel in a wireless network. A... |
| US-9,113,398 |
Multirole device muxing channel scan with channel scan time slices Systems and methods for channel scanning for multirole device are disclosed. One implementation relates to a method for servicing functions by a multirole... |
| US-9,113,340 |
Synchronized channel access in coexisting wireless networks A system and method for arbitrating channel access in a wireless device including co-located network transceivers are disclosed herein. A wireless device... |
| US-9,113,325 |
Signaling of random access preamble time-frequency location in wireless
networks Embodiments of the present disclosure provide a base station sub-system, a method of allocating random access configurations and a method of downlink signaling... |
| US-9,112,916 |
Systems and methods for construction of and network coding using
near-maximum distance separable (MDS) linear... A method for network coding using a near-maximum distance separable linear network code includes generating a message matrix where each column of the message... |
| US-9,112,753 |
Interleaver design and header structure for ITU G.hnem Embodiments of the invention provide an interleaver design and header fields for ITU-T G.hnem. The header may comprise two parts that are separately encoded. A... |
| US-9,112,527 |
Digital-to-analog sinusoidal driver apparatus, systems and methods Input codes are sequenced at a lower-resolution linear DAC and the output is converted to a linear current waveform. A first of two interconnected analog... |
| US-9,112,413 |
Switched mode assisted linear regulator with AC coupling with capacitive
charge control The disclosed switched mode assisted linear (SMAL) amplifier/regulator architecture may be configured as a SMAL regulator to supply power to a dynamic load,... |
| US-9,112,409 |
Switched mode assisted linear regulator with dynamic buck turn-off using
ZCD-controlled tub switching A switched mode assisted linear regulator includes a linear amplifier (LA) and a buck converter configured as a current source. In example embodiments, the buck... |
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