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Patent # Description
US-8,129,962 Low dropout voltage regulator with clamping
Apparatus and methods for reducing output load transients of a low dropout voltage regulator ("LDO") are disclosed herein. A voltage regulator includes an...
US-8,129,814 Schottky diode with silicide anode and anode-encircling P-type doped region
An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a...
US-8,129,682 On-chip calibration system and method for infrared sensor
A radiation sensor includes an integrated circuit radiation sensor chip (1A) including first (7) and second (8) thermopile junctions connected in series to form...
US-8,129,248 Method of producing bipolar transistor structures in a semiconductor process
In the method of producing bipolar transistor structures in a semiconductor process, an advanced epitaxial trisilane process can be used without the risk of...
US-8,129,246 Advanced CMOS using super steep retrograde wells
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer...
US-8,129,228 Manufacturing method for integrating a shunt resistor into a semiconductor package
An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to...
US-8,129,227 Semiconductor device having grooved leads to confine solder wicking
A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes...
US-8,129,224 Stud bumps as local heat sinks during transient power operations
A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding...
US-8,129,089 Use of blended solvents in defectivity prevention
The present invention provides a blended solvent for solubilizing an ultraviolet photoresist. The blended solvent comprises a mixture of from about 5 vol % to...
US-8,127,263 Improving routability of integrated circuit design without impacting the design area
Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined...
US-8,127,211 Adding known data to CRC processing without increased processing time
Cyclic redundancy check processing is applied advantageously to a set of input data that includes an unknown data portion and a data portion that is already...
US-8,127,189 Gates and sync circuitry connecting TAP to serial communications circuitry
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus....
US-8,126,707 Method and system for speech compression
Methods, encoders, and digital systems are provided for predictive encoding of speech parameters in which an input frame is encoded by quantizing a parameter...
US-8,126,681 Semiconductor outlier identification using serially-combined data transform processing methodologies
A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain...
US-8,126,401 Transmitter PLL with bandwidth on demand
An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator...
US-8,126,164 Digital compensation of analog volume control gain in a digital audio amplifier
A digital audio system including a combination of analog and digital volume control is disclosed. A variable power supply voltage biases a power amplifier for...
US-8,126,158 Reducing sound pressure of noise
A system comprising converter logic that introduces noise to a signal. The system also comprises amplifier logic that reduces a sound pressure associated with...
US-8,126,092 Multistage PN code acquisition circuit and method
A circuit for detecting a serial signal comprises a first circuit coupled to receive the serial signal during a predetermined plurality of time periods of...
US-8,125,885 Frequency offset estimation in orthogonal frequency division multiple access wireless networks
A method of wireless transmission for estimating the carrier frequency offset in a base station of a received transmission from a user equipment (UE) accessing...
US-8,125,830 Area-efficient electrically erasable programmable memory cell
Electrically erasable programmable "read-only" memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell...
US-8,125,810 Low power ternary content-addressable memory (TCAM)
An integrated circuit (200) includes a semiconductor memory device (202) operative for determining match between received search data and stored data in a...
US-8,125,800 Secondary-side amplifier with soft start
An isolated switching regulator has a closed-loop soft-start feature that allows tighter regulation of the output voltage and eliminates or reduces overshoot....
US-8,125,579 Polarized light emitting diode and use thereof
Provided is a light emitting diode (LED). The LED, in one embodiment, includes a reflective layer located over a substrate and a quarter wave plate emitter...
US-8,125,558 Integrated image capture and projection system
An integrated system comprises a light valve and an image sensor for image display and image capture. The image sensor and the light valve share a common...
US-8,125,553 Solid-state imaging device
An imaging apparatus is provided. The apparatus generally comprises an array and storage elements. The array includes photosensitive cells that are arranged in...
US-8,125,273 Apparatus and method for driving an LED
Here, a driver for an light emitting diode (LED) is provided. Within this driver, several differential pairs of bipolar transistors are employed in an input...
US-8,125,253 System and method for dynamically switching between low and high frequency reference clock to PLL and...
A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter...
US-8,125,238 Automatic test equipment
A coupling line is provided for coupling a signal generator to a device under test and includes a first Zener diode and a second Zener diode. The first Zener...
US-8,125,189 Systems for charging a battery in a closed loop configuration
A system is provided for charging a battery with an AC adapter. The system includes a first closed loop electrical path between the battery and the AC adapter....
US-8,125,054 Semiconductor device having enhanced scribe and method for fabrication
In a semiconductor device for use in a wafer level chip scale package (WLCSP) and a method for fabrication, an inner scribe seal is formed around a functional...
US-8,125,053 Embedded scribe lane crack arrest structure for improved IC package reliability of plastic flip chip devices
A system, method, and apparatus for suppressing cracks in the wafer dicing process. A wafer includes a plurality of die attached to a frame and mounting tape,...
US-8,125,035 CMOS fabrication process
Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible...
US-8,125,030 High voltage SCRMOS in BiCMOS process technologies
An integrated circuit containing an SCRMOS transistor. The SCRMOS transistor has one drain structure with a centralized drain diffused region and distributed...
US-8,124,529 Semiconductor device fabricated using a metal microstructure control process
The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the...
US-8,124,511 Method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder
One aspect provides a method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder. In one aspect, this improvement is...
US-8,124,486 Method to enhance channel stress in CMOS processes
The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier...
US-8,124,482 MOS transistor with gate trench adjacent to drain extension field insulation
An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source...
US-8,124,321 Etching method for use in deep-ultraviolet lithography
In a lithography process using an ultraviolet process, the applied ultraviolet resist can be removed by intentionally condensing the ultraviolet resist before...
US-8,122,311 Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules...
In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module...
US-8,122,310 Input buffer, test switches and switch control with serial I/O
The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
US-8,122,244 Secure management of configuration parameters in a computing platform
A computing platform (10) protects system firmware (30) using a manufacturer certificate (36). The manufacturer certificate binds the system firmware (30) to...
US-8,121,835 Automatic level control of speech signals
Automatic level control of speech portions of an audio signal is provided. An audio signal is received in the form of a sequence of samples and may contain...
US-8,121,576 Linearity of an RF receive path by spurious tone suppression
A method of increasing linearity of an RF signal receive path includes measuring a signal amplified by the receive path. The receive path has a local oscillator...
US-8,121,561 Power tuning system and method for power amplifier
An automatic power tuning system and method, and a transmitter employing either the system or the method. In one embodiment, the system includes: (1) a power...
US-8,121,558 Local oscillator generator architecture using a wide tuning range oscillator
A local oscillator (LO) generator architecture using a wide tuning range oscillator is disclosed. In one embodiment, a wide tuning oscillator based LO generator...
US-8,121,482 Spatial light modulator-based reconfigurable optical add-drop multiplexer and method of adding an optical...
A reconfigurable optical add-drop multiplexer (ROADM) and a method of passing at least one optical channel through the multiplexer. In one embodiment, the...
US-8,121,299 Method and system for music detection
Methods, digital systems, and computer readable media are provided for detection of music in an audio signal. Music is detected by partitioning the audio signal...
US-8,121,214 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using XOR operation
A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF...
US-8,121,194 Fast macroblock encoding with the early qualification of skip prediction mode using its temporal coherence
The latest video-coding standards achieve higher coding efficiency than the previous video standards, while increasing the complexity and the difficulty of...
US-8,120,884 Reverse voltage protection circuit
A voltage protection circuit that has a protection transistor coupled between a voltage supply pin of an integrated circuit and a voltage output terminal of the...
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