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Patent # Description
US-8,213,367 Methods for dimensioning the control channel for transmission efficiency in communication systems
Embodiments of the invention provide methods for optimizing the spectral efficiency of control channel transmissions carrying scheduling assignments from a...
US-8,212,720 Detecting lack of movement to aid GNSS receivers
Embodiments of the invention provide a method of detecting movement to aid GNSS receivers. By detecting when the user is stationary, the Doppler frequency...
US-8,212,705 Pipeline ADC
Pipeline analog-to-digital converters (ADCs) are used in many applications, but because of the configuration, components may be idled, which wastes power. Here,...
US-8,212,644 Transformer assembly
The present invention relates to a transformer assembly (1) and a process for manufacturing same. The transformer (1) comprises a primary winding (5) wound on a...
US-8,212,611 Switching core layout
Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local...
US-8,212,606 Apparatus and method for offset drift trimming
An apparatus is provided that includes a drift trimming stage that includes a first current source providing a current with a first temperature dependency and a...
US-8,212,400 Multi-rail power-supply system
A multi-rail power-supply system provides power to circuitry requiring at least one additional rail between a high and a low-voltage rail. The system comprises...
US-8,211,794 Properties of metallic copper diffusion barriers through silicon surface treatments
In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of...
US-8,211,773 SRAM cell with asymmetrical pass gate
A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a...
US-8,209,650 Method and system for entry and verification of parasitic design constraints for analog integrated circuits
A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with...
US-8,209,575 MIMO hybrid-ARQ using basis hopping
A Hybrid Automatic Retransmission Request (H-ARQ) technique is provided for Multi-Input Multi-Output (MIMO) systems. The technique changes the basis (V) upon...
US-8,208,759 Light valve projection of visible image correlated with non-visible image
An image system comprises a light valve and an image capturing unit. The light valve comprises an array of individually addressable pixels capable of generating...
US-8,208,558 Transform domain fast mode search for spatial prediction in advanced video coding
This invention is method for determining direction mode for an image block in intra prediction of video frames. The method calculates a plurality of energy...
US-8,207,831 Transponder demodulator for a low antenna limiter threshold
An RFID transponder having an antenna for receiving an RF signal including an amplitude modulated downlink data signal, and a demodulating stage coupled to the...
US-8,207,764 Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high...
An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop,...
US-8,207,559 Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures
In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material,...
US-8,205,145 High-speed add-compare-select (ACS) circuit
A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional...
US-8,205,125 Enhanced control in scan tests of integrated circuits with partitioned scan chains
A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an...
US-8,205,057 Method and system for integrated pipeline write hazard handling using memory attributes
In a system and method for write hazard handling a memory management unit policy is pre-computed for a write request using an address that is at least one clock...
US-8,204,753 Stabilization and glitch minimization for CCITT recommendation G.726 speech CODEC during packet loss scenarios...
This invention decoded encoded speech using alternative parameters upon detection of a lost packet. Upon detection of a first good packet following packet loss,...
US-8,204,470 Predecoding for joint processing coordinated multi-point transmission
This invention is a method of predecoding for joint processing coordinated multi-point transmission. The invention identifies for a particular transmission the...
US-8,203,867 8T SRAM cell with one word line
An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and...
US-8,203,786 Method and system for screen attachment
Methods and apparatus for a display system include a frame and one or more screen panels. Each panel has an inwardly disposed face and an outwardly disposed...
US-8,203,776 Planarity of pixel mirrors
A method of forming an electronic device includes providing a patterned lower metal layer over a substrate and a first sacrificial layer there between. A second...
US-8,203,384 Amplifier
An amplifier has first and second differential outputs connected to first and second ends of one side of a balun. A second side of the balun, inductively...
US-8,203,383 Reducing the effect of bulk leakage currents
A current mirroring circuit is provided. The circuit generally comprises a current source; a first drain extended (DE) MOS transistor, a second DE MOS...
US-8,203,323 Switched mode power supply with current sensing
An electronic device for switched mode DC-DC conversion is provided that includes a stage for sensing an output current causing a voltage difference between a...
US-8,203,197 Thermally enhanced semiconductor devices
Thermal communication of matched transistors formed in lower electrical resistance subregions of first and second active substrate regions is provided by...
US-8,202,773 Engineered oxygen profile in metal gate electrode and nitrided high-k gate dielectrics structure for high...
A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS...
US-8,202,433 Reducing adherence in a MEMS device
In one embodiment, an apparatus for reducing adherence in a micro-electromechanical system (MEMS) device comprises a substrate. A MEMS is disposed outwardly...
US-8,201,036 IC with test and shadow access ports and output circuit
The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform...
US-8,201,004 Entry/exit control to/from a low power state in a complex multi level memory system
An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller...
US-8,200,954 Multi-stage boot pin sampling
In accordance with embodiments, a method for configuring an electronic device during a power-on sequence includes sampling a boot pin state multiple times. The...
US-8,200,479 Method and system for asymmetric independent audio rendering
Methods and mobile devices are provided for asymmetric independent processing of audio streams in a system on a chip (SOC). More specifically, independent audio...
US-8,200,461 Small-signal stability analysis at transient time points of integrated circuit simulation
Simulation method and system for analyzing the stability of a modeled electronic circuit. Simulation of the transient response to a desired input stimulus is...
US-8,199,706 Random access design for high doppler in wireless networks
UE-initiated accesses within a cellular network are optimized to account for Doppler shift. A user equipment (UE) receives information that designates a...
US-8,199,666 Transmission of acknowledge/not-acknowledge with repetition
In ACK/NAK responses with repetition, the ACK/NAK response from the user equipment to a Physical Downlink Shared CHannel (PDSCH) transmission is repeated in...
US-8,199,577 Ripple programming of memory cells in a nonvolatile memory
An electrically erasable programmable read-only memory (EEPROM) with a ripple programming mode. Memory cells in an the EEPROM array include floating-gate...
US-8,199,037 ADC channel selection and conversion
A microcontroller includes a microcontroller core and an analog-to-digital converter ("ADC") coupled to said microcontroller core. The ADC has multiple input...
US-8,198,932 Voltage generating circuit for an attenuator
A circuit includes a digital-to-analog converter (DAC), coupled to a power supply, that provides a first current at a first output terminal of the DAC and a...
US-8,198,918 Capacitor cell supporting circuit operation at higher-voltages while employing capacitors designed for lower...
An integrated circuit (IC) includes a functional circuit and a capacitor cell. The functional circuit may operate with one of two power supply voltages. The...
US-8,198,912 Driver circuit correction arm decoupling resistance in steady state mode
A voltage-mode driver circuit supporting pre-emphasis is implemented to include a driver arm and a correction arm. The driver arm receives an input signal, and...
US-8,198,873 Power converter
This invention relates to a power converter (1) comprising a converter input (3), a converter output, a power factor pre-regulation stage (5), an isolation...
US-8,198,184 Method to maximize nitrogen concentration at the top surface of gate dielectrics
An integrated circuit having a gate dielectric layer (414, 614, 814) having an improved nitrogen profile and a method of fabrication. The gate dielectric layer...
US-8,198,105 Monitor for variation of critical dimensions (CDs) of reticles
The present invention provides a reticle 100 for use in a lithographic process. The reticle, in one embodiment, includes a patterned layer 110 located over a...
US-8,196,076 Optimal flow in designing a circuit operable in multiple timing modes
A design approach provided according to an aspect of the present invention consolidates the constraint files of respective modes into consolidated information...
US-8,195,994 Inverter and TMS clocked flip-flop pairs between TCK and reset
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-8,195,972 Jitter precorrection filter in time-average-frequency clocked systems
Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals....
US-8,195,932 Authentication and encryption for secure data transmission
A system and method for authenticating and encrypting messages for secure transmission is disclosed. A frame to be transmitted between devices comprises a frame...
US-8,195,109 Single ended switched power amplifier with tuned load coupling block
A switched power amplifier contained in a circuit is implemented to receive a single-ended input signal and generate a single-ended output signal, the...
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