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Patent # Description
US-8,094,765 Clock and mode signals controlling data communication in three states
Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and...
US-8,094,638 Adaptive selection of transmission parameters for reference signals
An embodiment of the present invention uses estimates of delay spreads of transmissions from user equipments (UEs) to a NodeB to determine a set of transmission...
US-8,094,352 Mirror assembly with recessed mirror
A mirror device and a method for manufacturing the mirror device are presented. The mirror device includes a mirror formed from a first substrate and a...
US-8,094,234 System and method for multistage frame rate conversion
System and method for multistage frame rate conversion. A method comprises receiving an incoming frame at a first frame rate, and determining whether a fault...
US-8,094,050 Bandwidth mismatch estimation in time-interleaved analog-to-digital converters
With high speed, high resolution time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches between the various ADC branches can pose a...
US-8,093,941 Systems and devices for dynamically scaled charge pumping
Systems and devices for dynamically scaled charge pumping are presented. Example embodiments of the disclosed systems of dynamically scaled charge pumping...
US-8,093,925 Current driver circuit
An integrated regulated current drive circuit for driving a squib of an inflatable airbag has a current sense resistor connected in series with a load, and a...
US-8,093,878 Switching power supply device
A switching power supply device for a ripple control system that can obtain the ripple component with the necessary amplitude without using discrete elements....
US-8,093,716 Contact fuse which does not touch a metal layer
The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer...
US-8,093,688 Device comprising an ohmic via contact, and method of fabricating thereof
Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a...
US-8,093,622 Semiconductor device and its driving method
A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth...
US-8,093,115 Tuning of SOI substrate doping
A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an...
US-8,093,070 Method for leakage reduction in fabrication of high-density FRAM arrays
A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor...
US-8,088,664 Method of manufacturing integrated deep and shallow trench isolation structures
A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers...
US-8,085,958 Virtualizer sweet spot expansion
Audio loudspeaker virtualizers and cross-talk cancellers and methods use a combination of interaural intensity difference and interaural time difference to...
US-8,085,951 Method and system for determining a gain reduction parameter level for loudspeaker equalization
Methods, digital systems, and computer readable media are provided for determining a gain reduction parameter level for loudspeaker equalization by determining...
US-8,085,940 Rebalancing of audio
Rebalancing of an audio signal refers to achieving a balance of perceived loudness, typically of right and left channels, given an unbalanced input. A flexible...
US-8,085,580 System for bitcell and column testing in SRAM
A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The...
US-8,085,074 Fast-locking delay locked loop
A fast locking delay-locked loop (DLL), which can also operate as a clock data recovery circuit (CDR), includes a delay chain, a sampling circuit and a...
US-8,085,008 System for accounting for switch impendances
A Universal Serial Bus (USB) switch matrix is provided. The switch matrix generally comprises a switch network, and amplifier, a adjustable current source, and...
US-8,084,787 PMD liner nitride films and fabrication methods for improved NMOS performance
Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress...
US-8,084,312 Nitrogen based implants for defect reduction in strained silicon
A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain...
US-8,083,961 Method and system for controlling the uniformity of a ballistic electron beam by RF modulation
A method and system for treating a substrate using a ballistic electron beam is described, whereby the radial uniformity of the electron beam flux is adjusted...
US-8,081,481 Apparatus and method for a clip device for coupling a heat sink plate system with a burn-in board system
A clip for coupling a first board and second board, the first board having plurality of first post coupled thereto, the second board having a plurality of...
US-8,078,927 Wrapper leads gating TAP instruction and data registers
In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture,...
US-8,078,898 Synchronizing TAP controllers with sequence on TMS lead
A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and...
US-8,078,897 Power management in federated/distributed shared memory architecture
This invention is a power management scheme for a shared memory multiprocessor system which splits the control logic between the master-specific logic and...
US-8,078,842 Removing local RAM size limitations when executing software code
An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory...
US-8,073,684 Apparatus and method for automatic classification/identification of similar compressed audio files
An audio file is divided into frames in the time domain and each frame is compressed, according to a psycho-acoustic algorithm, into file in the frequency...
US-8,073,074 System and method for power control in a wireless transmitter
A power control loop includes a feed forward unit 301 coupled to a data source, the feed forward unit 301 processes a signal for transmission, a feedback unit...
US-8,072,918 Network-based inter-cell power control for multi-channel wireless networks
A method is described for operating a cellular network, where the cellular network uses a plurality of frequency division multiplexing (FDM) bands for wireless...
US-8,072,770 Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame
Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material...
US-8,072,262 Low input bias current chopping switch circuit and method
A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input...
US-8,071,430 Stress buffer layer for ferroelectric random access memory
An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between...
US-8,069,290 Processing system operable in various execution environments
A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait...
US-8,069,201 8.times.8 transform and quantization
Low complexity (16 bit arithmetic) video compression has 8.times.8 block with transforms using 8.times.8 integer matrices and quantization with look up table...
US-8,068,871 Systems and methods for time optimization for silencing wireless devices in coexistence networks
Embodiments provide systems and methods to optimize the time when to transmit a silencing frame, and hence, improve the overall network throughput and avoid...
US-8,068,466 Transmission of multiple information elements in multiple channels
A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations. The transmission from the secondary to...
US-8,068,379 Dynamic RAM
A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line...
US-8,068,267 Speckle reduction in display systems that employ coherent light sources
Speckle effect in display system is reduced by utilizing the instability of phase-coherent light and the transmission of the instable phase-coherent light...
US-8,068,043 Method and apparatus for video processing in context-adaptive binary arithmetic coding
A method and apparatus of a digital signal processor for coding of a significant map. The method for coding of a significant map includes carrying out a scan of...
US-8,067,955 Preventing erroneous operation in a system where synchronized operation is required
This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its...
US-8,067,795 Single poly EEPROM without separate control gate nor erase regions
A single-poly EEPROM memory device comprises source and drain regions in a semiconductor body, a floating gate overlying a portion of the source and drain...
US-8,067,792 Memory device with memory cell including MuGFET and FIN capacitor
One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region...
US-8,067,279 Application of different isolation schemes for logic and embedded memory
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and...
US-8,065,578 Inverted TCK access port selector selecting one of plural TAPs
The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The...
US-8,065,577 Dual controllers for scan paths, distributors, and collectors
Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these...
US-8,065,506 Application specific instruction set processor for digital radio processor receiving chain signal processing
This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable...
US-8,065,505 Stall-free pipelined cache for statically scheduled and dispatched execution
This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute...
US-8,065,140 Method and system for determining predominant fundamental frequency
Methods, digital systems, and computer readable media are provided for determining a predominant fundamental frequency of a frame of an audio signal by finding...
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