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Patent # Description
US-8,195,103 Linearization of a transmit amplifier
A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to...
US-8,195,034 Low complexity event detection for video programs
A video processing method for detecting significant events from a video program includes computing short-time sub-band energies in the audio for plural audio...
US-8,195,002 Adaptive post-deringing filter on compressed images
An image filtering method, apparatus and system, wherein the method comprising the steps of detecting at least one portion of an edge, wherein the portion of...
US-8,194,892 Output coupling capacitor free audio power amplifier dynamically configured for speakers and headphones with...
First and second channel bridge amplifiers are dynamically configured to drive either speakers or headphones. The first channel bridge amplifier includes a...
US-8,194,188 Displaying image frames in combination with a subpicture frame
An aspect of the present invention reduces memory accesses while forming combined images of a subpicture frame with each of a sequence of image frames. In an...
US-8,194,141 Method and apparatus for producing sharp frames with less blur
A method and apparatus motion triggered image stabilization. The method includes computing projection vector for at least a portion of a frame of an image using...
US-8,193,980 Doppler and code phase searches in a GNSS receiver
According to an aspect of the present invention, each correlation block in a Global Navigation Satellite System (GNSS) receiver is designed to examine a certain...
US-8,193,958 Signal regenerator
Pulses that are generated from multiple analog input signals are sampled, and signal elements contained in the analog signals are extracted accurately using the...
US-8,193,841 Electronic device for power-on-reset
An electronic device is provided that includes a power-on-reset (POR) circuit. The POR circuit includes a trigger stage configured to change an output if a...
US-8,193,832 Arbiter array using two-dimensional address decoding
A system comprises a plurality of requesting agents and granting agents configured in an array of rows and a plurality of columns. Corresponding to each...
US-8,193,798 Buck regulators with adjustable clock frequency to achieve dropout voltage reduction
A method includes generating a drive signal for a transistor in a switching regulator. The drive signal turns the transistor on and off to generate a regulated...
US-8,193,644 Pop precursor with interposer for top package bond pad pitch compensation
An electronic assembly adapted for forming package on package (PoP) devices includes a package substrate having a molded IC die thereon that defines a mold cap...
US-8,193,603 Semiconductor structure and method of forming the semiconductor structure that provides two individual...
A semiconductor structure is formed in the metal interconnect structure of an integrated circuit in a method that provides either two individual resistors that...
US-8,193,602 Schottky diode with control gate for optimization of the on state resistance, the reverse leakage, and the...
A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated...
US-8,193,093 Thru silicon enabled die stacking scheme
A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully...
US-8,193,085 Method for fabricating flip-attached and underfilled semiconductor devices
A semiconductor device (1700), which comprises a workpiece (1201) with an outline (1711) and a plurality of contact pads (1205) and further an external part...
US-8,191,027 Validation of an integrated circuit for electro static discharge compliance
An aspect of the present invention validates ESD compliance by examining netlist data generated from a schematic level design of an integrated circuit. Routing...
US-8,190,954 Core circuit test architecture
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections....
US-8,190,931 Power management events profiling
In a method for monitoring power consumption by a system within an integrated circuit, one or more software programs are executed on the system on a chip (SOC)....
US-8,190,861 Micro-sequence based security model
A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are...
US-8,190,794 Control function for memory based buffers
Instantiating a plurality of buffers in a random access memory by storing in the random access memory (RAM) a plurality of descriptors each containing a base...
US-8,189,881 Fingerprint sensor using beams of light and methods of manufacture and use
A fingerprint sensor uses beams of light to detect a fingerprint as the finger is swiped over a ridged surface. The beams of light are directed toward...
US-8,189,817 System for amplifiers with low distortion and low output impedance
System for pulse-width-modulated class D audio amplifiers. In one preferred embodiment an adder is described to generate a difference signal responsive to an...
US-8,189,744 Dynamic hearing/voice carry over for global text telephony
A system and method for controlling a telecommunications device capable of text telephone, and voice carry over or hearing carry over operation where transition...
US-8,189,725 Loop bandwidth enhancement technique for a digital PLL and A HF divider that enables this technique
A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first...
US-8,189,557 Secondary synchronization channel design for OFDMA systems
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the...
US-8,189,456 Apparatus for and method of minimizing backoff for orthogonal frequency division multiplexing transmission
A novel and useful mechanism for reducing the required backoff and the peak to average power ratio (PAPR) needed for an OFDM transmitter whiles still meeting...
US-8,189,454 Multi-band OFDM communications system
A method for providing communication in a wireless network comprising one or more simultaneously operating pico networks includes dividing UWB spectrum into a...
US-8,189,309 Clamp for controlling current discharge
In many applications, particularly in automotive applications, integrated circuits (IC) are designed to withstand large fly-back currents from inductive loads....
US-8,189,284 Quiet retraction system
A quiet retraction method for regulating constant velocity while parking an arm within a disk drive is described. The method comprises the steps of: driving a...
US-8,189,079 Imaging apparatus and method
In recent years, the performance of CMOS and CCD image sensors has dramatically improved, and to utilize the improved performance of these sensors, processing...
US-8,188,902 Ternary search SAR ADC
Traditionally, successive approximation register (SAR) analog-to-digital converters (ADCs) using binary search algorithms have consumed power by performing...
US-8,188,790 Gated class H amplifier/line driver system and method
Amplifier circuitry (10) includes a driver amplifier (11) and an integrator amplifier (A.sub.H) producing an output signal (V.sub.AH) that controls a pass...
US-8,188,676 Systems and methods for driving light-emitting diodes
At least some embodiments include a LED driver system. The system includes multiple branches of series-coupled LEDs, multiple current sources, and control...
US-8,187,920 Integrated circuit micro-module
One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are...
US-8,185,952 Static and dynamic firewalls
A system comprising control logic adapted to activate multiple security levels for the system. The system further comprises a storage coupled to the control...
US-8,185,790 Resynchronization memory in series/parallel with control/output data scan cells
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a...
US-8,185,789 Capturing response after simultaneously inputting last stimulus bit in scan path subdivisions
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and...
US-8,185,774 Timer for low-power and high-resolution with low bits derived from set of phase shifted clock signals
The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing most significant bits...
US-8,185,672 Transmission of data bursts on a constant data rate channel
A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no...
US-8,185,666 Compare instruction
A processor executes an instruction that causes a comparison to be performed between contents of a first register and contents of a second register and between...
US-8,184,579 ACK/NAK repetition schemes in wireless networks
ACK/NAK repetition may be necessary to provide sufficient coverage for cell edge UEs. For a coverage limited UE, a NodeB may inform the UE that ACK/NAK...
US-8,184,474 Asymmetric SRAM cell with split transistors on the strong side
An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate...
US-8,184,154 Video surveillance correlating detected moving objects and RF signals
A surveillance method periodically detects an image of the area, identifies and tracks each moving object in a succession of the detected images, detects radio...
US-8,183,939 Ring oscillator
A ring oscillator has at least one latch connected to the outputs of at least one oscillator stage, where the latch drives the outputs of the oscillator stage...
US-8,183,621 Non-volatile memory cell having a heating element and a substrate-based control gate
The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that...
US-8,183,137 Use of dopants to provide low defect gate full silicidation
The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment,...
US-8,183,117 Device layout in integrated circuits to reduce stress from embedded silicon-germanium
An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring...
US-8,181,067 Apparatus and method for test and debug of a processor/core having advanced power management
An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit...
US-8,180,635 Weighted sequential variance adaptation with prior knowledge for noise robust speech recognition
A method for adapting acoustic models used for automatic speech recognition is provided. The method includes estimating noise in a portion of a speech signal,...
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