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Patent # Description
US-8,115,464 Boost circuit and power supply device
The objective of this invention is to provide a boost circuit that reduces power consumption and prevents malfunctioning when the input voltage becomes greater...
US-8,115,463 Compensation of LDO regulator using parallel signal path with fractional frequency response
A low drop out (LDO) voltage regulator (10) includes a pass transistor (MP.sub.pass) having a source coupled by an output conductor (4) to a load and a drain...
US-8,115,461 Power supply circuit and battery device
A power supply circuit with low noise and low power consumption and a battery device using the power supply circuit. If a voltage VDD is higher than a...
US-8,115,453 Method and apparatus for managing energy in plural energy storage units
A system for managing energy stored in a plurality of series connected energy storage units has a plurality of energy storage unit controllers, each controller...
US-8,115,345 Variable timing switching system and method
A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable...
US-8,115,337 Soft-start circuit
An apparatus is provided. The apparatus comprises an input circuit, a startup circuit, and a current limiter. The input circuit is coupled to a first source and...
US-8,115,310 Copper pillar bonding for fine pitch flip chip devices
A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and...
US-8,115,272 Silicon dioxide cantilever support and method for silicon etched structures
An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant...
US-8,114,784 Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement
Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS...
US-8,114,779 Silicon dioxide cantilever support and method for silicon etched structures
An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant...
US-8,114,744 Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom
A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon...
US-8,114,731 Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor
The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The...
US-8,114,729 Differential poly doping and circuits therefrom
A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface,...
US-8,114,728 Integration scheme for an NMOS metal gate
A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of...
US-8,114,727 Disposable spacer integration with stress memorization technique and silicon-germanium
An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT)...
US-8,114,706 Selective removal of gold from a lead frame
A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top...
US-8,113,662 System and method for reducing the effect of an image artifact
In accordance with the teachings of the present disclosure, a system and method for displaying an image are provided. In one embodiment, the method includes...
US-RE43,191 Adaptive Weiner filtering using line spectral frequencies
An acoustic noise suppression filter including attenuation filtering with a noise-free estimate based on a codebook of line spectral frequencies.
US-8,112,737 Contact resistance and capacitance for semiconductor devices
A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the...
US-8,112,685 Serial compressed data I/O in a parallel test compression architecture
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access...
US-8,112,684 Input linking circuitry connected to test mode select and enables
IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for...
US-8,112,668 Dynamic broadcast of configuration loads supporting multiple transfer formats
A method for dynamically broadcasting configuration information to controllers connected in a scan topology in a target system is provided in which a selection...
US-8,112,652 Multiprocessor system power management of shared memories powering down memory bank only when all processors...
This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each...
US-8,112,618 Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making
An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile...
US-8,112,400 Method for collecting data from semiconductor equipment
A method for collecting data from semiconductor equipment includes selecting a plurality of data values to request from semiconductor equipment and assigning...
US-8,112,168 Process and method for a decoupled multi-parameter run-to-run controller
A manufacturing process including a controller method to generate a tool setting which includes a tool offset and a device offset. The controller method uses a...
US-8,112,051 Method and system for false frequency lock free autonomous scan in a receiver
Method and system for false lock free autonomous scan in a receiver is disclosed. The method includes identifying a presence of a desired signal to avoid false...
US-8,112,050 Reducing power consumption in receivers employing conversion to intermediate frequency
A receiver to recover a signal of interest while consuming reduced power in some scenarios. The receiver contains a in-phase channel processing path and a...
US-8,111,760 Deblocking filters
Deblock filtering for Microsoft WMV video decoders partitions the computation so that the deblock filtering operations can be performed on horizontal or...
US-8,111,731 Block scrambling for orthogonal frequency division multiple access
A method of transmitting signals in a communication system over at least two time periods including generating a base signal comprising of at least two samples...
US-8,111,330 Method and apparatus for analog graphics sample clock frequency offset detection and verification
A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for...
US-8,111,324 Apparatus and method for film source reconstruction
A method for film reconstruction includes identifying motion tear artifacts within a plurality of video fields of a stream of video fields. The motion tear...
US-8,111,181 Single-ended polar transmitting circuit with current salvaging and substantially constant bandwidth
An embodiment of the invention provides a single-ended polar transmitting circuit. The single-ended polar transmitting circuit comprises a DAC, a ...
US-8,111,098 Segmented linear FM power amplifier
Various apparatuses and methods for amplifying an FM signal in a segmented linear power amplifier are disclosed herein. For example, some embodiments provide an...
US-8,111,092 Register with process, supply voltage and temperature variation independent propagation delay path
A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant...
US-8,111,047 Sensor node voltage clamping circuit and method
A voltage clamping circuit includes a current source having a fixed current source and a variable current source and a variable resistor receiving current from...
US-8,110,997 LED drive circuit
A LED drive circuit equipped with oscillator 18, up/down counter 20, and DAC 22 in order to drive multiple LEDs 10(1)-10(m) in a block. Up/down counter 20...
US-8,110,857 Low noise JFET
A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface...
US-8,110,855 Offset geometries for area reduction in memory arrays
An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not...
US-8,110,462 Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection
The present invention relates to electrostatic discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more...
US-8,110,454 Methods of forming drain extended transistors
A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also...
US-8,110,438 Thermal method to control underfill flow in semiconductor devices
A method and apparatus for assembling a semiconductor device. A chip (901) with solder bodies (903) on its contact pads is flipped onto a substrate (904). After...
US-8,110,416 AC impedance spectroscopy testing of electrical parametric structures
Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication...
US-8,110,414 Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes
A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region...
US-8,109,485 Tilting television wall mount
A display wall mount comprising a wall bracket configured to couple to a wall and having a first wall bracket edge, a display bracket configured to couple to...
US-8,108,742 Tap control of TCA scan clock and scan enable
The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with...
US-8,108,641 Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices
A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first...
US-8,107,570 Space time block coded transmit antenna diversity for WCDMA
A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (r.sub.j(i+.tau..sub.j), i=0-N-1) during a first...
US-8,107,547 Receivers for embedded ACK/NAK in CQI reference signals in wireless networks
Within a wireless network, uplink control information (UCI) transmitted by user equipment is received by a base station. The UCI includes a least two elements,...
US-8,107,420 Wireless communications system with cycling of unique cell bit sequences in station communications
A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a...
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