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Patent # Description
US-8,065,506 Application specific instruction set processor for digital radio processor receiving chain signal processing
This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable...
US-8,065,505 Stall-free pipelined cache for statically scheduled and dispatched execution
This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute...
US-8,065,140 Method and system for determining predominant fundamental frequency
Methods, digital systems, and computer readable media are provided for determining a predominant fundamental frequency of a frame of an audio signal by finding...
US-8,064,717 Digital camera and method
Deblurring of digital camera images by estimating the blur function from an image extracted from a video sequence taken about the time of an image capture. The...
US-8,064,611 Uplink noise cancellation
A system comprising audio logic adapted to convert captured sound into an audio signal. The system also comprises transmission logic which causes noise to be...
US-8,064,546 Random access preamble detection for long term evolution wireless networks
This invention is a method for preamble detection with estimation of UE timing advance (TA) and channel quality information (CQI) which uses a sliding window to...
US-8,064,279 Structure and method for screening SRAMS
An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also...
US-8,064,275 Local sensing and feedback for an SRAM array
An integrated circuit having an SRAM array includes SRAM cells arranged in rows and columns, and a global read circuit connected to globally read SRAM cells...
US-8,064,271 Static random access memory device having bit line voltage control for retain till accessed mode and method of...
A static random-access memory (SRAM) and a method of controlling bit line voltage. In one embodiment, the SRAM includes: (1) an array of SRAM cells organized in...
US-8,063,949 Activity-based system and method for reducing gain imbalance in a bayer pattern and digital camera employing...
An activity-based system for, and method of, reducing Gr-Gb gain imbalance and a digital camera incorporating the system or the method. In one embodiment, the...
US-8,063,948 Proximity-based system and method for reducing gain imbalance in a bayer pattern and digital camera employing...
A proximity-based system for, and method of, reducing Gr-Gb gain imbalance and a digital camera incorporating the system or the method. In one embodiment, the...
US-8,063,911 System and method for gamut mapping of out-of-gamut signals
A system and method for gamut mapping out-of-gamut signals. A method includes adjusting each color in a color signal, determining a maximum color value of the...
US-8,063,688 AC clamp circuit for video applications
This invention is a clamp circuit for a video input. The clamp circuit includes: a coupling capacitor; a differential amplifier comparing a video input to...
US-8,062,966 Method for integration of replacement gate in CMOS flow
Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides...
US-8,060,929 Method and system for providing security to processors
There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to...
US-8,060,027 RF transmission leakage mitigator, method of mitigating an RF transmission leakage and CDMA transceiver...
The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission...
US-8,060,019 Asymmetric ESD protection for FM transmitter
Various apparatuses and methods for protecting a transmitter from electrostatic discharge are disclosed herein. For example, some embodiments provide an...
US-8,059,917 3-D modeling
A system comprising an imaging device adapted to capture images of a target object at multiple angles. The system also comprises storage coupled to the imaging...
US-8,059,764 Systems and methods for low-complexity max-log MIMO detection
Embodiments provide novel systems and methods for multiple-input multiple-output (MIMO) Max-Log detection. These systems and methods enable near-optimal...
US-8,059,746 Producing STTD diversity signal from rake combined level 3 message
A circuit is designed with a measurement circuit (746) coupled to receive an input signal from at least one of a first antenna and a second antenna of a...
US-8,059,745 Sharing logic circuitry for a maximum likelihood MIMO decoder and a viterbi decoder
A receiver system for receiving and decoding modulated communications signals in a multiple-input, multiple-output (MIMO) environment, where the signals are...
US-8,059,735 Allocation of block spreading sequences
A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations. The transmission from the secondary to...
US-8,059,670 Hardware queue management with distributed linking information
A network element including a processor with logic for managing packet queues by way of packet descriptor index values that are mapped to addresses in the...
US-8,059,524 Allocation and logical to physical mapping of scheduling request indicator channel in wireless networks
A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is...
US-8,059,340 Method and system for reducing speckle by vibrating a line generating element
Provided is a method and system for reducing speckle in an image produced from a light source. The method, in one embodiment, includes providing a line...
US-8,059,323 Stabilizer for MEMS devices having deformable elements
A stabilizer mechanism is coupled to a deformable element of a microelectromechanical device for reducing unwanted deformation of the deformable element by...
US-8,058,902 Circuit for aligning input signals
A circuit for aligning input signals includes a clock generating circuit (CGC) responsive to first signal and second signal to generate a clock signal. A first...
US-8,058,860 Single pin multi-VID bit interface circuit for dynamic voltage change of a DC/DC converter
A controller for a DC/DC converter is provided. The controller comprises an error circuit, control logic, a high side driver, a low side driver, and an...
US-8,058,706 Delamination resistant packaged die having support and shaped die having protruding lip on support
A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A...
US-8,058,677 Stress buffer layer for ferroelectric random access memory
An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between...
US-8,058,161 Recessed STI for wide transistors
A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a...
US-8,058,122 Formation of metal gate electrode using rare earth alloy incorporated into mid gap metal
Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy...
US-RE42,919 Power control with space time transmit diversity
A circuit is designed with a measurement circuit (432). The measurement circuit is coupled to receive a first input signal (903) from a first antenna (128) of a...
US-8,056,029 Merging sub-resolution assist features of a photolithographic mask
Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature...
US-8,055,967 TAP interface outputs connected to TAP interface inputs
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP...
US-8,055,962 Testing IC functional and test circuitry having separate input/output pads
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test....
US-8,055,947 Comparing supplied and sampled link ID bits on TMS lead
An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a...
US-8,055,886 Processor micro-architecture for compute, save or restore multiple registers and responsive to first...
An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction...
US-8,055,828 Electronic power management system
An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage...
US-8,055,231 RF feedback engine coupled to receiver low noise amplifier
Methods and apparatus to perform radio frequency (RF) analog-to-digital conversion are described. According to one example, a receiver includes an amplifier to...
US-8,055,217 Adaptive complex gain predistorter for a transmitter
Symbols are transmitted in a Cartesian transmitter by pre-distorting an input signal X having in-phase and quadrature components using a first compensation...
US-8,054,914 Noise variance estimation
A method and system for estimating noise variance. A method for noise variance estimation comprises receiving a first multi-sample symbol and receiving a second...
US-8,054,912 Large-dynamic-range lookup table for a transmitter predistorter and system and method employing the same
A predistorters for use with a nonlinear element and methods of predistorting for a nonlinear element for use in a 3G, e.g., WCDMA transmitter. In one...
US-8,054,861 Primary, secondary, and tertiary codes synchronizing slots in a frame
A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a...
US-8,054,823 Mapping schemes for secondary synchronization signal scrambling
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the...
US-8,054,810 Interleaver for transmit diversity
The present invention exploits the benefits obtainable from using transmit diversity by designing the size of the interleaver matrix to avoid the case where...
US-8,054,742 System and method for sidelobe suppression in communications systems
A system and method for sidelobe suppression in OFDM communications systems is provided. A method for transmitting an information symbol having a plurality of...
US-8,054,652 Systems and methods for off-time control in a voltage converter
Various embodiments of the present invention provide voltage converters and methods for using such. As one example, a voltage converter is disclosed that...
US-8,054,552 Lens array element and method
According to one embodiment of the present invention a method for directing light onto a digital micromirror device is disclosed that includes the steps of...
US-8,054,529 System and method for displaying images
System and method for simultaneous display of multiple images using a single light modulator array. A preferred embodiment comprises a light source that...
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