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Patent # Description
US-8,131,230 Method and system for FM transmitter coexistence
A system and method for operating an FM system and wireless networking system coexistent in a mobile wireless device. A mobile wireless device includes a...
US-8,130,889 Receive timing manager
A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition...
US-8,130,791 Receiver and method for processing a stream of data packets when an error occurred on the physical layer
A receiver which receives a stream of data packets including video data packets over a physical data link and drops data packets when an error on a physical...
US-8,130,667 Preamble group selection in random access of wireless networks
A transport block size (TBS) of a first uplink message (RACH Msg3) transmitted on a Physical Uplink Shared Channel (PUSCH) during a random access procedure in a...
US-8,130,653 Deletion request after number of failed acknowledgements to addition requests
Network circuitry and a method of operating the same in establishing and deleting a service flow in a wireless network. A network station receives a request,...
US-8,130,481 Electrostatic discharge trigger circuits for self-protecting cascode stages
Electrostatic discharge (ESD) protection circuits for self-protecting cascode stages are disclosed. In one example, an ESD protection circuit is described. A...
US-8,130,129 Analog-to-digital conversion
One embodiment of the present invention includes an analog-to-digital converter (ADC) system. The system includes an ADC configured to generate digital samples...
US-8,130,067 High frequency semiconductor transformer
A semiconductor transformer provides high frequency operation by forming the primary windings of the transformer around a section of magnetic material that has...
US-8,130,047 Open loop coarse tuning for a PLL
In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a...
US-8,130,040 Power amplifier with two transistors and traces forming two transformers
Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high...
US-8,130,032 Systems and methods for high-sensitivity detection of input bias current
The invention relates to systems and methods for high-sensitivity detection of input bias current. The invention more particularly relates to platforms and...
US-8,129,962 Low dropout voltage regulator with clamping
Apparatus and methods for reducing output load transients of a low dropout voltage regulator ("LDO") are disclosed herein. A voltage regulator includes an...
US-8,129,814 Schottky diode with silicide anode and anode-encircling P-type doped region
An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a...
US-8,129,682 On-chip calibration system and method for infrared sensor
A radiation sensor includes an integrated circuit radiation sensor chip (1A) including first (7) and second (8) thermopile junctions connected in series to form...
US-8,129,248 Method of producing bipolar transistor structures in a semiconductor process
In the method of producing bipolar transistor structures in a semiconductor process, an advanced epitaxial trisilane process can be used without the risk of...
US-8,129,246 Advanced CMOS using super steep retrograde wells
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer...
US-8,129,228 Manufacturing method for integrating a shunt resistor into a semiconductor package
An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to...
US-8,129,227 Semiconductor device having grooved leads to confine solder wicking
A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes...
US-8,129,224 Stud bumps as local heat sinks during transient power operations
A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding...
US-8,129,089 Use of blended solvents in defectivity prevention
The present invention provides a blended solvent for solubilizing an ultraviolet photoresist. The blended solvent comprises a mixture of from about 5 vol % to...
US-8,127,263 Improving routability of integrated circuit design without impacting the design area
Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined...
US-8,127,211 Adding known data to CRC processing without increased processing time
Cyclic redundancy check processing is applied advantageously to a set of input data that includes an unknown data portion and a data portion that is already...
US-8,127,189 Gates and sync circuitry connecting TAP to serial communications circuitry
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus....
US-8,126,707 Method and system for speech compression
Methods, encoders, and digital systems are provided for predictive encoding of speech parameters in which an input frame is encoded by quantizing a parameter...
US-8,126,681 Semiconductor outlier identification using serially-combined data transform processing methodologies
A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain...
US-8,126,401 Transmitter PLL with bandwidth on demand
An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator...
US-8,126,164 Digital compensation of analog volume control gain in a digital audio amplifier
A digital audio system including a combination of analog and digital volume control is disclosed. A variable power supply voltage biases a power amplifier for...
US-8,126,158 Reducing sound pressure of noise
A system comprising converter logic that introduces noise to a signal. The system also comprises amplifier logic that reduces a sound pressure associated with...
US-8,126,092 Multistage PN code acquisition circuit and method
A circuit for detecting a serial signal comprises a first circuit coupled to receive the serial signal during a predetermined plurality of time periods of...
US-8,125,885 Frequency offset estimation in orthogonal frequency division multiple access wireless networks
A method of wireless transmission for estimating the carrier frequency offset in a base station of a received transmission from a user equipment (UE) accessing...
US-8,125,830 Area-efficient electrically erasable programmable memory cell
Electrically erasable programmable "read-only" memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell...
US-8,125,810 Low power ternary content-addressable memory (TCAM)
An integrated circuit (200) includes a semiconductor memory device (202) operative for determining match between received search data and stored data in a...
US-8,125,800 Secondary-side amplifier with soft start
An isolated switching regulator has a closed-loop soft-start feature that allows tighter regulation of the output voltage and eliminates or reduces overshoot....
US-8,125,579 Polarized light emitting diode and use thereof
Provided is a light emitting diode (LED). The LED, in one embodiment, includes a reflective layer located over a substrate and a quarter wave plate emitter...
US-8,125,558 Integrated image capture and projection system
An integrated system comprises a light valve and an image sensor for image display and image capture. The image sensor and the light valve share a common...
US-8,125,553 Solid-state imaging device
An imaging apparatus is provided. The apparatus generally comprises an array and storage elements. The array includes photosensitive cells that are arranged in...
US-8,125,273 Apparatus and method for driving an LED
Here, a driver for an light emitting diode (LED) is provided. Within this driver, several differential pairs of bipolar transistors are employed in an input...
US-8,125,253 System and method for dynamically switching between low and high frequency reference clock to PLL and...
A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter...
US-8,125,238 Automatic test equipment
A coupling line is provided for coupling a signal generator to a device under test and includes a first Zener diode and a second Zener diode. The first Zener...
US-8,125,189 Systems for charging a battery in a closed loop configuration
A system is provided for charging a battery with an AC adapter. The system includes a first closed loop electrical path between the battery and the AC adapter....
US-8,125,054 Semiconductor device having enhanced scribe and method for fabrication
In a semiconductor device for use in a wafer level chip scale package (WLCSP) and a method for fabrication, an inner scribe seal is formed around a functional...
US-8,125,053 Embedded scribe lane crack arrest structure for improved IC package reliability of plastic flip chip devices
A system, method, and apparatus for suppressing cracks in the wafer dicing process. A wafer includes a plurality of die attached to a frame and mounting tape,...
US-8,125,035 CMOS fabrication process
Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible...
US-8,125,030 High voltage SCRMOS in BiCMOS process technologies
An integrated circuit containing an SCRMOS transistor. The SCRMOS transistor has one drain structure with a centralized drain diffused region and distributed...
US-8,124,529 Semiconductor device fabricated using a metal microstructure control process
The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the...
US-8,124,511 Method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder
One aspect provides a method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder. In one aspect, this improvement is...
US-8,124,486 Method to enhance channel stress in CMOS processes
The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier...
US-8,124,482 MOS transistor with gate trench adjacent to drain extension field insulation
An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source...
US-8,124,321 Etching method for use in deep-ultraviolet lithography
In a lithography process using an ultraviolet process, the applied ultraviolet resist can be removed by intentionally condensing the ultraviolet resist before...
US-8,122,311 Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules...
In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module...
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