Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: texas instruments





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-8,059,670 Hardware queue management with distributed linking information
A network element including a processor with logic for managing packet queues by way of packet descriptor index values that are mapped to addresses in the...
US-8,059,524 Allocation and logical to physical mapping of scheduling request indicator channel in wireless networks
A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is...
US-8,059,340 Method and system for reducing speckle by vibrating a line generating element
Provided is a method and system for reducing speckle in an image produced from a light source. The method, in one embodiment, includes providing a line...
US-8,059,323 Stabilizer for MEMS devices having deformable elements
A stabilizer mechanism is coupled to a deformable element of a microelectromechanical device for reducing unwanted deformation of the deformable element by...
US-8,058,902 Circuit for aligning input signals
A circuit for aligning input signals includes a clock generating circuit (CGC) responsive to first signal and second signal to generate a clock signal. A first...
US-8,058,860 Single pin multi-VID bit interface circuit for dynamic voltage change of a DC/DC converter
A controller for a DC/DC converter is provided. The controller comprises an error circuit, control logic, a high side driver, a low side driver, and an...
US-8,058,706 Delamination resistant packaged die having support and shaped die having protruding lip on support
A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A...
US-8,058,677 Stress buffer layer for ferroelectric random access memory
An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between...
US-8,058,161 Recessed STI for wide transistors
A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a...
US-8,058,122 Formation of metal gate electrode using rare earth alloy incorporated into mid gap metal
Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy...
US-RE42,919 Power control with space time transmit diversity
A circuit is designed with a measurement circuit (432). The measurement circuit is coupled to receive a first input signal (903) from a first antenna (128) of a...
US-8,056,029 Merging sub-resolution assist features of a photolithographic mask
Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature...
US-8,055,967 TAP interface outputs connected to TAP interface inputs
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP...
US-8,055,962 Testing IC functional and test circuitry having separate input/output pads
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test....
US-8,055,947 Comparing supplied and sampled link ID bits on TMS lead
An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a...
US-8,055,886 Processor micro-architecture for compute, save or restore multiple registers and responsive to first...
An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction...
US-8,055,828 Electronic power management system
An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage...
US-8,055,231 RF feedback engine coupled to receiver low noise amplifier
Methods and apparatus to perform radio frequency (RF) analog-to-digital conversion are described. According to one example, a receiver includes an amplifier to...
US-8,055,217 Adaptive complex gain predistorter for a transmitter
Symbols are transmitted in a Cartesian transmitter by pre-distorting an input signal X having in-phase and quadrature components using a first compensation...
US-8,054,914 Noise variance estimation
A method and system for estimating noise variance. A method for noise variance estimation comprises receiving a first multi-sample symbol and receiving a second...
US-8,054,912 Large-dynamic-range lookup table for a transmitter predistorter and system and method employing the same
A predistorters for use with a nonlinear element and methods of predistorting for a nonlinear element for use in a 3G, e.g., WCDMA transmitter. In one...
US-8,054,861 Primary, secondary, and tertiary codes synchronizing slots in a frame
A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a...
US-8,054,823 Mapping schemes for secondary synchronization signal scrambling
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the...
US-8,054,810 Interleaver for transmit diversity
The present invention exploits the benefits obtainable from using transmit diversity by designing the size of the interleaver matrix to avoid the case where...
US-8,054,742 System and method for sidelobe suppression in communications systems
A system and method for sidelobe suppression in OFDM communications systems is provided. A method for transmitting an information symbol having a plurality of...
US-8,054,652 Systems and methods for off-time control in a voltage converter
Various embodiments of the present invention provide voltage converters and methods for using such. As one example, a voltage converter is disclosed that...
US-8,054,552 Lens array element and method
According to one embodiment of the present invention a method for directing light onto a digital micromirror device is disclosed that includes the steps of...
US-8,054,529 System and method for displaying images
System and method for simultaneous display of multiple images using a single light modulator array. A preferred embodiment comprises a light source that...
US-8,054,358 Solid state image pickup device
This invention improves linearity of a solid-state image pickup device beyond that of the prior art source follower to improve image quality. The image pickup...
US-8,054,103 Synchronous clock multiplexing and output-enable
A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals...
US-8,054,057 Low dropout regulator testing system and device
A device for testing low dropout (LDO) regulator is disclosed. In one embodiment, a device for testing LDO regulators includes an absolute value measurement...
US-8,054,056 Frequency regulated hysteretic average current mode converter
A switch mode power converter that precisely controls average switching current and operating frequency. The switching control operative in hysteretic average...
US-8,053,876 Multi lead frame power package
According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead...
US-8,053,873 IC having voltage regulated integrated Faraday shield
An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit...
US-8,053,349 BGA package with traces for plating pads under the chip
A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching...
US-8,053,324 Method of manufacturing a semiconductor device having improved transistor performance
In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by...
US-8,053,322 Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated...
A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate...
US-8,053,296 Capacitor formed on a recrystallized polysilicon layer
The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The...
US-8,053,285 Thermally enhanced single inline package (SIP)
In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A...
US-8,053,256 Variable thickness single mask etch process
The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an...
US-8,053,252 Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean
A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A...
US-8,052,286 System and method for utilizing a scanning beam to display an image
A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first...
US-8,051,399 IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing...
An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which an output of a cell...
US-8,051,398 Test method and system for characterizing and/or refining an IC design cycle
Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical...
US-8,051,391 Method for layout of random via arrays in the presence of strong pitch restrictions
Exemplary embodiments provide a method for laying out an integrated circuit ("IC") design and the IC design layout. In one embodiment, the IC design layout can...
US-8,051,351 DDR circuit with addressable TAP linking circuitry and plural TAPS
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface...
US-8,051,349 Link instruction register with instruction register, and gate and multiplexer
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing...
US-8,051,347 Scan-enabled method and system for testing a system-on-chip
Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of...
US-8,051,313 Apparatus, system and method of power state control
An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for...
US-8,051,285 Battery processor circuitry with separate public and private bus
Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.