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Patent # Description
US-8,135,057 Reconfigurable chip level equalizer architecture
A reconfigurable chip level equalizer having circuitry that restores signal orthogonality and eliminates channel interference for a wireless transmitted signal....
US-8,134,996 Downlink synchronization for a cellular OFDM communication system
The present invention provides a method of operating a base station transmitter. In one embodiment, the method includes providing a cellular downlink...
US-8,134,897 Current gain control system
A current gain control system is described and comprises first and second gain blocks respectively associated with the first and second input channels, wherein...
US-8,134,850 Systems and methods for frequency control of a voltage converter
Various embodiments of the present invention provide voltage converters and methods for using such. As one example, a voltage converter is disclosed that...
US-8,134,807 Thermally enhanced disk drive
A disk drive data storage system. The system comprises a data storage disk, a movable member positioned near the data storage disk, and a sensor assembly,...
US-8,134,792 Preamplifier and method for synchronization with bit patterned media
A preamplifier and method writes data synchronized with the passing of a write head in a magnetic storage device over bit islands in discrete patterned...
US-8,134,710 Particulate detector system
A particulate detector system is provided that can sense particulates (such as smoke in the air). The system employs a reflected light system that generally...
US-8,134,411 Computation spreading utilizing dithering for spur reduction in a digital phase lock loop
A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A...
US-8,134,401 Systems and methods of low offset switched capacitor comparators
The disclosed systems and methods of low offset switched capacitor comparator reduce settling errors. The system operates in two major phases. During a first...
US-8,134,382 Semiconductor wafer having scribe line test modules including matching portions from subcircuits on active die
A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at...
US-8,134,318 System and method of current shaping control for retract
A system for implementing current shaping for retract of a voice coil motor (VCM) includes drive circuitry coupled to drive the VCM according to a logic state...
US-8,134,212 Implanted well breakdown in high voltage devices
An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed...
US-8,134,204 DEMOS transistors with STI and compensated well in drain
A drain extended MOS (DEMOS) transistor with an element of field oxide separating the drain contact from the gate, and a compensation region of opposite...
US-8,133,763 Method for semiconductor leadframes in low volume and rapid turnaround
A method for fabricating a leadframe for a QFN/SON semiconductor device by selecting (301) a strip of a first metal as the leadframe core, then plating (302) a...
US-8,133,761 Packaged system of semiconductor chips having a semiconductor interposer
A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to...
US-8,132,459 System and method to determine mechanical resonance of an accelerometer
Systems and methods are provided for determining mechanical resonance of a sensor. In one embodiment, a system is provided that comprises a bias voltage source...
US-8,132,064 Selectively accessing test access ports in a multiple test access port environment
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-8,131,791 Decision feedback equalizer having parallel processing architecture
An integrated circuit includes a decision feedback equalizer (DFE) including a first and second digital equalizer logic including circuitry to compensate first...
US-8,131,232 Method and apparatus for antenna tuning
A method for tuning a transmitter in order to improve impedance matching to an antenna or to intermediate radio frequency stages uses an error detector that...
US-8,131,230 Method and system for FM transmitter coexistence
A system and method for operating an FM system and wireless networking system coexistent in a mobile wireless device. A mobile wireless device includes a...
US-8,130,889 Receive timing manager
A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition...
US-8,130,791 Receiver and method for processing a stream of data packets when an error occurred on the physical layer
A receiver which receives a stream of data packets including video data packets over a physical data link and drops data packets when an error on a physical...
US-8,130,667 Preamble group selection in random access of wireless networks
A transport block size (TBS) of a first uplink message (RACH Msg3) transmitted on a Physical Uplink Shared Channel (PUSCH) during a random access procedure in a...
US-8,130,653 Deletion request after number of failed acknowledgements to addition requests
Network circuitry and a method of operating the same in establishing and deleting a service flow in a wireless network. A network station receives a request,...
US-8,130,481 Electrostatic discharge trigger circuits for self-protecting cascode stages
Electrostatic discharge (ESD) protection circuits for self-protecting cascode stages are disclosed. In one example, an ESD protection circuit is described. A...
US-8,130,129 Analog-to-digital conversion
One embodiment of the present invention includes an analog-to-digital converter (ADC) system. The system includes an ADC configured to generate digital samples...
US-8,130,067 High frequency semiconductor transformer
A semiconductor transformer provides high frequency operation by forming the primary windings of the transformer around a section of magnetic material that has...
US-8,130,047 Open loop coarse tuning for a PLL
In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a...
US-8,130,040 Power amplifier with two transistors and traces forming two transformers
Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high...
US-8,130,032 Systems and methods for high-sensitivity detection of input bias current
The invention relates to systems and methods for high-sensitivity detection of input bias current. The invention more particularly relates to platforms and...
US-8,129,962 Low dropout voltage regulator with clamping
Apparatus and methods for reducing output load transients of a low dropout voltage regulator ("LDO") are disclosed herein. A voltage regulator includes an...
US-8,129,814 Schottky diode with silicide anode and anode-encircling P-type doped region
An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a...
US-8,129,682 On-chip calibration system and method for infrared sensor
A radiation sensor includes an integrated circuit radiation sensor chip (1A) including first (7) and second (8) thermopile junctions connected in series to form...
US-8,129,248 Method of producing bipolar transistor structures in a semiconductor process
In the method of producing bipolar transistor structures in a semiconductor process, an advanced epitaxial trisilane process can be used without the risk of...
US-8,129,246 Advanced CMOS using super steep retrograde wells
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer...
US-8,129,228 Manufacturing method for integrating a shunt resistor into a semiconductor package
An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to...
US-8,129,227 Semiconductor device having grooved leads to confine solder wicking
A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes...
US-8,129,224 Stud bumps as local heat sinks during transient power operations
A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding...
US-8,129,089 Use of blended solvents in defectivity prevention
The present invention provides a blended solvent for solubilizing an ultraviolet photoresist. The blended solvent comprises a mixture of from about 5 vol % to...
US-8,127,263 Improving routability of integrated circuit design without impacting the design area
Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined...
US-8,127,211 Adding known data to CRC processing without increased processing time
Cyclic redundancy check processing is applied advantageously to a set of input data that includes an unknown data portion and a data portion that is already...
US-8,127,189 Gates and sync circuitry connecting TAP to serial communications circuitry
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus....
US-8,126,707 Method and system for speech compression
Methods, encoders, and digital systems are provided for predictive encoding of speech parameters in which an input frame is encoded by quantizing a parameter...
US-8,126,681 Semiconductor outlier identification using serially-combined data transform processing methodologies
A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain...
US-8,126,401 Transmitter PLL with bandwidth on demand
An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator...
US-8,126,164 Digital compensation of analog volume control gain in a digital audio amplifier
A digital audio system including a combination of analog and digital volume control is disclosed. A variable power supply voltage biases a power amplifier for...
US-8,126,158 Reducing sound pressure of noise
A system comprising converter logic that introduces noise to a signal. The system also comprises amplifier logic that reduces a sound pressure associated with...
US-8,126,092 Multistage PN code acquisition circuit and method
A circuit for detecting a serial signal comprises a first circuit coupled to receive the serial signal during a predetermined plurality of time periods of...
US-8,125,885 Frequency offset estimation in orthogonal frequency division multiple access wireless networks
A method of wireless transmission for estimating the carrier frequency offset in a base station of a received transmission from a user equipment (UE) accessing...
US-8,125,830 Area-efficient electrically erasable programmable memory cell
Electrically erasable programmable "read-only" memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell...
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