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Patent # Description
US-9,497,442 3D camera using flash with structured light
An imaging device capable of capturing depth information or surface profiles of objects is disclosed herein. The imaging device uses an enclosed flashing unit...
US-9,497,097 Inserting sequence numbers into data blocks merged from data streams
A method of detecting lost data within a data stream by inserting sequence numbers within the stream. Network data blocks to be transmitted are assembled from...
US-9,497,060 Method and circuit for transmitting data
Methods and circuits for transmitting data are disclosed. An embodiment of a method includes transmitting a predetermined number of pulses during predetermined...
US-9,496,926 Galvanic isolator
A system on a package (SOP) can include a galvanic isolator. The galvanic isolator can include an input stage configured to transmit an input RF signal in...
US-9,496,828 System and method for envelope tracking power supply
An envelope tracking power supply has a multiple-output DC/DC converter, having an alternating current generating portion and a full rectifying portion. The...
US-9,496,388 Trench MOSFET having reduced gate charge
A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the...
US-9,496,359 Integrated circuit having chemically modified spacer surface
A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack...
US-9,496,327 High precision capacitor dielectric
A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic...
US-9,496,313 CMOS-based thermopile with reduced thermal conductance
An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently...
US-9,496,262 High mobility transistors
An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity...
US-9,496,252 ESD protection device with improved bipolar gain using cutout in the body well
An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base...
US-9,496,208 Semiconductor device having compliant and crack-arresting interconnect structure
A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first...
US-9,496,206 Flippable leadframe for packaged electronic system having vertically stacked chips and components
A leadframe (100) for electronic systems comprising a first sub-leadframe (110) connected by links (150) to a second sub-leadframe (120), the first and second...
US-9,496,198 Integration of backside heat spreader for thermal management
A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a...
US-9,496,171 Printed interconnects for semiconductor packages
A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package...
US-9,496,142 Dummy gate placement methodology to enhance integrated circuit performance
A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an...
US-9,496,024 Automatic latch-up prevention in SRAM
A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank...
US-9,496,007 Method and apparatus for generating piece-wise linear regulated supply
The disclosure provides a voltage regulator for generating piece-wise linear regulated supply voltage. The voltage regulator includes a first clamp circuit that...
US-9,495,982 Current-limiting in an amplifier system
One example includes an amplifier system. The system includes a gain stage configured to conduct a gain current in response to an input voltage. The system also...
US-9,494,656 Systems and methods for determining battery state of charge
Systems (50, 200) and methods for determining a state of charge of a battery (52, 102, 150, 202) are provided. The system (50, 200) includes a power source (56,...
US-9,494,648 Comparator with load signal output connected to timestamp value register
This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined...
US-9,494,643 Bi-directional TCK lead carrying TCK and frame data in/out signal
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication...
US-9,494,640 Parallel scan distributors and collectors and process of testing integrated circuits
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-9,491,838 LED matrix manager
Circuits for controlling a plurality of LEDs connected in series are disclosed herein. The circuit includes a plurality of switches, wherein each switch is...
US-9,491,573 Communication device for providing value-added information based upon content and/or context information
A communication device, for use in a communication network, provides value-added information to a user of the communication device. The communication device...
US-9,491,375 Method, system and computer program product for reducing a delay from panning a camera system
For reducing a delay from panning a camera system, an estimate is received of a physical movement of the camera system. In response to the estimate, a...
US-9,491,012 Direct over-sampled pulse shaping circuit with flip flops and LUT
Example embodiments of systems and methods of direct oversampled low PAR pulse shaping encapsulating DSSS spreading are disclosed herein. Pulse-shaping of a...
US-9,490,967 Communication system and method
A communication system includes a receiver for decoding data having three states of -1, 0, and 1. The receiver includes a first input coupled to a first data...
US-9,490,783 Area efficient multi bit flip flop topologies
The invention is an intelligent connection of the internal scan logic in a multi-bit flip-flop register. Individual bits in this register are connected in a...
US-9,490,747 Re-configurable single transformer quadrature voltage controlled oscillator
A quadrature voltage controlled oscillator (QVCO). The QVCO includes a first node for providing a first quadrature signal, a second node for providing a second...
US-9,490,518 System for launching a signal into a dielectric waveguide
A system is provided for transmitting sub-terahertz electro-magnetic radio frequency (RF) signals using a dielectric waveguide (DWG) having a dielectric core...
US-9,490,162 Use of dielectric slots for reducing via resistance in dual damascene process
An integrated circuit may include dual damascene interconnects formed using a via-first dual damascene process or a trench-first dual damascene process. The...
US-9,490,143 Method of fabricating semiconductors
A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The...
US-9,489,925 Using natural movements of a hand-held device to manipulate digital content
A mobile device, such as a smart phone, is provided with a camera. Digital content displayed on display screen of the mobile device may be manipulated in...
US-9,489,332 System and method for virtual hardware memory protection
A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus...
US-9,489,314 Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC
This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip...
US-9,489,307 Multi domain bridge with auto snoop response
An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each...
US-9,489,208 Operating a pipeline flattener in order to track instructions for complex breakpoints
A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a...
US-9,489,197 Highly efficient different precision complex multiply accumulate to enhance chip rate functionality in DSSS...
This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using...
US-9,489,098 Method, apparatus and system for level shifting of common mode voltage from input to output for capacitive...
A circuit for a level shifting of common mode voltage. The circuit includes a first amplifier, wherein the input of the first amplifier is coupled to a voltage...
US-9,489,093 Capacitive sensing apparatus and methods
One or more waveform generators impose an input waveform across touch sensor components. Phase shift detection logic measures a phase shift between the input...
US-9,487,397 Coatings for relatively movable surfaces
A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating...
US-9,485,520 Parallel motion estimation in video coding
Methods for improved parallel motion estimation are provided that decouple the merging candidate list derivation and motion estimation for merge mode and skip...
US-9,485,506 Method and system for constraining slice header processing overhead in video coding
A method for encoding a picture of a video sequence in a bit stream that constrains slice header processing overhead is provided. The method includes computing...
US-9,484,979 Switching between transmit and receive modes in a wireless transceiver
A wireless transceiver decodes a receive signal to extract data contained in the receive signal. A processing block contained in the wireless transceiver then...
US-9,484,921 LVDS input circuit with comparators, or gate, and multiplexer
First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an...
US-9,484,913 Emulation of LED input characteristics in BICMOS process
An LED input emulator to interface a signal source designed for use with an LED optocoupler, to capacitive or other galvanic isolation circuitry, emulating LED...
US-9,484,858 Inductive coupled pass transistor quadrature voltage controlled oscillator
A quadrature voltage controlled oscillator (QVCO) for providing an oscillating output signal. The QVCO includes a first oscillating circuit for producing a...
US-9,484,630 Chip to dielectric waveguide interface for sub-millimeter wave communications link
In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue....
US-9,484,614 Dielectric waveguide signal divider
A dielectric waveguide (DWG) has a longitudinal core member with a first dielectric constant value surrounded by a cladding with a cladding dielectric constant...
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