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PoP precursor with interposer for top package bond pad pitch compensation
An electronic assembly adapted for forming package on package (PoP) devices includes a package substrate having a molded IC die thereon that defines a mold cap...
CVD showerhead alignment apparatus
A method and apparatus for aligning a CVD showerhead, comprising engaging a showerhead stem clamp with a showerhead stem outside of a process chamber of the CVD...
Energy-aware scheduling of application execution
A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be...
Concurrent production of CRC syndromes for different data blocks in an
input data sequence
Cyclic redundancy check (CRC) processing is applied to a received sequence of data blocks that are defined by respective sequences of sets of parallel data. For...
Electronic devices, information products, processes of manufacture and
apparatus for enabling code decryption...
An electronic device (1640) includes a non-volatile store (1620) holding a plurality of encrypted sub-applications (SubApp n), and application-specific...
Process, circuits, devices, and systems for encryption and decryption and
other purposes, and process making
A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a...
Reduced calculations in determining intra-prediction type method and
The method, system, and apparatus of source statistics based intra prediction type is disclosed. In one embodiment, a method includes classifying a four-pixel...
Downlink synchronization channel and methods for cellular systems
The present invention provides a method of operating a base station transmitter. The method includes providing a cellular downlink synchronization signal having...
System and method for reducing visible speckle in a projection visual
The invention provides an apparatus for reducing speckle in a projection visual display (PVD) system, a method of reducing visible speckle in a PVD system and a...
System and method for operating light processing electronic devices
A system and method for operating an electronic device used in light processing. A method comprises altering a spatial relationship between a spatial light...
Illumination source and method therefor
An illumination source and a method therefor. A light source includes a light circuit configured to process light and direct light, and a lighting element...
System and method for combining interlaced video frames
System and method for combining interlaced video frames. A method embodiment for displaying a de-interlaced video sequence includes receiving a video stream,...
Simplified, extendable, edge-based watchdog for DLL
A delay locked loop (DLL) is provided. Within this DLL is a watchdog circuit that determines whether harmonic lock is present. Based on this measurement, the...
Device-under-test power management
One embodiment of the present invention includes a system for managing power to a plurality of devices-under-test (DUTs). The system comprises a DUT test system...
Method and apparatus for switching a synchronous DC/DC converter between a
PWM mode of operation and a...
A synchronous buck converter operates in a PWM mode of operation and switches to light-load mode of operation under a light-load condition. When operating in...
Schottky diode with minimal vertical current flow
A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant...
Flexible interposer for stacking semiconductor chips and connecting same
A semiconductor device with a first (101) and a second (111) semiconductor chip assembled on an insulating flexible interposer (120). The interposer, preferably...
Photoresist dispenser with nozzle arrangement for cone-shaped spray
A cleaning system which can be integrated into a coater track system for use in the production of semiconductor devices and methods for its use are provided....
Parallel scan paths with header data circuitry and header return circuitry
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test...
Sampling mixer with asynchronous clock and signal domains
A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having...
System and method for projection systems using sequential color techniques
A projection system using a sequential color filter is provided. The sequential color filter utilizes various colors, such as red, blue, and green, divided into...
Methods and apparatus to reduce the stopping time of spindle motors
Methods and apparatus to reduce the stopping time of a spindle motor are disclosed. An example method includes detecting a dissipation current flowing in a...
Two terminal quantum device using MOS capacitor structure
A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate....
Silicon dioxide cantilever support and method for silicon etched
A semiconductor device includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality...
Formation of shallow junctions by diffusion from a dielectric doped by
cluster or molecular ion beams
A process for forming diffused region less than 20 nanometers deep with an average doping dose above 10.sup.14 cm.sup.-2 in an IC substrate, particularly LDD...
Method and apparatus for code optimization
A system comprising a compiler that compiles source-level code to generate an intermediate-level instruction comprising a predetermined component. The...
Modifying an instruction stream using one or more bits to replace an
instruction or to replace an instruction...
A processor comprising fetch logic adapted to fetch instructions from memory and decode logic coupled to the fetch logic and adapted to decode the fetched...
Rate/diversity adaptation sending speech in first and second packets
Packets of real-time information are sent with a source rate greater than zero kilobits per second, and a time or path or combined time/path diversity rate...
Receiver dynamically switching to pseudo differential mode for SOC spur
A low noise amplifier in an integrated circuit, the circuit having a digital portion and an analog portion on a common substrate, the digital portion having at...
Wireless MIMO transmitter with antenna and tone precoding blocks
Various wireless precoding systems and methods are presented. In some embodiments, a wireless transmitter comprises an antenna precoding block, a transform...
Systems and methods for efficient channel classification
Embodiments provide a system and method for efficiently classifying different channel types in an orthogonal frequency division multiplexing (OFDM) system....
System and method for converting scan data
An ultrasound device generates polar-coordinate image data divided up into an (N.times.M) array of polar-coordinate image data blocks; a first external memory...
Low phase noise frequency synthesizer
Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may...
Reference circuit with reduced current startup
An apparatus is provided. The apparatus comprises a reference circuit and a startup circuit. The reference circuit is adapted to provide a startup current,...
Gate structure and method
A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.
Links and chains verification and validation methodology for digital
The links and chains (LNC) of this invention is an applications verification and validation (AVV) methodology. LNC is a hierarchical and systematic approach...
Tap and control with data I/O, TMS, TDI, and TDO
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
Comparator circuitry connected to input and output of tristate buffer
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
Phase locking method for frequency domain time scale modification based on
a bark-scale spectral partition
This invention improves the perceived quality of frequency-domain time scale modification by selection of spectral bands used in phase locking based upon a Bark...
System and method for avoiding interference in a dual-signal device
A dual-signal wireless transceiver is provided, comprising: a first wireless transceiver circuit configured to transmit and receive first signals using a first...
Stereo synthesizer using comb filters and intra-aural differences
A method for creating a stereophonic sound image out of a monaural signal combines two sub-methods. Comb filters decorrelate the left and right channel signals....
Closed-loop transmit diversity scheme in frequency selective multipath
Closed loop multiple-antenna wireless communications system with antenna weights determined by maximizing a composite channel signal-to-interference-plus-noise...
Temperature dependent back-bias for a memory array
The present invention provides a thermostatic bias controller for use with a memory array. The thermostatic bias controller includes a temperature sensing...
LLC soft start by operation mode switching
An embodiment of the invention provides a method of reducing surge current in an LLC converter. The LLC converter comprises a switching circuit having a first...
Error correction method and apparatus
A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output...
Logic applying different bit positions to respective scan paths
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
Embedded sar based active gain capacitance measurement system and method
A system for measuring a capacitor (C.sub.SENj) precharges a CDAC (23) in a SAR converter (17) to a reference voltage (V.sub.AZ) and also precharges a first...
Methods and apparatus to facilitate ground fault detection with a single
coil and an oscillator
Methods and apparatus to facilitate ground fault detection with a single coil and an oscillator are disclosed. An example ground fault detection device includes...
Parallel redundant single-electron device and method of manufacture
A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped...
Method of planarizing a semiconductor device
A process of forming a semiconductor process fabricated device which contains a trench, hole or gap filled with a conformally deposited material is disclosed. A...