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Patent # Description
US-8,015,476 CRC syndrome generation for multiple data input widths
A sequence of cyclic redundancy check syndromes can be produced based on a received sequence of sets of parallel data wherein different ones of the sets can...
US-8,015,475 Erasure decoding for receivers
A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system...
US-8,015,466 Adapting scan-BIST architectures for low power operation
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-8,015,464 Segmented scan paths with cache bit memory inputs
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and...
US-8,015,463 IC with TAP, DIO interface, SIPE, and PISO circuits
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-8,014,098 Technique for duty cycle shift in hard disk drive write system
A circuit for providing a write current having a programmably adjustable duty cycle in a hard disk drive write channel has a differential pair gain circuit for...
US-8,013,911 Method for mixing high-gain and low-gain signal for wide dynamic range image sensor
A wide dynamic range image sensor method combines the response of high-gain sensing cells and low-gain sensing cells with better linearity than the prior art. A...
US-8,013,772 Reduced area digital-to-analog converter
One embodiment of the invention includes a digital-to-analog converter (DAC) system. A resistive ladder comprises a plurality of resistors having an...
US-8,013,763 Method and apparatus for unit interval calculation
A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval...
US-8,013,677 One-sided switching pulse width modulation amplifiers
One-sided pulse width modulated (PWM) amplifiers are disclosed. An example amplifier includes an integrator to receive first and second analog signals, and to...
US-8,013,655 Apparatus and method for efficient level shift
An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level...
US-8,013,635 Multi-mode circuit and a method for preventing degradation in the multi-mode circuit
Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the...
US-8,013,634 LVDS data input circuit with multiplexer selecting data out input
First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an...
US-8,012,879 Etching method using an at least semi-solid media
An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively...
US-8,012,877 Backside nitride removal to reduce streak defects
Exemplary embodiments provide a method for fabricating an integrated circuit (IC) device with reduced streak defects. In one embodiment, the IC device structure...
US-8,012,844 Method of manufacturing an integrated circuit
A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR),...
US-8,012,842 Method for fabricating isolated integrated semiconductor structures
An integrated semiconductor structure that has first and second bipolar transistor structures. The first bipolar transistor structure has a doped tank region in...
US-8,012,319 Multi-chambered metal electrodeposition system for semiconductor substrates
A multi-chambered system for electroplating metal layers on a semiconductor substrate. The system comprises a fluid reservoir having at least a first chamber...
US-RE42,681 Wireless system with transmitter having multiple transmit antennas and combining open loop and closed loop...
A wireless communication system (40). The system comprises transmitter circuitry (42) comprising encoder circuitry (44) for receiving a plurality of symbols...
US-8,010,857 Input/output boundary cells and output data summing scan cell
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one...
US-8,010,818 Power efficient method for controlling an oscillator in a low power synchronous system with an asynchronous I2C bus
In a method and apparatus for saving power in a device coupled to a bus, the device is placed to operate in a power saving mode by powering off a selective...
US-8,009,688 Decoding packets with deadlines in communications channels processing unit
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing...
US-8,009,546 Over current protection device
An over current protection device is described. It includes a plurality of input channels for receiving an input signal; a plurality of low pass filters coupled...
US-8,009,395 Methods and apparatus for over-voltage protection of device inputs
Methods and apparatus for over-voltage protection of device inputs are disclosed. An example apparatus to protect a device from an over-voltage condition...
US-8,008,969 Single supply class-D amplifier
Traditionally, switching amplifiers (i.e., class-D and class-G) with negative supply rails had issues with direct current (DC) power loss, included large...
US-8,008,968 Multipath amplifier
Because of variations in open loop gain and bandwidth in successive approximate register (SAR) analog-to-digital converters (ADCs), designing amplifiers with...
US-8,008,216 Nitrogen profile in high-K dielectrics using ultrathin disposable capping layers
Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric to improve transistor...
US-8,008,200 Poison-free and low ULK damage integration scheme for damascene interconnects
A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra...
US-8,008,183 Dual capillary IC wirebonding
The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual...
US-8,008,131 Semiconductor chip package assembly method and apparatus for countering leadfinger deformation
The invention provides semiconductor chip packages, tools, and methods for preventing and for correcting leadfinger deformation caused during wirebonding in...
US-8,006,151 TAP and shadow port operating on rising and falling TCK
The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform...
US-8,005,153 Method and apparatus for increasing the number of orthogonal signals using block spreading
Embodiments of the invention apply block spreading to transmitted signals to increase the number orthogonally multiplexed signals. The principle of the...
US-8,004,860 Radiofrequency and electromagnetic interference shielding
An electrical device comprising an electronic component mounted to a surface of a printed circuit board, a ground connection on said surface, and...
US-8,004,444 ADC chopping transconductor having two pairs of cascode transistors
A chopping transconductor includes an transconductor input stage coupled with input signals of the chopping transconductor; a chopping switch coupled with an...
US-8,004,366 Area and power efficient, high swing and monolitihic ground centered headphone amplifier circuit operable on a...
A minimal area, power efficient, high swing and monolithic ground centered headphone amplifier circuit operable on a low voltage. An input amplifier stage...
US-8,004,298 IC with first and second distributors collectors and scan paths
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-8,004,248 Systems and methods for multi-mode battery charging
Various systems and methods for battery charging are disclosed herein. As just one example, a battery charger is disclosed that includes a current feedback loop...
US-8,004,051 Lateral trench MOSFET having a field plate
One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes...
US-8,002,611 Chemical mechanical polishing pad having improved groove pattern
A chemical mechanical polishing pad and method for chemical-mechanical polishing is provided, wherein the polishing pad has a plurality of first mesas and one...
US-8,001,436 Changing scan paths shifting by changing mode select input state
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...
US-8,001,435 Register selection circuitry receiving select signals from test interfaces
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-8,001,427 Method and system of indexing into trace data based on entries in a log buffer
A method and system of indexing into trace data based on entries in a log buffer. At least some of the illustrative embodiments are methods comprising executing...
US-8,000,921 Method and apparatus for synchronizing signals in a testing system
The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal...
US-8,000,670 Removing close-in interferers through a feedback loop
System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer...
US-8,000,428 All-digital frequency synthesis with DCO gain calculation
An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word...
US-8,000,425 Methods and apparatus to provide clock resynchronization in communication networks
Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein...
US-8,000,200 HFM enable control system
A modulation control system for use with a high frequency modulator is described. This system comprises a latch for selectively receiving enable signals,...
US-7,999,833 Deinterleaving transpose circuits in digital display systems
The present invention provides a method and apparatus of converting a stream of pixel data in space and time into a stream of bitplane data. In particular, the...
US-7,999,793 Median and mean coherent filter and method for eliminating noise in touch screen controller
A touch screen system includes a touch screen assembly (30,31) and a touch screen controller (1A) coupled to terminals (24,25,26,27) of the touch screen...
US-7,999,710 Multistage chopper stabilized delta-sigma ADC with reduced offset
A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential...
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