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Patent # Description
US-8,053,322 Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated...
A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate...
US-8,053,296 Capacitor formed on a recrystallized polysilicon layer
The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The...
US-8,053,285 Thermally enhanced single inline package (SIP)
In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A...
US-8,053,256 Variable thickness single mask etch process
The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an...
US-8,053,252 Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean
A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A...
US-8,052,286 System and method for utilizing a scanning beam to display an image
A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first...
US-8,051,399 IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing...
An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which an output of a cell...
US-8,051,398 Test method and system for characterizing and/or refining an IC design cycle
Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical...
US-8,051,391 Method for layout of random via arrays in the presence of strong pitch restrictions
Exemplary embodiments provide a method for laying out an integrated circuit ("IC") design and the IC design layout. In one embodiment, the IC design layout can...
US-8,051,351 DDR circuit with addressable TAP linking circuitry and plural TAPS
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface...
US-8,051,349 Link instruction register with instruction register, and gate and multiplexer
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing...
US-8,051,347 Scan-enabled method and system for testing a system-on-chip
Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of...
US-8,051,313 Apparatus, system and method of power state control
An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for...
US-8,051,285 Battery processor circuitry with separate public and private bus
Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In...
US-8,050,934 Local pitch control based on seamless time scale modification and synchronized sampling rate conversion
This invention locally controls the pitch of speech and audio signals. The invention is based on a seamless time scale modification (S-TSM) scheme connected to...
US-8,050,903 Apparatus and method for checkpointing simulation data in a simulator
Apparatus for storing all logic simulation signal values generated by a logic simulator during a simulation run is provided. The apparatus includes a runtime...
US-8,050,657 Tamper resistant circuitry and portable electronic devices
A portable electronic device. Tamper-resistant circuitry for inclusion in an electronic device. The tamper-resistant circuitry comprises wireless receiving...
US-8,050,641 Limiting the power consumption of a wireless electronic system
In at least some disclosed embodiments, a wireless electronic system includes a decoder module coupled to a processor. The decoder module is configured to send...
US-8,050,375 Digital phase locked loop with integer channel mitigation
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked...
US-8,050,368 Nonlinear adaptive phase domain equalization for multilevel phase coded demodulators
A novel and useful apparatus for and method of nonlinear adaptive phase domain equalization for multilevel phase coded demodulators. The invention improves the...
US-8,050,254 IC reconstructing lost speech packets from secondary stage partial data
A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice...
US-8,050,148 Flash time stamp apparatus
One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the...
US-8,049,946 Lubricating micro-machined devices using fluorosurfactants
A method of lubricating MEMS devices using fluorosurfactants 42. Micro-machined devices, such as a digital micro-mirror device (DMD.TM.) 940, which make...
US-8,049,654 Digital trimming of SAR ADCs
Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data...
US-8,049,562 Amplifier with improved input resistance and controlled common mode
An amplifier includes a first pair of transistors (the first pair) that defines a first output, each transistor of the first pair having a gate coupled to a...
US-8,049,555 Low leakage sampling switch
An electronic device includes a cascade of a plurality of transistors. Each transistor of the cascade receives an input voltage at a first terminal of its...
US-8,049,534 Low-power high-speed differential driver with precision current steering
In bipolar CMOS or BiCMOS process technologies, drivers (such as mixed mode or hybrid mode drivers) using both bipolar and CMOS transistors (i.e., field effect...
US-8,049,465 Systems, methods and circuits for determining micro-short
Various systems and methods for determining micro-shorts are disclosed. For example, some embodiments of the present invention provide battery systems including...
US-8,049,320 Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom
A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive...
US-8,049,312 Semiconductor device package and method of assembly thereof
A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a...
US-8,049,254 Semiconductor device with gate-undercutting recessed region
A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a...
US-8,049,214 Degradation correction for finFET circuits
A pair of split-gate fin field effect transistors (finFETs) in an IC, each containing a signal gate and a control gate, in which an adjustable voltage source,...
US-8,049,119 Integrated circuit package having integrated faraday shield
A packaged integrated circuit (IC) (100) includes a first substrate (110) comprising a first plurality of layers and a first circuit coupling features (112) at...
US-8,048,750 Method to enhance channel stress in CMOS processes
The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier...
US-8,048,358 Pop semiconductor device manufacturing method
The objective of the invention is to prevent electrostatic destruction of semiconductor chips during resin molding. With the semiconductor device manufacturing...
US-8,047,660 Projection system and method including spatial light modulator and compact diffractive optics
A method and apparatus for a projection display system includes a spatial light modulator and a volume illumination hologram. The spatial light modulator...
US-8,046,748 Method and system to emulate an M-bit instruction set
A method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an...
US-8,046,651 Compare circuit receiving scan register and inverted clock flip-flop data
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device...
US-8,046,650 TAP with control circuitry connected to device address port
The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without...
US-8,046,649 Scan circuits formed peripheral of core circuits with control leads
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test...
US-8,046,228 Voice activated hypermedia systems using grammatical metadata
This is a voice activated Hypermedia system using grammatical metadata, the system comprising: a speech user agent; a browsing module; and an information...
US-8,046,199 System and method for computing parameters for a digital predistorter
Digital predistortion system, methods and circuitry for adapting a predistortion system linearizing a non-linear element. The system is a multiply partitioned...
US-8,045,941 Methods and apparatus to implement receiver linearity enhancement
Methods and apparatus to implement receiver linearity enhancement are described. One example method includes controlling receiver gain by determining a level of...
US-8,045,922 Apparatus for and method of bluetooth and wireless local area network coexistence using a single antenna in a...
A novel and useful apparatus for and method of providing a mechanism for achieving coexistence between a Bluetooth system and WLAN system collocated in the same...
US-8,045,836 System and method for recording high frame rate video, replaying slow-motion and replaying normal speed with...
A method to record high frame rate video, compatible with existing industry standards, that permits selecting either slow-motion playback or true speed playback...
US-8,045,670 Interpolative all-digital phase locked loop
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked...
US-8,045,662 Binary ripple counter sampling with adjustable delays
The output bits of a binary ripple counter are used to control the sampling of those output bits, thereby ensuring accurate sampling. A sampler is provided with...
US-8,045,661 System and method for blind identification of multichannel finite impulse response filters using an iterative...
A system for, and method of, blind identification of multichannel finite impulse response filters. In one embodiment, the system includes: (1) a decomposition...
US-8,045,632 Systems and methods for dual-carrier modulation encoding and decoding
Systems and methods for dual-carrier modulation (DCM) encoding and decoding for communication systems. Some embodiments comprise a DCM encoder for applying a...
US-8,045,576 Methods and apparatus to manage power consumption in wireless local area network devices
Methods and apparatus to manage power consumption in wireless devices are disclosed. A disclosed example apparatus comprises performing a first received signal...
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