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Patent # Description
US-8,026,507 Two terminal quantum device using MOS capacitor structure
A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate....
US-8,026,177 Silicon dioxide cantilever support and method for silicon etched structures
A semiconductor device includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality...
US-8,026,135 Formation of shallow junctions by diffusion from a dielectric doped by cluster or molecular ion beams
A process for forming diffused region less than 20 nanometers deep with an average doping dose above 10.sup.14 cm.sup.-2 in an IC substrate, particularly LDD...
US-8,024,716 Method and apparatus for code optimization
A system comprising a compiler that compiles source-level code to generate an intermediate-level instruction comprising a predetermined component. The...
US-8,024,554 Modifying an instruction stream using one or more bits to replace an instruction or to replace an instruction...
A processor comprising fetch logic adapted to fetch instructions from memory and decode logic coupled to the fetch logic and adapted to decode the fetched...
US-8,024,182 Rate/diversity adaptation sending speech in first and second packets
Packets of real-time information are sent with a source rate greater than zero kilobits per second, and a time or path or combined time/path diversity rate...
US-8,023,919 Receiver dynamically switching to pseudo differential mode for SOC spur reduction
A low noise amplifier in an integrated circuit, the circuit having a digital portion and an analog portion on a common substrate, the digital portion having at...
US-8,023,589 Wireless MIMO transmitter with antenna and tone precoding blocks
Various wireless precoding systems and methods are presented. In some embodiments, a wireless transmitter comprises an antenna precoding block, a transform...
US-8,023,577 Systems and methods for efficient channel classification
Embodiments provide a system and method for efficiently classifying different channel types in an orthogonal frequency division multiplexing (OFDM) system....
US-8,023,359 System and method for converting scan data
An ultrasound device generates polar-coordinate image data divided up into an (N.times.M) array of polar-coordinate image data blocks; a first external memory...
US-8,022,778 Low phase noise frequency synthesizer
Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may...
US-8,022,686 Reference circuit with reduced current startup
An apparatus is provided. The apparatus comprises a reference circuit and a startup circuit. The reference circuit is adapted to provide a startup current,...
US-8,021,990 Gate structure and method
A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.
US-8,020,126 Links and chains verification and validation methodology for digital devices
The links and chains (LNC) of this invention is an applications verification and validation (AVV) methodology. LNC is a hierarchical and systematic approach...
US-8,020,059 Tap and control with data I/O, TMS, TDI, and TDO
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
US-8,020,057 Comparator circuitry connected to input and output of tristate buffer
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
US-8,019,598 Phase locking method for frequency domain time scale modification based on a bark-scale spectral partition
This invention improves the perceived quality of frequency-domain time scale modification by selection of spectral bands used in phase locking based upon a Bark...
US-8,019,280 System and method for avoiding interference in a dual-signal device
A dual-signal wireless transceiver is provided, comprising: a first wireless transceiver circuit configured to transmit and receive first signals using a first...
US-8,019,086 Stereo synthesizer using comb filters and intra-aural differences
A method for creating a stereophonic sound image out of a monaural signal combines two sub-methods. Comb filters decorrelate the left and right channel signals....
US-8,018,903 Closed-loop transmit diversity scheme in frequency selective multipath channels
Closed loop multiple-antenna wireless communications system with antenna weights determined by maximizing a composite channel signal-to-interference-plus-noise...
US-8,018,780 Temperature dependent back-bias for a memory array
The present invention provides a thermostatic bias controller for use with a memory array. The thermostatic bias controller includes a temperature sensing...
US-8,018,740 LLC soft start by operation mode switching
An embodiment of the invention provides a method of reducing surge current in an LLC converter. The LLC converter comprises a switching circuit having a first...
US-8,018,369 Error correction method and apparatus
A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output...
US-8,018,241 Logic applying different bit positions to respective scan paths
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-8,018,238 Embedded sar based active gain capacitance measurement system and method
A system for measuring a capacitor (C.sub.SENj) precharges a CDAC (23) in a SAR converter (17) to a reference voltage (V.sub.AZ) and also precharges a first...
US-8,018,235 Methods and apparatus to facilitate ground fault detection with a single coil and an oscillator
Methods and apparatus to facilitate ground fault detection with a single coil and an oscillator are disclosed. An example ground fault detection device includes...
US-8,017,935 Parallel redundant single-electron device and method of manufacture
A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped...
US-8,017,493 Method of planarizing a semiconductor device
A process of forming a semiconductor process fabricated device which contains a trench, hole or gap filled with a conformally deposited material is disclosed. A...
US-8,017,439 Dual carrier for joining IC die or wafers to TSV wafers
A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer...
US-8,017,410 Power semiconductor devices having integrated inductor
An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a...
US-8,015,513 OPC models generated from 2D high frequency test patterns
A method of generating a scalable OPC model for composing reticle pattern files from IC layouts using 2D test patterns is disclosed. The 2D test patterns...
US-8,015,476 CRC syndrome generation for multiple data input widths
A sequence of cyclic redundancy check syndromes can be produced based on a received sequence of sets of parallel data wherein different ones of the sets can...
US-8,015,475 Erasure decoding for receivers
A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system...
US-8,015,466 Adapting scan-BIST architectures for low power operation
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-8,015,464 Segmented scan paths with cache bit memory inputs
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and...
US-8,015,463 IC with TAP, DIO interface, SIPE, and PISO circuits
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-8,014,098 Technique for duty cycle shift in hard disk drive write system
A circuit for providing a write current having a programmably adjustable duty cycle in a hard disk drive write channel has a differential pair gain circuit for...
US-8,013,911 Method for mixing high-gain and low-gain signal for wide dynamic range image sensor
A wide dynamic range image sensor method combines the response of high-gain sensing cells and low-gain sensing cells with better linearity than the prior art. A...
US-8,013,772 Reduced area digital-to-analog converter
One embodiment of the invention includes a digital-to-analog converter (DAC) system. A resistive ladder comprises a plurality of resistors having an...
US-8,013,763 Method and apparatus for unit interval calculation
A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval...
US-8,013,677 One-sided switching pulse width modulation amplifiers
One-sided pulse width modulated (PWM) amplifiers are disclosed. An example amplifier includes an integrator to receive first and second analog signals, and to...
US-8,013,655 Apparatus and method for efficient level shift
An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level...
US-8,013,635 Multi-mode circuit and a method for preventing degradation in the multi-mode circuit
Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the...
US-8,013,634 LVDS data input circuit with multiplexer selecting data out input
First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an...
US-8,012,879 Etching method using an at least semi-solid media
An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively...
US-8,012,877 Backside nitride removal to reduce streak defects
Exemplary embodiments provide a method for fabricating an integrated circuit (IC) device with reduced streak defects. In one embodiment, the IC device structure...
US-8,012,844 Method of manufacturing an integrated circuit
A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR),...
US-8,012,842 Method for fabricating isolated integrated semiconductor structures
An integrated semiconductor structure that has first and second bipolar transistor structures. The first bipolar transistor structure has a doped tank region in...
US-8,012,319 Multi-chambered metal electrodeposition system for semiconductor substrates
A multi-chambered system for electroplating metal layers on a semiconductor substrate. The system comprises a fluid reservoir having at least a first chamber...
US-RE42,681 Wireless system with transmitter having multiple transmit antennas and combining open loop and closed loop...
A wireless communication system (40). The system comprises transmitter circuitry (42) comprising encoder circuitry (44) for receiving a plurality of symbols...
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