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Patent # Description
US-8,055,231 RF feedback engine coupled to receiver low noise amplifier
Methods and apparatus to perform radio frequency (RF) analog-to-digital conversion are described. According to one example, a receiver includes an amplifier to...
US-8,055,217 Adaptive complex gain predistorter for a transmitter
Symbols are transmitted in a Cartesian transmitter by pre-distorting an input signal X having in-phase and quadrature components using a first compensation...
US-8,054,914 Noise variance estimation
A method and system for estimating noise variance. A method for noise variance estimation comprises receiving a first multi-sample symbol and receiving a second...
US-8,054,912 Large-dynamic-range lookup table for a transmitter predistorter and system and method employing the same
A predistorters for use with a nonlinear element and methods of predistorting for a nonlinear element for use in a 3G, e.g., WCDMA transmitter. In one...
US-8,054,861 Primary, secondary, and tertiary codes synchronizing slots in a frame
A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a...
US-8,054,823 Mapping schemes for secondary synchronization signal scrambling
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the...
US-8,054,810 Interleaver for transmit diversity
The present invention exploits the benefits obtainable from using transmit diversity by designing the size of the interleaver matrix to avoid the case where...
US-8,054,742 System and method for sidelobe suppression in communications systems
A system and method for sidelobe suppression in OFDM communications systems is provided. A method for transmitting an information symbol having a plurality of...
US-8,054,652 Systems and methods for off-time control in a voltage converter
Various embodiments of the present invention provide voltage converters and methods for using such. As one example, a voltage converter is disclosed that...
US-8,054,552 Lens array element and method
According to one embodiment of the present invention a method for directing light onto a digital micromirror device is disclosed that includes the steps of...
US-8,054,529 System and method for displaying images
System and method for simultaneous display of multiple images using a single light modulator array. A preferred embodiment comprises a light source that...
US-8,054,358 Solid state image pickup device
This invention improves linearity of a solid-state image pickup device beyond that of the prior art source follower to improve image quality. The image pickup...
US-8,054,103 Synchronous clock multiplexing and output-enable
A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals...
US-8,054,057 Low dropout regulator testing system and device
A device for testing low dropout (LDO) regulator is disclosed. In one embodiment, a device for testing LDO regulators includes an absolute value measurement...
US-8,054,056 Frequency regulated hysteretic average current mode converter
A switch mode power converter that precisely controls average switching current and operating frequency. The switching control operative in hysteretic average...
US-8,053,876 Multi lead frame power package
According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead...
US-8,053,873 IC having voltage regulated integrated Faraday shield
An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit...
US-8,053,349 BGA package with traces for plating pads under the chip
A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching...
US-8,053,324 Method of manufacturing a semiconductor device having improved transistor performance
In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by...
US-8,053,322 Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated...
A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate...
US-8,053,296 Capacitor formed on a recrystallized polysilicon layer
The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The...
US-8,053,285 Thermally enhanced single inline package (SIP)
In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A...
US-8,053,256 Variable thickness single mask etch process
The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an...
US-8,053,252 Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean
A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A...
US-8,052,286 System and method for utilizing a scanning beam to display an image
A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first...
US-8,051,399 IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing...
An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which an output of a cell...
US-8,051,398 Test method and system for characterizing and/or refining an IC design cycle
Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical...
US-8,051,391 Method for layout of random via arrays in the presence of strong pitch restrictions
Exemplary embodiments provide a method for laying out an integrated circuit ("IC") design and the IC design layout. In one embodiment, the IC design layout can...
US-8,051,351 DDR circuit with addressable TAP linking circuitry and plural TAPS
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface...
US-8,051,349 Link instruction register with instruction register, and gate and multiplexer
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing...
US-8,051,347 Scan-enabled method and system for testing a system-on-chip
Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of...
US-8,051,313 Apparatus, system and method of power state control
An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for...
US-8,051,285 Battery processor circuitry with separate public and private bus
Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In...
US-8,050,934 Local pitch control based on seamless time scale modification and synchronized sampling rate conversion
This invention locally controls the pitch of speech and audio signals. The invention is based on a seamless time scale modification (S-TSM) scheme connected to...
US-8,050,903 Apparatus and method for checkpointing simulation data in a simulator
Apparatus for storing all logic simulation signal values generated by a logic simulator during a simulation run is provided. The apparatus includes a runtime...
US-8,050,657 Tamper resistant circuitry and portable electronic devices
A portable electronic device. Tamper-resistant circuitry for inclusion in an electronic device. The tamper-resistant circuitry comprises wireless receiving...
US-8,050,641 Limiting the power consumption of a wireless electronic system
In at least some disclosed embodiments, a wireless electronic system includes a decoder module coupled to a processor. The decoder module is configured to send...
US-8,050,375 Digital phase locked loop with integer channel mitigation
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked...
US-8,050,368 Nonlinear adaptive phase domain equalization for multilevel phase coded demodulators
A novel and useful apparatus for and method of nonlinear adaptive phase domain equalization for multilevel phase coded demodulators. The invention improves the...
US-8,050,254 IC reconstructing lost speech packets from secondary stage partial data
A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice...
US-8,050,148 Flash time stamp apparatus
One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the...
US-8,049,946 Lubricating micro-machined devices using fluorosurfactants
A method of lubricating MEMS devices using fluorosurfactants 42. Micro-machined devices, such as a digital micro-mirror device (DMD.TM.) 940, which make...
US-8,049,654 Digital trimming of SAR ADCs
Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data...
US-8,049,562 Amplifier with improved input resistance and controlled common mode
An amplifier includes a first pair of transistors (the first pair) that defines a first output, each transistor of the first pair having a gate coupled to a...
US-8,049,555 Low leakage sampling switch
An electronic device includes a cascade of a plurality of transistors. Each transistor of the cascade receives an input voltage at a first terminal of its...
US-8,049,534 Low-power high-speed differential driver with precision current steering
In bipolar CMOS or BiCMOS process technologies, drivers (such as mixed mode or hybrid mode drivers) using both bipolar and CMOS transistors (i.e., field effect...
US-8,049,465 Systems, methods and circuits for determining micro-short
Various systems and methods for determining micro-shorts are disclosed. For example, some embodiments of the present invention provide battery systems including...
US-8,049,320 Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom
A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive...
US-8,049,312 Semiconductor device package and method of assembly thereof
A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a...
US-8,049,254 Semiconductor device with gate-undercutting recessed region
A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a...
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