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Partial timing modeling for gate level simulation
Various apparatuses, methods and systems for creating an integrated circuit and performing a gate level simulation of a circuit are disclosed herein. For...
Testing of integrated circuits using test module
A method and apparatus for testing of integrated circuits using a Direct Memory Load Execute Dump (DMLED) test module. The method includes loading a test case...
Determining bit error rate using single data burst
A communication system includes a transceiver capable of receiving a data burst as part of a paging block and a processing logic capable of comparing at least...
Satellite positioning system receiver utilizing broadcast doppler
A cellular communicating device (10). The device comprises means (22.sub.1) for communicating bi-directional data to and from a cellular transceiver station...
Methods, apparatus, and systems for securing SIM (subscriber identity
module) personalization and other data on...
An electronic circuit 120 includes a more-secure processor (600) having hardware based security (138) for storing data. A less-secure processor (200) eventually...
Laser diode driver architectures
Laser diode driver architectures are disclosed. Some example current drivers are described, including a current channel to provide an output current. The...
Bit cell designs for ternary content addressable memory
A scheme for bit cell designs for ternary content addressable memory for comparing search data with content data is disclosed. In one embodiment, a system for...
Low power load switch with protection circuitry
Load switches are relatively common and in use with a variety of applications, and conventional load switches have been designed to have continually operating...
Dying gasp charge controller
In many applications, "dying gasp" periods following power down are used. Conventional circuits supply energy for the "dying gasp" periods generally by use of...
Local interconnect network transceiver driver
Various driver circuit apparatuses and methods for driving an electrical signal are disclosed herein. For example, some embodiments provide a driver circuit...
BIST DDR memory interface circuit and method for testing the same
An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a...
Driver for light emitting semiconductor device
An electronic device is provided comprising a driver for light emitting semiconductor devices. The driver includes a first MOS transistor (MN1) coupled with a...
Stable gold bump solder connections
A metallic interconnect structure (200) for connecting a gold bump (205) and a copper pad (212), as used for example in semiconductor flip-chip assembly. A...
Area efficient 3D integration of low noise JFET and MOS in linear bipolar
Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important...
Systems and methods that selectively modify liner induced stress
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a...
Method to manufacture silicon quantum islands and single-electron devices
A method of manufacturing a single-electron transistor device is provided. The method includes forming a thinned region in a silicon substrate, the thinned...
Method of adjusting FDSOI threshold voltage through oxide charges
generation in the buried oxide
Different performance MOSFET Fully Depleted devices can be achieved on a single chip by varying the Vt through ion implantation. The integration of multiple Vt...
Palladium-spot leadframes for high adhesion semiconductor devices and
method of fabrication
A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal;...
TAP with enable input gated and multiplexed mode select
A TAP Linking Module (TLM) couples plural TAPs, via select and enable signals, to an externally accessible IEEE 1149.1 interface. The select signals are outputs...
Selectively accessing test access ports in a multiple test access port
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
System and method for transporting video data through a dual-link HD-SDI
In accordance with the teachings the present invention, a system and method for transporting video data through a dual-link HD-SDI connection is provided. In a...
Delayed combining of frequency-domain equalized wireless channels with
Methods and apparatus to perform frequency-domain equalization in high-speed downlink packet access (HSDPA) receivers for wireless channels with large...
Reduced power bitline precharge scheme for low power applications in
A method and system are described for a two step precharging of bitlines in a memory array. In the first step a partial precharge of the bitline is accomplished...
Universal structure for memory cell characterization
An integrated circuit includes a structure, where the structure includes a memory base cell, a first port set, a second port set, and a set of other ports,...
Adaptive voltage control for SRAM
The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM...
System and method for displaying images
System and method for projection display with slim cabinet depth. An embodiment comprises a collimating layer positioned in a light path of a display plane, and...
Local oscillator incorporating phase command exception handling utilizing
a quadrature switch
A novel and useful apparatus for and method of local oscillator generation employing an exception handling mechanism that permits an oscillator having a limited...
Computation spreading for spur reduction in a digital phase lock loop
A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based...
IC output signal path with switch, bus holder, and buffer
An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal. The signal path...
Micro-optical device packaging system
According to one embodiment, a micro-optical device includes an electro-optical circuit and an annular frame disposed on a surface of a substrate. The...
Method of forming PZT ferroelectric capacitors for integrated circuits
One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a...
Self-clearing asynchronous interrupt edge detect latching register
A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a...
Interrupt-related circuits, systems, and processes
An electronic interrupt circuit includes an interrupt-related input line, a security-related status input line, a context-related status input line, and a...
Digital video contrast enhancement and skin tone correction by conversion to CIECAM02 color space with lightness transformation and a skin tone probability...
Multipath equalization for MIMO multiuser systems
Interference rejection (85) can be applied to a wireless communication signal with reduced computational complexity by producing from a sample vector (y) a...
F-RAM device with current mirror sense amp
A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage...
Parallel CABAC decoding for video decompression
A method of video decoding is provided that includes receiving a data stream comprising a sequence of syntax elements that were compressed using...
A D-class amplifier that can suppress noise generated when a D-class amplification operation is started/stopped. When a D-class amplification operation is...
Master slave delay locked loops and uses thereof
Various systems and methods for delaying a signal relative to another signal are disclosed. As one example, a delay lock loop circuit is disclosed that includes...
Pop noise suppression technique
A voltage supply circuit and a circuit device can reduce the noise in the output of the circuit when the power to the circuit is turned on and off and can...
System and method for switch mode power supply delay compensation
A delay applied to a turn-on time for a high side switch in a switch mode power converter prevents oscillation between continuous and discontinuous conduction...
Methodology of improving the manufacturability of laser anneal
A method of laser annealing a workpiece for reduction of warpage, slip defects and breakage, the method comprising (a) moving a workpiece through a laser beam...
Method and system for accessing indirect memories
Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that...
System and method for making photomasks
The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn...
Method and apparatus for reducing memory current leakage a mobile device
A processing system includes a processor (20) having an idle mode node for generating an idle mode signal indicating whether the processor is in an idle mode...
Power-optimizing memory analyzer, method of operating the analyzer and
system employing the same
Embodiments of the present disclosure provide a power-optimizing memory analyzer, a method of operating a power-optimizing memory analyzer and a memory system...
Tire rotation detection system and method
A method for determining whether a tire is in rotation is provided. A measured acceleration is compared to a first threshold after a first timer indicates that...
Method and system for reducing device test time
A system and method for reducing device test time are disclosed herein. A method for reducing device test time includes applying a linear program solver to...
Method and apparatus for synchronizing time stamps
Traditionally, time stamp circuits have been used for precise digital time measurements. The resolution of these types of circuits, though, was generally...
Apparatus for and method of Bluetooth and WiMAX coexistence in a mobile
A novel and useful apparatus for and method of Bluetooth and WiMAX coexistence. The invention provides a system approach to achieving coexistence between...