Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: texas instruments





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,949,917 Maintaining data coherency in multi-clock systems
A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a...
US-7,949,323 Local oscillator leakage counterbalancing in a receiver
The present invention provides a local oscillator (LO) leakage controller for use with a receiver. In one embodiment, the LO leakage controller includes a...
US-7,949,064 Codebook and pre-coder selection for closed-loop mimo
A method of transmitting a communication signal (FIG. 1) is disclosed. The method includes receiving a data signal (102). The method further includes receiving...
US-7,948,866 Low complexity design of primary synchronization sequence for OFDMA
The present disclosure provides a base station transmitter, a user equipment receiver and methods of operating a base station transmitter and a user equipment...
US-7,948,499 Color control algorithm for use in display systems
A color control algorithm compensates variations in the display system so as to maintain color consistency in the projected images on the screen by constructing...
US-7,948,410 Multibit recyclic pipelined ADC architecture
An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit...
US-7,948,319 Current-mirroring systems and methods
One embodiment of the invention includes a current-mirror system. The system includes a current-mirror circuit configured to conduct an input current through a...
US-7,948,316 Low bias current amplifier
An amplifier is provided that includes an output portion that sources and sinks current associated with an output load and an amplification portion that is...
US-7,948,199 Single-ended gain stage and disk drive
An electrical apparatus comprising an amplifier having a first input, a second input, and an output. The apparatus further comprises a first electrical path...
US-7,947,602 Conductive pattern formation method
The objective of the present invention is to offer a method for forming a conductive pattern on a substrate and solder protrusions on the conductive pattern....
US-7,945,875 Methodology for hierarchy separation at asynchronous clock domain boundaries for multi-voltage optimization...
This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and...
US-7,945,838 Parity check decoder architecture
A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder...
US-7,945,832 Interface to full and reduced pin JTAG devices
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced...
US-7,945,831 Gating TDO from plural JTAG circuits
Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan...
US-7,945,008 Systems and methods for lattice enumeration-aided detection
Embodiments provide systems and methods for improved multiple-input, multiple-output (MIMO) detection comprising generating at least one list of candidate...
US-7,944,904 Systems and methods for managing timing functions in multiple timing protocols
One embodiment of the present invention includes a system for managing timing functions associating with at least one timing protocol. The system comprises a...
US-7,944,819 System and method for transmission and acknowledgment of blocks of data frames in distributed wireless networks
The present application describes a system and method for transmitting and acknowledging a block of frames in a wireless network. According to an embodiment, a...
US-7,944,503 Interlaced-to-progressive video processing
An edge direction vector determination, which can be used for video interlaced-to-progressive conversion by motion-adaptive interpolation, has a coarse edge...
US-7,944,379 SAR ADC and method with INL compensation
An apparatus for analog-to-digital conversion using successive approximation is provided. There is a successive approximation register or SAR controller for...
US-7,944,348 Tire monitoring device and tire problem detecting device
A device to accurately identify the wheel position where each tire has a radio wave transmitter installed without special means or operation during application...
US-7,944,319 Clock spreading systems and methods
Clock spreading systems and methods are disclosed. In one embodiment of the invention, a clock spreading system is provided in an integrated transceiver system...
US-7,944,287 Low-noise, wide offset range, programmable input offset amplifier front end and method
A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first...
US-7,944,252 High performance LVDS driver for scalable supply
Traditionally, complementary metal oxide semiconductor (CMOS) and bipolar transistors have been separately employed in low voltage differential signal (LVDS)...
US-7,944,034 Array molded package-on-package having redistribution lines
A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to...
US-7,943,514 Integrated circuits having TSVs including metal gettering dielectric liners
An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit...
US-7,943,499 FUSI integration method using SOG as a sacrificial planarization layer
A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from...
US-7,943,489 Bonded wafer assembly system and method
A system and method for the removal of superfluous material in a bonded wafer assembly. The method includes cutting a plurality of parallel cuts in a top wafer,...
US-7,943,479 Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT)...
A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a...
US-7,943,472 CoSi2 Schottky diode integration in BiSMOS process
Cobalt silicide (CoSi2) Schottky diodes fabricated per the current art suffer from excess leakage currents in reverse bias. In this invention, an floating...
US-7,943,456 Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom
A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes providing a substrate having a semiconductor surface including PMOS regions...
US-7,943,451 Integration scheme for reducing border region morphology in hybrid orientation technology (HOT) using direct...
Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary...
US-7,943,450 Gated resonant tunneling diode
A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably...
US-7,943,425 Semiconductor wafer sawing system and method
Semiconductor wafer sawing systems and methods are described in which a wafer may be secured in a sawing position having a surface exposed to incur sawing with...
US-7,941,790 Data processing apparatus, system and method
A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a...
US-7,941,774 Partial timing modeling for gate level simulation
Various apparatuses, methods and systems for creating an integrated circuit and performing a gate level simulation of a circuit are disclosed herein. For...
US-7,941,722 Testing of integrated circuits using test module
A method and apparatus for testing of integrated circuits using a Direct Memory Load Execute Dump (DMLED) test module. The method includes loading a test case...
US-7,941,711 Determining bit error rate using single data burst
A communication system includes a transceiver capable of receiving a data burst as part of a paging block and a processing logic capable of comparing at least...
US-7,941,164 Satellite positioning system receiver utilizing broadcast doppler information
A cellular communicating device (10). The device comprises means (22.sub.1) for communicating bi-directional data to and from a cellular transceiver station...
US-7,940,932 Methods, apparatus, and systems for securing SIM (subscriber identity module) personalization and other data on...
An electronic circuit 120 includes a more-secure processor (600) having hardware based security (138) for storing data. A less-secure processor (200) eventually...
US-7,940,824 Laser diode driver architectures
Laser diode driver architectures are disclosed. Some example current drivers are described, including a current channel to provide an output current. The...
US-7,940,541 Bit cell designs for ternary content addressable memory
A scheme for bit cell designs for ternary content addressable memory for comparing search data with content data is disclosed. In one embodiment, a system for...
US-7,940,505 Low power load switch with protection circuitry
Load switches are relatively common and in use with a variety of applications, and conventional load switches have been designed to have continually operating...
US-7,940,118 Dying gasp charge controller
In many applications, "dying gasp" periods following power down are used. Conventional circuits supply energy for the "dying gasp" periods generally by use of...
US-7,940,076 Local interconnect network transceiver driver
Various driver circuit apparatuses and methods for driving an electrical signal are disclosed herein. For example, some embodiments provide a driver circuit...
US-7,940,066 BIST DDR memory interface circuit and method for testing the same
An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a...
US-7,940,037 Driver for light emitting semiconductor device
An electronic device is provided comprising a driver for light emitting semiconductor devices. The driver includes a first MOS transistor (MN1) coupled with a...
US-7,939,939 Stable gold bump solder connections
A metallic interconnect structure (200) for connecting a gold bump (205) and a copper pad (212), as used for example in semiconductor flip-chip assembly. A...
US-7,939,863 Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process
Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important...
US-7,939,400 Systems and methods that selectively modify liner induced stress
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a...
US-7,939,398 Method to manufacture silicon quantum islands and single-electron devices
A method of manufacturing a single-electron transistor device is provided. The method includes forming a thinned region in a silicon substrate, the thinned...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.