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Method and system for reducing device test time
A system and method for reducing device test time are disclosed herein. A method for reducing device test time includes applying a linear program solver to...
Method and apparatus for synchronizing time stamps
Traditionally, time stamp circuits have been used for precise digital time measurements. The resolution of these types of circuits, though, was generally...
Apparatus for and method of Bluetooth and WiMAX coexistence in a mobile
A novel and useful apparatus for and method of Bluetooth and WiMAX coexistence. The invention provides a system approach to achieving coexistence between...
Method and apparatus for digital amplitude and phase modulation
A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a...
Multiple space time transmit diversity communication system with selected
complex conjugate inputs
A transmitter comprising circuitry (14) for converting input bits to a plurality of symbols; and circuitry (24.sub.x) for forming a complex conjugate of signals...
Variable power communications including rapid switching between coding
constellations of various sizes
A method of varying the power output of a transmitter. The method includes providing bit-loading information associated with each tone of multiple tones, where...
System and method for optical frequency conversion
A system and method for optical frequency conversion having asymmetric output include a coherent light apparatus. The coherent light apparatus includes a...
Method, system and apparatus for providing signal based packet loss
concealment for memoryless codecs
In a method, apparatus and system for transmitting packet loss concealment (PLC) information, a subscriber device divides a voice sample into a plurality of...
Receiving a pilot design and channel estimation
A receiver in an OFDM based communication system is adapted to perform channel estimation using a received reference signal transmitted from at least one...
Pulse width modulation algorithm
In display systems employing spatial light modulators, the OFF-state light from OFF-state pixels of the spatial light modulator can be captured and directed...
Method and apparatus to improve and control the propagation delay in a
current slewing circuit
A circuit for independently controlling slew and propagation delay of a current DAC is provided. The circuit applies dual slope technique with feed-back control...
Semi-buffered auto-direction-sensing voltage translator
In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage...
Load-induced voltage overshoot detection and correction in switching power
One embodiment of the invention includes a switching power supply system. The system includes a switch network comprising at least one switch configured to...
Linear voltage regulator with accurate open load detection
A linear voltage regulator is provided which has a pair of complementary power transistors connected "back to back" in series between a voltage input and a...
Method and apparatus for power management of a low dropout regulator
A method of switching a low dropout regulator includes determining an actual active time of a power request from an electronic device; enabling the low dropout...
On-chip current sensing
One embodiment of the invention includes an on-chip current-sense system for measuring a magnitude of an output current through a power transistor. The system...
Semiconductor package having buss-less substrate
A ball grid array device with an insulating substrate (110) having metal traces (106, for example copper, about 18 .mu.m thick) with sidewalls (108) at right...
Flexible interposer for stacking semiconductor chips and connecting same
A semiconductor device with a first (101) and a second (111) semiconductor chip assembled on an insulating flexible interposer (120). The interposer, preferably...
Semiconductor chip package assembly with deflection- resistant leadfingers
The invention relates to leadframes and semiconductor chip package assemblies using leadframes, and to methods for their assembly. A disclosed embodiment of the...
Package-level electromagnetic interference shielding
A shielded electronic package, comprising a semiconductor device, an insulating housing surrounding the semiconductor device and a metal coating on the...
A semiconductor device that attenuates light to the circuit element area is provided. The semiconductor device includes light-sensitive element area formed on...
Cross-contamination control for semiconductor process flows having metal
comprising gate electrodes
A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel...
Method of reducing channeling of ion implants using a sacrificial
Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and...
Simplified double mask patterning system
One embodiment of the present invention relates to a method for which a two mask lithography process can be used to reduce design density. The two mask process...
Spot heat wirebonding
Methods and systems are disclosed for forming secure wirebonds between electrical contacts in electronic device assemblies. Representative embodiments of the...
Scan circuitry controlled switch connecting buffer output to test lead
The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
DDR gate and delay clock circuitry for parallel interface registers
A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The...
Generator/compactor scan circuit low power adapter
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
Multiplexer connecting TDI or AX1/TDI to data and instruction registers
The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG...
Augmentation instruction shift register with serial and two parallel
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
Hardware key encryption for data scrambling
Apparatus and method to scramble data prior to placing it on a bus or in memory uses embedded hardware keys for encryption/decryption. The hardware keys may be...
Method, system and apparatus for providing a boot loader of an embedded
A method, system and apparatus for executing a boot loader for an embedded system including a system-on-chip (SOC) processor coupled to a memory including first...
Reporting a saturated counter value
A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number....
Memory optimization packet loss concealment in a voice over packet network
A method to reduce memory requirements for a packet loss concealment algorithm in the event of packet loss in a receiver of pulse code modulated voice signals....
Method for memory cell characterization using universal structure
A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first...
Hidden micromirror support structure
Methods and apparatus for use with a micromirror element includes a micromirror a micromirror having a substantially flat outer surface disposed outwardly from...
Use of three phase clock in sigma delta modulator to mitigate the
quantization noise folding
A differential sigma delta modulator operates by modulating an input signal by intermittently coupling a reference signal to the input signal using one or more...
Integrated poly-phase fir filter in double-sampled analog to digital
A sigma delta analog to digital converter includes a clock operating at a conversion clock rate and first and second conversion paths. The first path includes a...
Key based pin sharing selection
This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention plural operational units each having a...
Fault protection circuit, method of operating a fault protection circuit
and a voltage regulator employing the same
Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one...
Nanotip repair and characterization using field ion microscopy
A system (100) for characterizing surfaces can include a nanotip microscope (104) in a first pressure envelope (102) at a first pressure with an electrically...
Low computation mono to stereo conversion using intra-aural differences
A method of converting single channel audio (mono) signals to two channel audio (stereo) signals using simple filters and an Intra-aural Time Difference (ITD)...
Idle connection state power consumption reduction in a wireless local area
network using beacon delay advertisement
A novel and useful apparatus for and method of improving idle connection state power consumption in wireless local area network (WLAN) system. Beacon...
Ferroelectric memory devices with partitioned platelines
One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in...
Method for maintaining the phase difference of a positioning mirror as a
constant with respect to a high speed...
System and method for synchronizing the low speed mirror movement of a mirror display system with incoming frame or video signals, and synchronizing buffered...
Digital phase locked loop with dithering
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked...
System and method for auto-power gating synthesis for active leakage
A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power...
Methods and apparatus to sense a PTAT reference in a fully isolated
NPN-based bandgap reference
In a traditional, fully-isolated bandgap reference circuits, it was difficult to detect currents that are proportional to absolute temperature (PTAT). Here, a...
Power up biasing in a system having multiple input biasing modes
This invention is an input bias control for a module input. A clock detect circuit generates a signal indicating whether an external clock signal is detected....
Methods and apparatus for controlling a digital power supply
Methods and apparatus for controlling a digital power supply are disclosed. An example method includes storing a first set of coefficients for controlling a...