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Area-efficient electrically erasable programmable memory cell
Electrically erasable programmable "read-only" memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell...
System and method for utilizing a scanning beam to display an image
A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first...
Method of fabricating a semiconductor device
In a method and apparatus for fabricating a semiconductor device having a flexible tape substrate, a hole is punched in the flexible tape substrate. The...
Scan path adaptor with state machine, counter, and gate circuitry
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan...
Serial I/O using JTAG TCK and TMS signals
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus....
Transferring control between programs of different security levels
Systems and methods for transferring control between programs of different security levels are described herein. Some embodiments include a processor capable of...
Loop bandwidth enhancement technique for a digital PLL and a HF divider
that enables this technique
A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first...
A modulation circuit uses pre-calculated and stored data to generate the modulated output. The modulator architecture uses pre-calculated, Gaussian filtered sine...
RF processor having internal calibration mode
The present invention pertains to a method of calibrating reception properties of a radio frequency (RF) processor. The application describes two embodiments of...
Method and circuitry for self testing of connectivity of touch screen
A touch screen digitizing system includes a first resistive screen and a touch screen controller including an ADC and self-test circuitry having a driver switch...
Increased intensity resolution for pulse-width modulation-based displays
with light emitting diode illumination
A method for increasing intensity resolution (bit-depth) using LED illumination. A preferred embodiment comprises determining a display time for a bit to be...
Digital-to-analog converter (DAC) with reference-rotated DAC elements
In accordance with at least some embodiments, an electronic device comprises a digital-to-analog converter (DAC) having a DAC element array. Reference-rotated...
Time-interleaved-dual channel ADC with mismatch compensation
Previously, when designing receivers for radio frequency (RF) or wireless communications, designers chose between time-interleaved (TI) analog-to-digital...
Process and temperature insensitive flicker noise monitor circuit
In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit...
Start-up circuit and method for a self-biased zero-temperature-coefficient
A current reference circuit is disclosed. A small startup current is defined as the base current into a bipolar transistor with its collector-emitter path...
Method of arranging dies in a wafer for easy inkless partial wafer process
In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle...
Bonding IC die to TSV wafers
A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that...
Semiconductor wafer handler
A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor...
Multi-function light modulators for optical systems
In one embodiment, a method includes transmitting one or more light beams by a first portion of a light modulator formed outwardly from a substrate. The one or...
Interconnections for plural and hierarchical P1500 test wrappers
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing...
Hinge design for enhanced optical performance for a digital micro-mirror
An apparatus for use with a digital micro-mirror 100 includes a hinge 116 disposed outwardly from a substrate 102. The hinge 116 is capable of at least partially...
Dual integrator circuit for analog front end (AFE)
A circuit includes a generating circuit that generates a current signal in response to an input signal, a first one of a plurality of integrators that generates...
Driver with programmable power commensurate with data-rate
One embodiment of the invention includes a driver circuit. The driver circuit comprises an output transistor that is biased to provide an output signal in...
Regulator with automatic power output device detection
A switching regulator (20) including an on-chip power output function (24) and also an interface (26) to which off-chip power output devices (42PU, 42PD) may be...
N2 based plasma treatment for enhanced sidewall smoothing and pore sealing
of porous low-k dielectric films
A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k...
Gated resonant tunneling diode
A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably...
Etch residue reduction by ash methodology
Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a...
Bumpless wafer scale device and board assembly
A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact...
Reducing gate CD bias in CMOS processing
A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a...
Distributed high voltage JFET
A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially...
Use of dual mask processing of different composition such as
inorganic/organic to enable a single poly etch...
In accordance with the invention, there are methods of making an integrated circuit, an integrated circuit device, and a computer readable medium. A method can...
Boundary scan path method and system with functional and non-functional
scan cell memories
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a...
Scan testable register file
Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test...
Memory having circuitry controlling the voltage differential between the
word line and array supply voltage
An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also...
Circuit and method for a fully integrated switched-capacitor step-down
A circuit and method for providing a fully integrated DC-DC converter using on-chip switched capacitors is disclosed. A switched capacitor matrix is coupled as a...
Circuit for compensation of leakage current-induced offset in a
An electronic device includes an operational amplifier, with the operational amplifier having an amplifier input stage coupled with a first output node to an...
Self-protecting core system
The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for...
An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT...
Switched capacitor measurement circuit for measuring the capacitance of an
A switched capacitor measurement circuit is provided for measuring the capacitance of an input capacitor with a parallel parasitic resistor. The circuit...
System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
Polysilicon structures resistant to laser anneal lightpipe waveguide
Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of...
Implanted vertical source-line under straight stack for FLASH EPROM
In FLASH EPROM cells, source diffusion continuity between horizontal and vertical source lines is provided by an arsenic implant under the stack in vertical...
Method for metal gate quality characterization
Measuring the amount of unreacted polysilicon gate material in a fully silicided (FUSI) nickel silicide gate process for metal oxide semiconductor (MOS)...
System and method for making photomasks
The present disclosure is directed a method for preparing a system of photomask patterns for implementing a drawn pattern on a substrate with a multi-patterning...
System and method for making photomasks
The present disclosure is directed to a method for preparing photomask patterns for a lithography process that employs a plurality of photomasks. The method...
An RFID tag is provided, which has a transponder part with an antenna coil arranged in the transponder part. A mounting part is also provided for fixing the tag...
System and method for checking for sub-resolution assist features
In accordance with the invention, there is provided a system and method for checking a mask layout including sub-resolution assist features (SRAFs). A checking...
Wafer scale testing using a 2 signal JTAG interface
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
Method and system for selecting effective tap values for a digital filter
Systems and methods are provided for determining effective tap values for a digital filter. A first plurality of vectors is generated, wherein each of the first...
Multi-tap direct sub-sampling mixing system for wireless receivers
A multi-tap direct sub-sampling mixing system for wireless receivers is provided with a dynamically configurable passive switched capacitor filter. A front end...