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Patent # Description
US-7,932,843 Parallel CABAC decoding for video decompression
A method of video decoding is provided that includes receiving a data stream comprising a sequence of syntax elements that were compressed using...
US-7,932,779 D-class amplifier
A D-class amplifier that can suppress noise generated when a D-class amplification operation is started/stopped. When a D-class amplification operation is...
US-7,932,756 Master slave delay locked loops and uses thereof
Various systems and methods for delaying a signal relative to another signal are disclosed. As one example, a delay lock loop circuit is disclosed that includes...
US-7,932,711 Pop noise suppression technique
A voltage supply circuit and a circuit device can reduce the noise in the output of the circuit when the power to the circuit is turned on and off and can...
US-7,932,703 System and method for switch mode power supply delay compensation
A delay applied to a turn-on time for a high side switch in a switch mode power converter prevents oscillation between continuous and discontinuous conduction...
US-7,932,139 Methodology of improving the manufacturability of laser anneal
A method of laser annealing a workpiece for reduction of warpage, slip defects and breakage, the method comprising (a) moving a workpiece through a laser beam...
US-7,930,689 Method and system for accessing indirect memories
Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that...
US-7,930,656 System and method for making photomasks
The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn...
US-7,930,572 Method and apparatus for reducing memory current leakage a mobile device
A processing system includes a processor (20) having an idle mode node for generating an idle mode signal indicating whether the processor is in an idle mode...
US-7,930,565 Power-optimizing memory analyzer, method of operating the analyzer and system employing the same
Embodiments of the present disclosure provide a power-optimizing memory analyzer, a method of operating a power-optimizing memory analyzer and a memory system...
US-7,930,132 Tire rotation detection system and method
A method for determining whether a tire is in rotation is provided. A measured acceleration is compared to a first threshold after a first timer indicates that...
US-7,930,130 Method and system for reducing device test time
A system and method for reducing device test time are disclosed herein. A method for reducing device test time includes applying a linear program solver to...
US-7,930,121 Method and apparatus for synchronizing time stamps
Traditionally, time stamp circuits have been used for precise digital time measurements. The resolution of these types of circuits, though, was generally...
US-7,929,912 Apparatus for and method of Bluetooth and WiMAX coexistence in a mobile handset
A novel and useful apparatus for and method of Bluetooth and WiMAX coexistence. The invention provides a system approach to achieving coexistence between...
US-7,929,637 Method and apparatus for digital amplitude and phase modulation
A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a...
US-7,929,631 Multiple space time transmit diversity communication system with selected complex conjugate inputs
A transmitter comprising circuitry (14) for converting input bits to a plurality of symbols; and circuitry (24.sub.x) for forming a complex conjugate of signals...
US-7,929,626 Variable power communications including rapid switching between coding constellations of various sizes
A method of varying the power output of a transmitter. The method includes providing bit-loading information associated with each tone of multiple tones, where...
US-7,929,583 System and method for optical frequency conversion
A system and method for optical frequency conversion having asymmetric output include a coherent light apparatus. The coherent light apparatus includes a...
US-7,929,520 Method, system and apparatus for providing signal based packet loss concealment for memoryless codecs
In a method, apparatus and system for transmitting packet loss concealment (PLC) information, a subscriber device divides a voice sample into a plurality of...
US-7,929,416 Receiving a pilot design and channel estimation
A receiver in an OFDM based communication system is adapted to perform channel estimation using a received reference signal transmitted from at least one...
US-7,928,999 Pulse width modulation algorithm
In display systems employing spatial light modulators, the OFF-state light from OFF-state pixels of the spatial light modulator can be captured and directed...
US-7,928,784 Method and apparatus to improve and control the propagation delay in a current slewing circuit
A circuit for independently controlling slew and propagation delay of a current DAC is provided. The circuit applies dual slope technique with feed-back control...
US-7,928,766 Semi-buffered auto-direction-sensing voltage translator
In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage...
US-7,928,714 Load-induced voltage overshoot detection and correction in switching power supplies
One embodiment of the invention includes a switching power supply system. The system includes a switch network comprising at least one switch configured to...
US-7,928,711 Linear voltage regulator with accurate open load detection
A linear voltage regulator is provided which has a pair of complementary power transistors connected "back to back" in series between a voltage input and a...
US-7,928,707 Method and apparatus for power management of a low dropout regulator
A method of switching a low dropout regulator includes determining an actual active time of a power request from an electronic device; enabling the low dropout...
US-7,928,703 On-chip current sensing
One embodiment of the invention includes an on-chip current-sense system for measuring a magnitude of an output current through a power transistor. The system...
US-7,928,574 Semiconductor package having buss-less substrate
A ball grid array device with an insulating substrate (110) having metal traces (106, for example copper, about 18 .mu.m thick) with sidewalls (108) at right...
US-7,928,550 Flexible interposer for stacking semiconductor chips and connecting same to substrate
A semiconductor device with a first (101) and a second (111) semiconductor chip assembled on an insulating flexible interposer (120). The interposer, preferably...
US-7,928,544 Semiconductor chip package assembly with deflection- resistant leadfingers
The invention relates to leadframes and semiconductor chip package assemblies using leadframes, and to methods for their assembly. A disclosed embodiment of the...
US-7,928,538 Package-level electromagnetic interference shielding
A shielded electronic package, comprising a semiconductor device, an insulating housing surrounding the semiconductor device and a metal coating on the...
US-7,928,529 Semiconductor device
A semiconductor device that attenuates light to the circuit element area is provided. The semiconductor device includes light-sensitive element area formed on...
US-7,927,993 Cross-contamination control for semiconductor process flows having metal comprising gate electrodes
A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel...
US-7,927,987 Method of reducing channeling of ion implants using a sacrificial scattering layer
Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and...
US-7,927,782 Simplified double mask patterning system
One embodiment of the present invention relates to a method for which a two mask lithography process can be used to reduce design density. The two mask process...
US-7,926,698 Spot heat wirebonding
Methods and systems are disclosed for forming secure wirebonds between electrical contacts in electronic device assemblies. Representative embodiments of the...
US-7,925,951 Scan circuitry controlled switch connecting buffer output to test lead
The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
US-7,925,946 DDR gate and delay clock circuitry for parallel interface registers
A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The...
US-7,925,945 Generator/compactor scan circuit low power adapter
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-7,925,943 Multiplexer connecting TDI or AX1/TDI to data and instruction registers
The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG...
US-7,925,942 Augmentation instruction shift register with serial and two parallel inputs
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
US-7,925,896 Hardware key encryption for data scrambling
Apparatus and method to scramble data prior to placing it on a bus or in memory uses embedded hardware keys for encryption/decryption. The hardware keys may be...
US-7,925,877 Method, system and apparatus for providing a boot loader of an embedded system
A method, system and apparatus for executing a boot loader for an embedded system including a system-on-chip (SOC) processor coupled to a memory including first...
US-7,925,687 Reporting a saturated counter value
A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number....
US-7,924,704 Memory optimization packet loss concealment in a voice over packet network
A method to reduce memory requirements for a packet loss concealment algorithm in the event of packet loss in a receiver of pulse code modulated voice signals....
US-7,924,640 Method for memory cell characterization using universal structure
A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first...
US-7,924,489 Hidden micromirror support structure
Methods and apparatus for use with a micromirror element includes a micromirror a micromirror having a substantially flat outer surface disposed outwardly from...
US-7,924,194 Use of three phase clock in sigma delta modulator to mitigate the quantization noise folding
A differential sigma delta modulator operates by modulating an input signal by intermittently coupling a reference signal to the input signal using one or more...
US-7,924,191 Integrated poly-phase fir filter in double-sampled analog to digital converters
A sigma delta analog to digital converter includes a clock operating at a conversion clock rate and first and second conversion paths. The first path includes a...
US-7,924,050 Key based pin sharing selection
This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention plural operational units each having a...
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