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Patent # Description
US-7,927,993 Cross-contamination control for semiconductor process flows having metal comprising gate electrodes
A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel...
US-7,927,987 Method of reducing channeling of ion implants using a sacrificial scattering layer
Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and...
US-7,927,782 Simplified double mask patterning system
One embodiment of the present invention relates to a method for which a two mask lithography process can be used to reduce design density. The two mask process...
US-7,926,698 Spot heat wirebonding
Methods and systems are disclosed for forming secure wirebonds between electrical contacts in electronic device assemblies. Representative embodiments of the...
US-7,925,951 Scan circuitry controlled switch connecting buffer output to test lead
The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
US-7,925,946 DDR gate and delay clock circuitry for parallel interface registers
A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The...
US-7,925,945 Generator/compactor scan circuit low power adapter
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-7,925,943 Multiplexer connecting TDI or AX1/TDI to data and instruction registers
The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG...
US-7,925,942 Augmentation instruction shift register with serial and two parallel inputs
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
US-7,925,896 Hardware key encryption for data scrambling
Apparatus and method to scramble data prior to placing it on a bus or in memory uses embedded hardware keys for encryption/decryption. The hardware keys may be...
US-7,925,877 Method, system and apparatus for providing a boot loader of an embedded system
A method, system and apparatus for executing a boot loader for an embedded system including a system-on-chip (SOC) processor coupled to a memory including first...
US-7,925,687 Reporting a saturated counter value
A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number....
US-7,924,704 Memory optimization packet loss concealment in a voice over packet network
A method to reduce memory requirements for a packet loss concealment algorithm in the event of packet loss in a receiver of pulse code modulated voice signals....
US-7,924,640 Method for memory cell characterization using universal structure
A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first...
US-7,924,489 Hidden micromirror support structure
Methods and apparatus for use with a micromirror element includes a micromirror a micromirror having a substantially flat outer surface disposed outwardly from...
US-7,924,194 Use of three phase clock in sigma delta modulator to mitigate the quantization noise folding
A differential sigma delta modulator operates by modulating an input signal by intermittently coupling a reference signal to the input signal using one or more...
US-7,924,191 Integrated poly-phase fir filter in double-sampled analog to digital converters
A sigma delta analog to digital converter includes a clock operating at a conversion clock rate and first and second conversion paths. The first path includes a...
US-7,924,050 Key based pin sharing selection
This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention plural operational units each having a...
US-7,923,976 Fault protection circuit, method of operating a fault protection circuit and a voltage regulator employing the same
Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one...
US-7,921,465 Nanotip repair and characterization using field ion microscopy
A system (100) for characterizing surfaces can include a nanotip microscope (104) in a first pressure envelope (102) at a first pressure with an electrically...
US-7,920,708 Low computation mono to stereo conversion using intra-aural differences
A method of converting single channel audio (mono) signals to two channel audio (stereo) signals using simple filters and an Intra-aural Time Difference (ITD)...
US-7,920,535 Idle connection state power consumption reduction in a wireless local area network using beacon delay advertisement
A novel and useful apparatus for and method of improving idle connection state power consumption in wireless local area network (WLAN) system. Beacon...
US-7,920,404 Ferroelectric memory devices with partitioned platelines
One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in...
US-7,920,213 Method for maintaining the phase difference of a positioning mirror as a constant with respect to a high speed...
System and method for synchronizing the low speed mirror movement of a mirror display system with incoming frame or video signals, and synchronizing buffered...
US-7,920,081 Digital phase locked loop with dithering
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked...
US-7,920,020 System and method for auto-power gating synthesis for active leakage reduction
A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power...
US-7,920,015 Methods and apparatus to sense a PTAT reference in a fully isolated NPN-based bandgap reference
In a traditional, fully-isolated bandgap reference circuits, it was difficult to detect currents that are proportional to absolute temperature (PTAT). Here, a...
US-7,919,986 Power up biasing in a system having multiple input biasing modes
This invention is an input bias control for a module input. A clock detect circuit generates a signal indicating whether an external clock signal is detected....
US-7,919,958 Methods and apparatus for controlling a digital power supply
Methods and apparatus for controlling a digital power supply are disclosed. An example method includes storing a first set of coefficients for controlling a...
US-7,919,860 Semiconductor device having wafer level chip scale packaging substrate decoupling
One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the...
US-7,919,842 Structure and method for sealing cavity of micro-electro-mechanical device
A cavity package (100) for micrometer-scale MEMS devices surrounding the cavity (210) with the MEMS device (220) with a rim (232) of solder-wettable metal, and...
US-7,919,775 Semiconductor device and method comprising a high voltage reset driver and an isolated memory array
A method of operating a semiconductor device, a semiconductor device and a digital micromirror system are presented. In an embodiment, the semiconductor device...
US-7,919,368 Area-efficient electrically erasable programmable memory cell
Electrically erasable programmable "read-only" memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell...
US-7,918,563 System and method for utilizing a scanning beam to display an image
A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first...
US-7,918,018 Method of fabricating a semiconductor device
In a method and apparatus for fabricating a semiconductor device having a flexible tape substrate, a hole is punched in the flexible tape substrate. The...
US-7,917,824 Scan path adaptor with state machine, counter, and gate circuitry
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan...
US-7,917,822 Serial I/O using JTAG TCK and TMS signals
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus....
US-7,917,753 Transferring control between programs of different security levels
Systems and methods for transferring control between programs of different security levels are described herein. Some embodiments include a processor capable of...
US-7,916,824 Loop bandwidth enhancement technique for a digital PLL and a HF divider that enables this technique
A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first...
US-7,916,808 8PSK modulator
A modulation circuit uses pre-calculated and stored data to generate the modulated output. The modulator architecture uses pre-calculated, Gaussian filtered sine...
US-7,916,672 RF processor having internal calibration mode
The present invention pertains to a method of calibrating reception properties of a radio frequency (RF) processor. The application describes two embodiments of...
US-7,916,127 Method and circuitry for self testing of connectivity of touch screen panel
A touch screen digitizing system includes a first resistive screen and a touch screen controller including an ADC and self-test circuitry having a driver switch...
US-7,916,104 Increased intensity resolution for pulse-width modulation-based displays with light emitting diode illumination
A method for increasing intensity resolution (bit-depth) using LED illumination. A preferred embodiment comprises determining a display time for a bit to be...
US-7,916,058 Digital-to-analog converter (DAC) with reference-rotated DAC elements
In accordance with at least some embodiments, an electronic device comprises a digital-to-analog converter (DAC) having a DAC element array. Reference-rotated...
US-7,916,050 Time-interleaved-dual channel ADC with mismatch compensation
Previously, when designing receivers for radio frequency (RF) or wireless communications, designers chose between time-interleaved (TI) analog-to-digital...
US-7,915,905 Process and temperature insensitive flicker noise monitor circuit
In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit...
US-7,915,882 Start-up circuit and method for a self-biased zero-temperature-coefficient current reference
A current reference circuit is disclosed. A small startup current is defined as the base current into a bipolar transistor with its collector-emitter path...
US-7,915,087 Method of arranging dies in a wafer for easy inkless partial wafer process
In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle...
US-7,915,080 Bonding IC die to TSV wafers
A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that...
US-7,914,694 Semiconductor wafer handler
A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor...
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