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Patent # Description
US-8,004,248 Systems and methods for multi-mode battery charging
Various systems and methods for battery charging are disclosed herein. As just one example, a battery charger is disclosed that includes a current feedback loop...
US-8,004,051 Lateral trench MOSFET having a field plate
One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes...
US-8,002,611 Chemical mechanical polishing pad having improved groove pattern
A chemical mechanical polishing pad and method for chemical-mechanical polishing is provided, wherein the polishing pad has a plurality of first mesas and one...
US-8,001,436 Changing scan paths shifting by changing mode select input state
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...
US-8,001,435 Register selection circuitry receiving select signals from test interfaces
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-8,001,427 Method and system of indexing into trace data based on entries in a log buffer
A method and system of indexing into trace data based on entries in a log buffer. At least some of the illustrative embodiments are methods comprising executing...
US-8,000,921 Method and apparatus for synchronizing signals in a testing system
The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal...
US-8,000,670 Removing close-in interferers through a feedback loop
System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer...
US-8,000,428 All-digital frequency synthesis with DCO gain calculation
An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word...
US-8,000,425 Methods and apparatus to provide clock resynchronization in communication networks
Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein...
US-8,000,200 HFM enable control system
A modulation control system for use with a high frequency modulator is described. This system comprises a latch for selectively receiving enable signals,...
US-7,999,833 Deinterleaving transpose circuits in digital display systems
The present invention provides a method and apparatus of converting a stream of pixel data in space and time into a stream of bitplane data. In particular, the...
US-7,999,793 Median and mean coherent filter and method for eliminating noise in touch screen controller
A touch screen system includes a touch screen assembly (30,31) and a touch screen controller (1A) coupled to terminals (24,25,26,27) of the touch screen...
US-7,999,710 Multistage chopper stabilized delta-sigma ADC with reduced offset
A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential...
US-7,999,615 Current canceling variable gain amplifier and transmitter using same
A current canceling CMOS variable gain amplifier includes a first leg and a second leg. The first leg has a first input line, a first output line, a first ON...
US-7,999,596 Digital suppression of spikes on an 1.sup.2C bus
An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I.sup.2C) bus is provided. The apparatus comprises a serial data (SDA) filter,...
US-7,999,558 Systems and methods of overvoltage and undervoltage detection
Systems and methods for overvoltage and undervoltage detection may be implemented with a fully differential circuit that includes a coarse comparator and a band...
US-7,999,524 Interleaved power factor correction pre-regulator phase management circuitry
Methods for power factor correction (PFC) and for reducing conduction losses and switching losses in a power converter as well as the power converter and phase...
US-7,999,521 DC-DC converter usable for dual voltage supply
A converter has a single inductor with a first terminal connectable to a first terminal of the supply input through a first power transistor and a second...
US-7,999,293 Photodiode semiconductor device and manufacturing method
The invention provides a semiconductor device manufactured with a plurality of photodiodes so that it does not short circuit, and includes an opening without...
US-7,998,865 Systems and methods for removing wafer edge residue and debris using a residue remover mechanism
A system (500) removes wafer edge residue from a target wafer (508). A wafer holding mechanism (502) holds and rotates the target wafer (508). A residue remover...
US-7,997,744 Electrically conductive protection layer and a microelectromechanical device using the same
A deformable hinge for use in microelectromechanical devices comprises a protection layer that is electrically conductive. The protection layer is on top of...
US-7,996,740 Adaptor With Clocks For Like Parts of Different Scan Paths
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan...
US-7,996,660 Software controlled CPU pipeline protection
A processor in a digital system executes instructions in an instruction execution pipeline. The processor detects a pipeline protection directive while...
US-7,995,640 Dynamic interpolation location
Apparatus and method for optimizing interpolation in the despreader data-path of a wireless telecommunications network employing Code Division Multiple Access...
US-7,995,316 Integrated ESD protection device
An integrated electrostatic discharge (ESD) device includes a first ESD structure coupled to a pad terminal of the integrated ESD device and a second ESD...
US-7,995,279 Color light combiner
For combining light from different light sources that are spatially apart, an optical system comprises a prism assembly that comprises a ...
US-7,995,264 System and method for actuation of spatial light modulators
A system comprises a spatial light modulator comprising a plurality of modulation elements, the spatial light modulator operable to receive an optical signal...
US-7,995,258 Angle diversity antispeckling in spot displays
Improvement of speckling noise is discussed in which a central light beam received at a double-sided mirror is divided into a plurality of sub-beams. An...
US-7,995,144 Optimized phase alignment in analog-to-digital conversion of video signals
A digital video system (2) is disclosed, in which an analog input video signal is sampled at an optimum sample phase (P.sub.nc), and converted to a digital...
US-7,994,819 Level-shifter circuit
One embodiment of the invention includes a level-shifter circuit. The circuit comprises a control stage that steers a current from one of a first control node...
US-7,994,600 Antireflective coating
Device and method for an antireflective coating to improve image quality in an image display system. A preferred embodiment comprises a first high refractive...
US-7,994,073 Low stress sacrificial cap layer
A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film. Alternatively, a low...
US-7,993,014 Prism for high contrast projection
Prism elements having TIR surfaces placed in close proximity to the active area of a SLM device to separate unwanted off-state and/or flat-state light from the...
US-7,992,065 Automatic scan format selection based on scan topology selection
A method for specifying a signaling protocol to be used by a controller in a group of controllers connected with shared signaling is provided in which the...
US-7,992,064 Selecting a scan topology
A controller that shares an interface with several other controllers connected in a scan topology in a target system may be selected by receiving a selection...
US-7,992,049 Monitoring of memory and external events
A system comprises a circuit configured to execute instructions and output event data corresponding to the execution of the instructions. The system also...
US-7,991,959 Visualizing contents and states of hierarchical storage systems
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
US-7,990,916 Cell specific sounding reference signal sub-frame configuration
A method of wireless communication including a plurality of fixed base stations and a plurality of mobile user equipment with each base station transmitting to...
US-7,990,672 Supervision circuit to detect very fast power supply drops
This invention is power supply protection for complex digital circuits employing an external high voltage supply and an internally generated low voltage core...
US-7,990,471 Interlaced-to-progressive video
Interlaced-to-progressive conversion with (1) 3-2 pulldown detection, (2) pre-filtering for field motion detection, (3) field motion detection with feedback,...
US-7,990,188 Clock buffer
An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT...
US-7,990,074 Adaptive algorithm for camera flash LED power control vs. battery impedance, state of discharge (SOD), aging,...
A method for driving a light-emitting semiconductor is provided. A supply voltage is converted into a secondary output voltage for supplying the light-emitting...
US-7,989,949 Heat extraction from packaged semiconductor chips, scalable with chip area
A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more...
US-7,989,853 Integration of high voltage JFET in linear bipolar CMOS process
A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first,...
US-7,989,232 Method of using electrical test structure for semiconductor trench depth monitor
Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch...
US-7,987,436 Sub-resolution assist feature to improve symmetry for contact hole lithography
A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a...
US-7,987,393 Determining operating context of an executed instruction
Determining operating context of an executed instruction. At least some of the illustrative embodiments are a computer-readable medium storing a debug-trace...
US-7,987,014 Systems and methods for selecting wafer processing order for cyclical two pattern defect detection
A method of sequencing wafer processing order to minimize sequence correlation in a cyclical two pattern model by generating a set of sequences of wafer...
US-7,986,566 SRAM cell with read buffer controlled for low leakage current
A functional memory of the integrated circuit includes row and column periphery units and an array of memory cells having a core storage element and a read...
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