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Patent # Description
US-7,915,080 Bonding IC die to TSV wafers
A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that...
US-7,914,694 Semiconductor wafer handler
A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor...
US-7,914,151 Multi-function light modulators for optical systems
In one embodiment, a method includes transmitting one or more light beams by a first portion of a light modulator formed outwardly from a substrate. The one or...
US-7,913,135 Interconnections for plural and hierarchical P1500 test wrappers
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing...
US-7,911,679 Hinge design for enhanced optical performance for a digital micro-mirror device
An apparatus for use with a digital micro-mirror 100 includes a hinge 116 disposed outwardly from a substrate 102. The hinge 116 is capable of at least partially...
US-7,911,256 Dual integrator circuit for analog front end (AFE)
A circuit includes a generating circuit that generates a current signal in response to an input signal, a first one of a plurality of integrators that generates...
US-7,911,243 Driver with programmable power commensurate with data-rate
One embodiment of the invention includes a driver circuit. The driver circuit comprises an output transistor that is biased to provide an output signal in...
US-7,911,190 Regulator with automatic power output device detection
A switching regulator (20) including an on-chip power output function (24) and also an interface (26) to which off-chip power output devices (42PU, 42PD) may be...
US-7,910,936 N2 based plasma treatment for enhanced sidewall smoothing and pore sealing of porous low-k dielectric films
A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k...
US-7,910,918 Gated resonant tunneling diode
A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably...
US-7,910,477 Etch residue reduction by ash methodology
Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a...
US-7,910,471 Bumpless wafer scale device and board assembly
A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact...
US-7,910,422 Reducing gate CD bias in CMOS processing
A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a...
US-7,910,417 Distributed high voltage JFET
A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially...
US-7,910,289 Use of dual mask processing of different composition such as inorganic/organic to enable a single poly etch...
In accordance with the invention, there are methods of making an integrated circuit, an integrated circuit device, and a computer readable medium. A method can...
US-7,908,537 Boundary scan path method and system with functional and non-functional scan cell memories
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a...
US-7,908,535 Scan testable register file
Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test...
US-7,907,456 Memory having circuitry controlling the voltage differential between the word line and array supply voltage
An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also...
US-7,907,429 Circuit and method for a fully integrated switched-capacitor step-down power converter
A circuit and method for providing a fully integrated DC-DC converter using on-chip switched capacitors is disclosed. A switched capacitor matrix is coupled as a...
US-7,907,015 Circuit for compensation of leakage current-induced offset in a single-ended op-amp
An electronic device includes an operational amplifier, with the operational amplifier having an amplifier input stage coupled with a first output node to an...
US-7,906,999 Self-protecting core system
The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for...
US-7,906,995 Clock buffer
An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT...
US-7,906,976 Switched capacitor measurement circuit for measuring the capacitance of an input capacitor
A switched capacitor measurement circuit is provided for measuring the capacitance of an input capacitor with a parallel parasitic resistor. The circuit...
US-7,906,441 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-7,906,405 Polysilicon structures resistant to laser anneal lightpipe waveguide effects
Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of...
US-7,906,394 Implanted vertical source-line under straight stack for FLASH EPROM
In FLASH EPROM cells, source diffusion continuity between horizontal and vertical source lines is provided by an arsenic implant under the stack in vertical...
US-7,906,351 Method for metal gate quality characterization
Measuring the amount of unreacted polysilicon gate material in a fully silicided (FUSI) nickel silicide gate process for metal oxide semiconductor (MOS)...
US-7,906,271 System and method for making photomasks
The present disclosure is directed a method for preparing a system of photomask patterns for implementing a drawn pattern on a substrate with a multi-patterning...
US-7,906,253 System and method for making photomasks
The present disclosure is directed to a method for preparing photomask patterns for a lithography process that employs a plurality of photomasks. The method...
US-7,905,418 RFID tag
An RFID tag is provided, which has a transponder part with an antenna coil arranged in the transponder part. A mounting part is also provided for fixing the tag...
US-7,904,854 System and method for checking for sub-resolution assist features
In accordance with the invention, there is provided a system and method for checking a mask layout including sub-resolution assist features (SRAFs). A checking...
US-7,904,774 Wafer scale testing using a 2 signal JTAG interface
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-7,904,496 Method and system for selecting effective tap values for a digital filter
Systems and methods are provided for determining effective tap values for a digital filter. A first plurality of vectors is generated, wherein each of the first...
US-7,904,048 Multi-tap direct sub-sampling mixing system for wireless receivers
A multi-tap direct sub-sampling mixing system for wireless receivers is provided with a dynamically configurable passive switched capacitor filter. A front end...
US-7,903,870 Digital camera and method
Redeye removal methods detect redeyes in a two-step procedure. In the first step it detects faces in the input image and in the second step it searches for...
US-7,903,823 Apparatus and method for effecting sound stage expansion
An apparatus for effecting sound stage expansion in an audio system presenting two sound channels includes: (a) A first signal source coupled for providing at...
US-7,903,439 Methods and apparatus to control a digital power supply
Methods and apparatus to control a digital power supply are disclosed. An example method includes calculating a duty cycle of a pulse width modulated signal to...
US-7,903,433 Current balancing for multi-phase converters
A converter for a multi-phase current network can include a plurality of current sensors, each of the plurality of current sensors being configured to detect...
US-7,903,015 Cascaded DAC architecture with pulse width modulation
An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at...
US-7,902,807 Multiple switch node power converter control scheme that avoids switching sub-harmonics
A method of and system for modulating buck and boost modulation ramps of a multiple switch node power converter without overlap. As the pulse width or duty cycle...
US-7,902,805 Self-oscillating DC-DC buck converter with zero hysteresis
A self-oscillating DC-DC buck converter with zero hysteresis is described. The converter comprises a comparator with a supply input, a non-inverting input to...
US-7,902,778 Programmable constant voltage retract of disk drive actuator
A disk drive system including retract logic for control of the voice coil motor in a retract operation, in which the voice coil motor positions the read/write...
US-7,902,576 Phosphorus activated NMOS using SiC process
A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate...
US-7,902,574 Solid state image pickup device and operating method thereof
This invention provides a type of solid-state image pickup device characterized by the fact that for a solid-state image pickup device with a broad dynamic...
US-7,902,055 Method of manufacturing a dual metal Schottky diode
An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another...
US-7,902,033 Methods and devices for a high-k stacked capacitor
An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend...
US-7,902,032 Method for forming strained channel PMOS devices and integrated circuits therefrom
An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate...
US-7,901,106 Solid-state illuminator for display applications
The disclosure in one aspect provides an illuminator that includes a plurality of segmented diodes to generate a plurality of light beams. In another aspect, the...
US-7,900,113 Debug circuit and a method of debugging
A debug circuit for a multi-mode circuit driven by a clock signal, with an input for a clock signal, and a debug signal generator arranged to generate for each...
US-7,900,110 Optimized JTAG interface
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
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