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Wafer scale testing using a 2 signal JTAG interface
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
Method and system for selecting effective tap values for a digital filter
Systems and methods are provided for determining effective tap values for a digital filter. A first plurality of vectors is generated, wherein each of the first...
Multi-tap direct sub-sampling mixing system for wireless receivers
A multi-tap direct sub-sampling mixing system for wireless receivers is provided with a dynamically configurable passive switched capacitor filter. A front end...
Digital camera and method
Redeye removal methods detect redeyes in a two-step procedure. In the first step it detects faces in the input image and in the second step it searches for...
Apparatus and method for effecting sound stage expansion
An apparatus for effecting sound stage expansion in an audio system presenting two sound channels includes: (a) A first signal source coupled for providing at...
Methods and apparatus to control a digital power supply
Methods and apparatus to control a digital power supply are disclosed. An example method includes calculating a duty cycle of a pulse width modulated signal to...
Current balancing for multi-phase converters
A converter for a multi-phase current network can include a plurality of current sensors, each of the plurality of current sensors being configured to detect...
Cascaded DAC architecture with pulse width modulation
An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at...
Multiple switch node power converter control scheme that avoids switching
A method of and system for modulating buck and boost modulation ramps of a multiple switch node power converter without overlap. As the pulse width or duty cycle...
Self-oscillating DC-DC buck converter with zero hysteresis
A self-oscillating DC-DC buck converter with zero hysteresis is described. The converter comprises a comparator with a supply input, a non-inverting input to...
Programmable constant voltage retract of disk drive actuator
A disk drive system including retract logic for control of the voice coil motor in a retract operation, in which the voice coil motor positions the read/write...
Phosphorus activated NMOS using SiC process
A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate...
Solid state image pickup device and operating method thereof
This invention provides a type of solid-state image pickup device characterized by the fact that for a solid-state image pickup device with a broad dynamic...
Method of manufacturing a dual metal Schottky diode
An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another...
Methods and devices for a high-k stacked capacitor
An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend...
Method for forming strained channel PMOS devices and integrated circuits
An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate...
Solid-state illuminator for display applications
The disclosure in one aspect provides an illuminator that includes a plurality of segmented diodes to generate a plurality of light beams. In another aspect, the...
Debug circuit and a method of debugging
A debug circuit for a multi-mode circuit driven by a clock signal, with an input for a clock signal, and a debug signal generator arranged to generate for each...
Optimized JTAG interface
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
BDX data in stable states
A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions...
Correction of incorrect cache accesses
The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is...
Predictive method to improve within wafer CMP uniformity through optimized
A method of conditioning a CMP polishing pad to attain a desired thickness profile in a polished layer on a wafer is disclosed. The incoming thickness profile of...
Method and apparatus for processing analytical-form compression noise in
images with known statistics
Embodiments of the invention provide methods to calculate compression noise statistics of decompressed images in transform coding. They can be used in compressed...
Method, apparatus and system for detecting anomalies in mixed signal
An embodiment relates generally to a method of testing a mixed signal device. The method includes monitoring multiple parameters of the mixed signal device and...
F-SRAM power-off operation
A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least...
Methods and apparatus to reduce substrate voltage bounces and spike
voltages in switching amplifiers
Methods and apparatus to reduce voltage bounces and spike voltages in switching amplifiers are disclosed. An example method of removing a substrate current from...
Thermal conduction by encapsulation
A packaged electronic device includes a substrate with an upper surface interrupted by a well formed in the substrate. The well has a substrate bottom surface...
System and method for maintaining hue constancy
System and method for maintaining perceived hue constancy. A method for displaying an image includes receiving a color vector and associated image data,...
GNSS receiver with reduced storage requirements
A Global Navigation Satellite System (GNSS) receiver provided according to an aspect of the present invention contains a buffer to store less than a number of...
Correction of sampling mismatch in time-interleaved analog-to-digital
A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a...
Increasing the common mode range of a circuit
Increasing the input common-mode range of a circuit which accepts differential signals as inputs. Such an increase may be attained by correcting an input signal...
A driver is provided. The driver generally comprises a current source, a current mirror, an amplifier and a presetting circuit. The current source is generally...
Known good die using existing process infrastructure
An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the...
Method for low stress flip-chip assembly of fine-pitch semiconductor
A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column...
Stacked flip-assembled semiconductor chips embedded in thin hybrid
A semiconductor system having a substrate (101) including a rigid insulating interposer (110) with a high modulus and a top (140) and a bottom (150) low-modulus...
Method of making (100) NMOS and (110) PMOS sidewall surface on the same
fin orientation for multiple gate...
A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin...
Method and apparatus for driving a liquid lens
A liquid lens driver 10 has DC-DC converter 12, oscillator 14, pulse width modulator 16, and control logic circuit 18. The output buffer circuit 30 divides...
Method for forming a metal silicide
The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing...
Semiconductor doping with reduced gate edge diode leakage
Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and...
Use of in-situ HCL etch to eliminate by oxidation recrystallization border
defects generated during solid phase...
A method for reducing defects at an interface between a amorphized, recrystallized cleaved wafer layer and an unamorphized cleaved wafer layer can comprise an...
Close proximity scanning surface contamination analyzer
Reducing chemical contaminants is increasingly important for maintaining competitive production costs during fabrication of electronic devices. There is...
Verification method with the implementation of well voltage pseudo diodes
A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a...
Generation of standard cell library components with increased signal
Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed....
Matrix system and method for debugging scan structure
An aspect of the present invention is drawn to a system that includes an automatic test engine, a decompressor, a first scan chain, a second scan chain, a...
Estimation of power level in a communication device
A system comprising a first communication device and a second communication device adapted to determine a property of communications between the first and second...
Method and system for controlling carrier leakage in a direct conversion
A system for controlling carrier leakage in a communications device includes a first mixer unit operable to receive and convert a first signal into a second...
Method and apparatus for reducing ringing artifacts
A method and apparatus for ringing artifacts reduction for compressed video signals. The method includes receiving luma data to the digital signal processor,...
Calibration model to mitigate data conversion errors
An error model can be utilized to mitigate errors associated with a conversion system, such as an analog-to-digital or digital-to analog converter. The error...
Self-calibrated adaptive equalization system and methods of performing the
A self-calibrating, adaptive equalization system for generating an ideal digital signal is disclosed. The adaptive equalization system includes an equalizer and...
System and method of flexible channel allocation in an ultra wideband
(UWB) frequency hopping communication system
A system and method of flexible channel allocation in an ultra wideband frequency hopping communication system is disclosed. In one embodiment, a method includes...