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Integrated channel diode
A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over...
MOS transistor with varying channel width
One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the...
TCAM providing efficient move contents operation
An embodiment of the invention includes a Ternary Content Addressable Memory (TCAM) that includes a group of TCAM block. Each TCAM block stores a number of...
Method and system for preventing unauthorized processor mode switches
A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing...
Unified input/output controller for integrated wireless devices
A novel and useful apparatus for and method of a unified IO controller well suited for use in integrated wireless devices incorporating multiple functions. The...
Power regulation with load detection
One embodiment of the present invention includes a power regulator system. The system includes a power stage configured to provide an output voltage to a load...
Integrated circuits and methods for testing integrated circuits are disclosed herein. An embodiment of an integrated circuit includes a microprocessor and...
Wafer scale testing using a 2 signal JTAG interface
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
Optical electronic device and method of fabrication
An optical electronic device and method that forms cavities through an interposer wafer after bonding the interposer wafer to a window wafer. The cavities are...
Distributed power control for controlling power consumption based on
detected activity of logic blocks
An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller...
ID-based control unit-key fob pairing
A key fob includes a transceiver to send and receive signals, a memory to store a key fob identification (KFID), and a processor coupled to said transceiver and...
Initial command to switch transistors disconnecting keys from microphone
An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in...
Method and circuitry for direction of arrival estimation using microphone
array with a sharp null
A device is configured for identifying a direction of a sound. The device includes a controller comprising circuitry. The circuitry is configured to receive a...
IIR DFE updating gain and time constants using LMS equations
A method for adapting a mixed signal Infinite Impulse Response (IIR) Decision Feedback Equalizer (DFE) using pivot taps and monitor taps is disclosed. The...
Gain and offset correction in an interpolation ADC
In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a...
Position detecting system
A position detecting system detects and responds to the movement of a target through a sensing domain area of a plane. The movement causes the amount of the...
Self-aligned under bump metal
An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with...
2-pin interface with data input, data output, address match input
A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One...
Low dropout voltage regulator circuits
In an embodiment, a voltage regulator is disclosed. The voltage regulator circuit includes a switch, a first feedback circuit and a second feedback circuit. The...
Divided scan path cells with first and state hold multiplexers
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan...
Low power Scan-BIST test data generator and compactor pass/fail output
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
Apparatus and methods for qualifying HEMT FET devices
A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain...
Allocation and logical to physical mapping of scheduling request indicator
channel in wireless networks
A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is...
Computer generated sequences for downlink and uplink signals in wireless
The present disclosure provides a base station transmitter, a user equipment transmitter and methods of operating the base station and user equipment...
Method and system to improve the performance of a video encoder
Method and system to improve the performance of a video encoder. The method includes processing an initial video signal in a front-end image pre-processor to...
Sample adaptive offset (SAO) filtering in video coding
A method for sample adaptive offset (SAO) filtering of largest coding units (LCUs) of a video frame in an SAO component is provided that includes receiving, by...
Loop filtering managing storage of filtered and unfiltered pixels
A video encoder comprises a loop filter to filter luminance and chrominance pixel values, first and second loop filter working buffers accessible to the loop...
Method and system for reducing slice header parsing overhead in video
A method for encoding a picture of a video sequence in a bit stream that reduces slice header parsing overhead is provided. The method includes determining...
Enabling coordinated multi-point reception
This invention measures the propagation delay .tau..sub.1 between the user equipment and a first cooperating unit and the propagation delay .tau..sub.2 between...
Software reconfigurable digital phase lock loop architecture
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit...
Series arranged multiplexers specification support enablement circuit and
Several circuits and methods that may be implemented to enable specification support of a plurality of interface components in an IC are disclosed. In an...
An amplifier receives a differential signal and, in response, generates a first negative input current and a first positive input current. In a first operating...
Tunable power amplifier with wide frequency range
A circuit includes an amplifier configured to amplify an input signal and generate an output signal. The circuit also includes a tuning network configured to...
Switched mode assisted linear regulator with seamless transition between
power tracking configurations
A Switch Node Assisted Linear architecture, including a linear amplifier in parallel with a switched converter, is configurable in two tracking modes: (a) a...
Dielectric waveguide comprised of a core, a cladding surrounding the core
and cylindrical shape conductive...
A dielectric waveguide (DWG) has a dielectric core member that has a length L and an oblong cross section. The core member has a first dielectric constant...
Isolated semiconductor layer over buried isolation layer
An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of...
Die testing using top surface test pads
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding...
Integrated circuit package strip insert assembly
A plurality of inserts adapted are to be received in a plurality of holes in a support plate having a first surface adapted to engage a first surface of an...
SRAM with buffered-read bit cells and its testing
An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a...
Using L1 cache as re-order buffer
A method is shown that eliminates the need for a dedicated reorder buffer register bank or memory space in a multi level cache system. As data requests from the...
Execution of additional instructions in conjunction atomically as
specified in instruction field
A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a...
Low area full adder with shared transistors
A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input...
Valid context status retention in processor power mode management
A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining...
Microprocessor based power management system architecture
An electronic system is disposed on a single integrated circuit including a plurality of power domains and a power control manager. Each power domain may be...
Split phosphor/slit color wheel segment for color generation in
solid-state illumination system
Apparatus for generating blue color illumination for use in a projection system a color wheel with segments of respective different color light emitting...
Embedded parallel scan paths, stimulus formatter, and control interface
The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and...
Capacitive MEMS sensor devices
A packaged capacitive MEMS sensor device includes at least one capacitive MEMS sensor element with at least one capacitive MEMS sensor cell including a first...
Interdigitated chip capacitor assembly
A method of registering terminals on an interdigitated chip capacitor ("IDC") with a plurality of contact pads on a substrate. At least one vertically extending...
Power module with improved cooling and method for making
Disclosed examples include power modules and fabrication methods therefor in which one or more power device dies include a switching device and a second device...
Combined hybrid and local dimming control of light emitting diodes
An LED backlight controller combines global/hybrid and local brightness/dimming control for an LED backlight illuminator with local regions illuminated by...