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Patent # Description
US-7,906,999 Self-protecting core system
The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for...
US-7,906,995 Clock buffer
An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT...
US-7,906,976 Switched capacitor measurement circuit for measuring the capacitance of an input capacitor
A switched capacitor measurement circuit is provided for measuring the capacitance of an input capacitor with a parallel parasitic resistor. The circuit...
US-7,906,441 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-7,906,405 Polysilicon structures resistant to laser anneal lightpipe waveguide effects
Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of...
US-7,906,394 Implanted vertical source-line under straight stack for FLASH EPROM
In FLASH EPROM cells, source diffusion continuity between horizontal and vertical source lines is provided by an arsenic implant under the stack in vertical...
US-7,906,351 Method for metal gate quality characterization
Measuring the amount of unreacted polysilicon gate material in a fully silicided (FUSI) nickel silicide gate process for metal oxide semiconductor (MOS)...
US-7,906,271 System and method for making photomasks
The present disclosure is directed a method for preparing a system of photomask patterns for implementing a drawn pattern on a substrate with a multi-patterning...
US-7,906,253 System and method for making photomasks
The present disclosure is directed to a method for preparing photomask patterns for a lithography process that employs a plurality of photomasks. The method...
US-7,905,418 RFID tag
An RFID tag is provided, which has a transponder part with an antenna coil arranged in the transponder part. A mounting part is also provided for fixing the tag...
US-7,904,854 System and method for checking for sub-resolution assist features
In accordance with the invention, there is provided a system and method for checking a mask layout including sub-resolution assist features (SRAFs). A checking...
US-7,904,774 Wafer scale testing using a 2 signal JTAG interface
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-7,904,496 Method and system for selecting effective tap values for a digital filter
Systems and methods are provided for determining effective tap values for a digital filter. A first plurality of vectors is generated, wherein each of the first...
US-7,904,048 Multi-tap direct sub-sampling mixing system for wireless receivers
A multi-tap direct sub-sampling mixing system for wireless receivers is provided with a dynamically configurable passive switched capacitor filter. A front end...
US-7,903,870 Digital camera and method
Redeye removal methods detect redeyes in a two-step procedure. In the first step it detects faces in the input image and in the second step it searches for...
US-7,903,823 Apparatus and method for effecting sound stage expansion
An apparatus for effecting sound stage expansion in an audio system presenting two sound channels includes: (a) A first signal source coupled for providing at...
US-7,903,439 Methods and apparatus to control a digital power supply
Methods and apparatus to control a digital power supply are disclosed. An example method includes calculating a duty cycle of a pulse width modulated signal to...
US-7,903,433 Current balancing for multi-phase converters
A converter for a multi-phase current network can include a plurality of current sensors, each of the plurality of current sensors being configured to detect...
US-7,903,015 Cascaded DAC architecture with pulse width modulation
An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at...
US-7,902,807 Multiple switch node power converter control scheme that avoids switching sub-harmonics
A method of and system for modulating buck and boost modulation ramps of a multiple switch node power converter without overlap. As the pulse width or duty cycle...
US-7,902,805 Self-oscillating DC-DC buck converter with zero hysteresis
A self-oscillating DC-DC buck converter with zero hysteresis is described. The converter comprises a comparator with a supply input, a non-inverting input to...
US-7,902,778 Programmable constant voltage retract of disk drive actuator
A disk drive system including retract logic for control of the voice coil motor in a retract operation, in which the voice coil motor positions the read/write...
US-7,902,576 Phosphorus activated NMOS using SiC process
A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate...
US-7,902,574 Solid state image pickup device and operating method thereof
This invention provides a type of solid-state image pickup device characterized by the fact that for a solid-state image pickup device with a broad dynamic...
US-7,902,055 Method of manufacturing a dual metal Schottky diode
An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another...
US-7,902,033 Methods and devices for a high-k stacked capacitor
An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend...
US-7,902,032 Method for forming strained channel PMOS devices and integrated circuits therefrom
An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate...
US-7,901,106 Solid-state illuminator for display applications
The disclosure in one aspect provides an illuminator that includes a plurality of segmented diodes to generate a plurality of light beams. In another aspect, the...
US-7,900,113 Debug circuit and a method of debugging
A debug circuit for a multi-mode circuit driven by a clock signal, with an input for a clock signal, and a debug signal generator arranged to generate for each...
US-7,900,110 Optimized JTAG interface
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
US-7,900,109 BDX data in stable states
A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions...
US-7,900,020 Correction of incorrect cache accesses
The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is...
US-7,899,571 Predictive method to improve within wafer CMP uniformity through optimized pad conditioning
A method of conditioning a CMP polishing pad to attain a desired thickness profile in a polished layer on a wafer is disclosed. The incoming thickness profile of...
US-7,899,263 Method and apparatus for processing analytical-form compression noise in images with known statistics
Embodiments of the invention provide methods to calculate compression noise statistics of decompressed images in transform coding. They can be used in compressed...
US-7,899,237 Method, apparatus and system for detecting anomalies in mixed signal devices
An embodiment relates generally to a method of testing a mixed signal device. The method includes monitoring multiple parameters of the mixed signal device and...
US-7,898,837 F-SRAM power-off operation
A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least...
US-7,898,783 Methods and apparatus to reduce substrate voltage bounces and spike voltages in switching amplifiers
Methods and apparatus to reduce voltage bounces and spike voltages in switching amplifiers are disclosed. An example method of removing a substrate current from...
US-7,898,724 Thermal conduction by encapsulation
A packaged electronic device includes a substrate with an upper surface interrupted by a well formed in the substrate. The well has a substrate bottom surface...
US-7,898,706 System and method for maintaining hue constancy
System and method for maintaining perceived hue constancy. A method for displaying an image includes receiving a color vector and associated image data,...
US-7,898,475 GNSS receiver with reduced storage requirements
A Global Navigation Satellite System (GNSS) receiver provided according to an aspect of the present invention contains a buffer to store less than a number of...
US-7,898,446 Correction of sampling mismatch in time-interleaved analog-to-digital converters
A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a...
US-7,898,331 Increasing the common mode range of a circuit
Increasing the input common-mode range of a circuit which accepts differential signals as inputs. Such an increase may be attained by correcting an input signal...
US-7,898,321 Driver circuit
A driver is provided. The driver generally comprises a current source, a current mirror, an amplifier and a presetting circuit. The current source is generally...
US-7,898,275 Known good die using existing process infrastructure
An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the...
US-7,898,083 Method for low stress flip-chip assembly of fine-pitch semiconductor devices
A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column...
US-7,898,069 Stacked flip-assembled semiconductor chips embedded in thin hybrid substrate
A semiconductor system having a substrate (101) including a rigid insulating interposer (110) with a high modulus and a top (140) and a bottom (150) low-modulus...
US-7,897,994 Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate...
A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin...
US-7,897,899 Method and apparatus for driving a liquid lens
A liquid lens driver 10 has DC-DC converter 12, oscillator 14, pulse width modulator 16, and control logic circuit 18. The output buffer circuit 30 divides...
US-7,897,513 Method for forming a metal silicide
The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing...
US-7,897,496 Semiconductor doping with reduced gate edge diode leakage
Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and...
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