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Patent # Description
US-7,899,571 Predictive method to improve within wafer CMP uniformity through optimized pad conditioning
A method of conditioning a CMP polishing pad to attain a desired thickness profile in a polished layer on a wafer is disclosed. The incoming thickness profile of...
US-7,899,263 Method and apparatus for processing analytical-form compression noise in images with known statistics
Embodiments of the invention provide methods to calculate compression noise statistics of decompressed images in transform coding. They can be used in compressed...
US-7,899,237 Method, apparatus and system for detecting anomalies in mixed signal devices
An embodiment relates generally to a method of testing a mixed signal device. The method includes monitoring multiple parameters of the mixed signal device and...
US-7,898,837 F-SRAM power-off operation
A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least...
US-7,898,783 Methods and apparatus to reduce substrate voltage bounces and spike voltages in switching amplifiers
Methods and apparatus to reduce voltage bounces and spike voltages in switching amplifiers are disclosed. An example method of removing a substrate current from...
US-7,898,724 Thermal conduction by encapsulation
A packaged electronic device includes a substrate with an upper surface interrupted by a well formed in the substrate. The well has a substrate bottom surface...
US-7,898,706 System and method for maintaining hue constancy
System and method for maintaining perceived hue constancy. A method for displaying an image includes receiving a color vector and associated image data,...
US-7,898,475 GNSS receiver with reduced storage requirements
A Global Navigation Satellite System (GNSS) receiver provided according to an aspect of the present invention contains a buffer to store less than a number of...
US-7,898,446 Correction of sampling mismatch in time-interleaved analog-to-digital converters
A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a...
US-7,898,331 Increasing the common mode range of a circuit
Increasing the input common-mode range of a circuit which accepts differential signals as inputs. Such an increase may be attained by correcting an input signal...
US-7,898,321 Driver circuit
A driver is provided. The driver generally comprises a current source, a current mirror, an amplifier and a presetting circuit. The current source is generally...
US-7,898,275 Known good die using existing process infrastructure
An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the...
US-7,898,083 Method for low stress flip-chip assembly of fine-pitch semiconductor devices
A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column...
US-7,898,069 Stacked flip-assembled semiconductor chips embedded in thin hybrid substrate
A semiconductor system having a substrate (101) including a rigid insulating interposer (110) with a high modulus and a top (140) and a bottom (150) low-modulus...
US-7,897,994 Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate...
A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin...
US-7,897,899 Method and apparatus for driving a liquid lens
A liquid lens driver 10 has DC-DC converter 12, oscillator 14, pulse width modulator 16, and control logic circuit 18. The output buffer circuit 30 divides...
US-7,897,513 Method for forming a metal silicide
The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing...
US-7,897,496 Semiconductor doping with reduced gate edge diode leakage
Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and...
US-7,897,447 Use of in-situ HCL etch to eliminate by oxidation recrystallization border defects generated during solid phase...
A method for reducing defects at an interface between a amorphized, recrystallized cleaved wafer layer and an unamorphized cleaved wafer layer can comprise an...
US-7,897,410 Close proximity scanning surface contamination analyzer
Reducing chemical contaminants is increasingly important for maintaining competitive production costs during fabrication of electronic devices. There is...
US-7,895,554 Verification method with the implementation of well voltage pseudo diodes
A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a...
US-7,895,551 Generation of standard cell library components with increased signal routing resources
Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed....
US-7,895,489 Matrix system and method for debugging scan structure
An aspect of the present invention is drawn to a system that includes an automatic test engine, a decompressor, a first scan chain, a second scan chain, a...
US-7,894,864 Estimation of power level in a communication device
A system comprising a first communication device and a second communication device adapted to determine a property of communications between the first and second...
US-7,894,787 Method and system for controlling carrier leakage in a direct conversion wireless device
A system for controlling carrier leakage in a communications device includes a first mixer unit operable to receive and convert a first signal into a second...
US-7,894,685 Method and apparatus for reducing ringing artifacts
A method and apparatus for ringing artifacts reduction for compressed video signals. The method includes receiving luma data to the digital signal processor,...
US-7,894,536 Calibration model to mitigate data conversion errors
An error model can be utilized to mitigate errors associated with a conversion system, such as an analog-to-digital or digital-to analog converter. The error...
US-7,894,517 Self-calibrated adaptive equalization system and methods of performing the same
A self-calibrating, adaptive equalization system for generating an ideal digital signal is disclosed. The adaptive equalization system includes an equalizer and...
US-7,894,503 System and method of flexible channel allocation in an ultra wideband (UWB) frequency hopping communication system
A system and method of flexible channel allocation in an ultra wideband frequency hopping communication system is disclosed. In one embodiment, a method includes...
US-7,894,491 Data transfer circuit
A data transfer circuit is provided for sending digital data at high rates across short but significant distances within an integrated circuit. The data is sent...
US-7,894,284 Ferroelectric memory bake for screening and repairing bits
A method (300) of identifying failing bits in a ferroelectric memory device including at least one ferroelectric capacitor includes (302) writing same state data...
US-7,894,280 Asymmetrical SRAM cell with separate word lines
An integrated circuit includes a memory array having a plurality of SRAM memory cells arranged in a plurality of rows and columns, the array also having a...
US-7,894,235 F-RAM device with current mirror sense amp
A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator....
US-7,894,234 F-SRAM before package solid data write
A process of polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation and...
US-7,894,226 Content addressable memory based on a ripple search scheme
A scheme for ultra-low power content addressable memory based on a ripple search is disclosed. In one embodiment, a system for content addressable memory (CAM),...
US-7,894,121 Light valve assembly with a holographic optical element and a method of making the same
A light valve assembly comprises a holographic optical element and a light valve that comprises an array of individually addressable pixels. The light valve...
US-7,893,945 Color mapping techniques for color imaging devices
Disclosed embodiments relate to techniques for color gamut mapping when an input signal transmitting color visual images has a different color gamut than does...
US-7,893,768 Automatic gain control
A method and system for providing automatic gain control for a differential amplifier are provided. An impedance network is set to have a first impedance that...
US-7,893,765 Current canceling variable gain amplifier and transmitter using same
A current canceling CMOS variable gain amplifier includes a first leg and a second leg. The first leg has a first input line, a first output line, a first ON...
US-7,893,746 High speed intra-pair de-skew circuit
For differential signal transmission (especially in high speed applications), intra-pair skew between paths carrying complementary portions of a differential...
US-7,893,734 Power-on reset circuit
An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a...
US-7,893,723 Minimizing leakage in logic designs
Devices and methods are disclosed for logic gate devices to provide reduced leakage while improving performance. The device is configured for low leakage logic...
US-7,893,720 Bus low voltage differential signaling (BLVDS) circuit
A differential signaling circuit and a control circuit. The differential signaling circuit includes a first positive driver and a first negative driver. The...
US-7,893,675 Current mode controlled DC-to-DC converter
An apparatus having an input voltage and an output voltage is provided. The apparatus comprises a switch that receives the input voltage and that is adapted to...
US-7,893,672 Technique to improve dropout in low-dropout regulators by drive adjustment
An electronic device includes a low drop-out regulator for providing a regulated output voltage. The low drop-out regulator generally comprises a power MOSFET...
US-7,893,671 Regulator with improved load regulation
A regulator to provide an output voltage of a constant level at an output node. In an embodiment, the regulator contains a pass transistor to provide a...
US-7,893,544 Semiconductor device having improved contacts
A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across...
US-7,893,499 MOS transistor with gate trench adjacent to drain extension field insulation
An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source...
US-7,892,957 Gate CD trimming beyond photolithography
A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a...
US-7,892,931 Use of a single mask during the formation of a transistor's drain extension and recessed strained epi regions
A method 300 for forming a transistor's drain extension 70 and recessed strained epi regions 150 with a single mask step 306. In an example embodiment, the...
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