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Patent # Description
US-7,872,336 Low cost lead-free preplated leadframe having improved adhesion and solderability
A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack...
US-7,871,931 Method for chemical mechanical planarization of a metal layer located over a photoresist layer and a method for...
The present invention provides a method for planarizing a metal layer, and a method for manufacturing a micro pixel array. The method for planarizing the metal...
US-7,871,864 Locking feature and method for manufacturing transfer molded IC packages
The invention discloses integrated circuits (ICs), molded IC packages, and to leadframe arrays, package arrays and methods for their manufacture. Leadframe...
US-7,870,451 Automatable scan partitioning for low power using external control
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
US-7,870,450 High speed double data rate JTAG interface
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface...
US-7,869,231 System and method for synchronous rectifier drive that enables converters to operate in transition and...
A synchronous rectifier is switched in accordance with a primary switch transition and a reference signal representing current in a current storage device to...
US-7,869,145 System and method for illuminating a target
According to one embodiment of the present invention, a system for illuminating a target includes a light source configured to emit one or more light beams with...
US-7,868,794 Methods and apparatus to test and compensate multi-channel digital-to-analog converters
Methods and apparatus to test and compensate multi-channel digital-to-analog converters (DACs) are described. In some examples, a multi-channel digital-to-analog...
US-7,868,690 Comparator with sensitivity control
A comparator has a differential input stage, a current source coupled to the differential input stage for providing a tail current to one side of the...
US-7,868,670 Phase-locked loop (PLL) circuit and method
A phase-locked loop (PLL) circuit includes a reference clock divider with a reference clock input, a phase-frequency detector, a charge pump, a loop filter, a...
US-7,868,599 Method of optimum current blanking time implementation in current sense circuit
In a method and system for sensing current in a switching regulator (SWR) operating in a current mode, a power switch is coupled to receive the current from a...
US-7,866,852 Heat sinks for cooling LEDs in projectors
According to certain embodiments, an apparatus for cooling light emitting diodes (LEDs) in projectors includes one or more first LEDs, one or more first heat...
US-7,866,036 Method of fabricating micromirror device
A micromirror device and a method of making the same are disclosed herein. The micromirror device comprises a mirror plate, hinge, and post each having an...
US-7,865,849 System and method for estimating test escapes in integrated circuits
A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for...
US-7,865,791 Reduced signaling interface method and apparatus
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,864,661 Time-switched preamble generator, method of generating and multiple-input, multiple-output communication system...
The present invention is directed to a time-switched preamble generator and method of generating a time-switched preamble for use with a multiple-input,...
US-7,864,600 Memory cell employing reduced voltage
A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and...
US-7,864,494 Methodology to guard ESD protection circuits against precharge effects
An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge...
US-7,864,191 Techniques for efficient dithering
A system comprising a storage including an image file associated with a plurality of pixels and processing logic coupled to the storage. The processing logic is...
US-7,863,994 System and method for increasing radio frequency (RF) microwave inductor-capacitor (LC) oscillator frequency...
System and method for increasing the frequency tuning range of a RF/microwave LC oscillator. A preferred embodiment comprises a voltage controlled oscillator...
US-7,863,985 High frequency amplifier linearization technique
An output stage for an amplifier is provided. The amplifier generally provides for compensation of an error current generated by the base-collector (or...
US-7,863,944 Passive clock detector
A clock detector is provided. The clock detector generally comprises a filter, a first branch, a second branch, a latch, and logic. The filter is adapted to...
US-7,863,921 Circuit board and method for automatic testing
A circuit board (CB) and method for automatic testing of an electronic device under test (DUT). The circuit board (CB) has a first terminal (T1) for coupling to...
US-7,863,919 Applying test response start and command signals to power lead
The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device....
US-7,863,913 Parallel scan distributors and collectors and process of testing integrated circuits
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-7,863,738 Apparatus for connecting integrated circuit chip to power and ground circuits
In a method and system for transferring at least one of power and ground signal between a die and a package base of a semiconductor device, a connector is formed...
US-7,863,192 Methods for full gate silicidation of metal gate structures
One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the...
US-7,863,103 Thermally improved semiconductor QFN/SON package
A semiconductor device without cantilevered leads uses conductive wires (120) to connect the chip terminals to the leads (110), and a package compound (140) to...
US-7,863,098 Flip chip package with advanced electrical and thermal properties for high current designs
A QFN package and method of making same is provided comprising a substrate having a metal line extending from a connection element on a perimeter region of the...
US-7,860,710 Methods, devices and systems for improved codebook search for voice codecs
An electronic circuit (1100) including a processor circuit (1110) and a storage circuit establishing a speech coder (1170) for execution by said processor...
US-7,860,152 Wireless communications system with secondary synchronization code based on values in primary synchronization code
A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting...
US-7,860,132 Comma free codes for fast cell search using tertiary synchronization channel
A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a...
US-7,860,028 Flexible ethernet bridge
Flooding in an Ethernet bridge can be minimized by employing various techniques. In one embodiment using an address table containing a plurality of entries, each...
US-7,859,985 Control on at least one frequency selecting data carrier frequencies
System and method for signaling control information in a multi-carrier communications system to transmit data. A preferred embodiment comprises demodulating a...
US-7,859,289 Method for measuring interface traps in thin gate oxide MOSFETS
A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined...
US-7,859,275 Parallel scan distributors and collectors and process of testing integrated circuits
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-7,859,237 Method and apparatus for voltage to current conversion
A voltage to current converter that can provide multiple current sources at differing voltage levels using a single inductor, without the need to provide a...
US-7,859,131 Sample and hold scheme for a feedback network of a power converter
One embodiment of the invention includes a system for regulating an output voltage of a power converter. The system comprises an error amplifier that compares a...
US-7,859,024 Integrated circuit having efficiently packed decoupling capacitors
An integrated circuit includes a substrate having a semiconducting surface (605) and a plurality of standard cells arranged in a plurality of rows including at...
US-7,858,459 Work function adjustment with the implant of lanthanides
Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal...
US-7,857,463 Optical system for a thin, low-chin, projection television
A micro-mirror based projection display system in an enclosure with minimum chin and depth measurements is disclosed. A solid-state laser light source generates...
US-7,856,328 Systems, methods and circuits for determining potential battery failure based on a rate of change of internal...
Various systems and methods for determining potential battery failure are disclosed. For example, some embodiments of the present invention provide battery...
US-7,855,907 Mitigation of charge sharing in memory devices
One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to...
US-7,855,903 System and method for programming an internal parameter or feature in a power converter with a multi-function...
A programmable parameter or feature is provided for a power converter through a multi-function connection on the converter controller. The parameter or feature...
US-7,855,863 Driver with electrostatic discharge protection
Various apparatuses, methods and systems for protecting a driver from electrostatic discharge are disclosed herein. For example, some exemplary embodiments...
US-7,855,849 Methods and apparatus for temperature compensation for hard disk drive write overshoot current
Methods and apparatus for temperature compensation for hard disk drive writer overshoot current are disclosed. A disclosed system comprises creating a first...
US-7,855,812 Cellular phone with scanning capability
A cellular phone is provided with a media scanning capability. Scanner optics, an optional light source and related scanning circuitry is integrated within a...
US-7,855,595 High dynamic range ASK demodulator for use in an RFID transponder
An ASK demodulator for use in an RFID transponder having a limiter circuit associated with the antenna circuit and converting the ASK antenna field strength...
US-7,855,535 Inrush current control
One embodiment of the present invention includes a power supply system. The power supply system comprises a variable voltage source configured to provide and...
US-7,855,432 Integrated thermal characterization and trim of polysilicon resistive elements
Devices, systems, and methods for providing an on-chip, temperature-stable resistance network for generating a precision current or precision resistance are...
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