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Patent # Description
US-7,960,238 Multiple indium implant methods and devices and integrated circuits therefrom
An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate...
US-7,960,234 Multiple-gate MOSFET device and associated manufacturing methods
One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is...
US-7,959,305 Light recycling in a micromirror-based projection display system
A digital micromirror projection display system is disclosed in which "off" pixel light is recaptured and recycled. In the disclosed system, a digital...
US-7,958,420 Clock delay circuits and multiplexer connected to boundary scan circuitry
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits...
US-7,958,419 Entering a shift-DR state in one of star connected components
A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method...
US-7,958,408 On-chip receiver sensitivity test mechanism
An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The...
US-7,957,760 Method and apparatus for transmit power control in wireless data communications systems
The distance between a first Multi Band Orthogonal Frequency Division Multiplex (MB-OFDM) data transceiver and a second or more such transceiver is determined...
US-7,957,759 Wideband reference signal transmission in SC-FDMA communication systems
Embodiments of the invention provide methods for transmitting reference signals (RS) from user equipments (UEs) in wireless communication systems. These RS are...
US-7,957,713 Method for calibrating automatic gain control in wireless devices
Disclosed herein is an iterative process for calibrating an AGC in a wireless system, wherein the iterative process comprises transmitting a calibration signal,...
US-7,957,534 System and method for security association between communication devices within a wireless home network
Embodiments of the application describe a method and system for discovering and authenticating communication devices and establishing a secure communication...
US-7,957,493 Candidate generation
A method and system for generating a set of candidate symbols. A system includes a Multiple Input Multiple Output ("MIMO") receiver. The receiver includes a...
US-7,957,484 Candidate list generation and interference cancellation framework for MIMO detection
A method and system for performing Multiple-Input Multiple-Output ("MIMO") detection that reduces complexity by decomposing MIMO detection problem into two less...
US-7,957,474 Robust detection of packet types
Disclosed herein is a system and method for determining the presence of rotated-BPSK modulation. In addition, disclosed herein is a system and method for...
US-7,957,362 System and method of communication in mesh networks
A network node is provided that includes a transceiver and a component. The transceiver is operable for communication of messages having a broadcast portion and...
US-7,957,178 Storage cell having buffer circuit for driving the bitline
An integrated circuit includes a memory array including a plurality of memory cells, the memory cells include a core storage element having at least a first...
US-7,956,941 Method and apparatus for reducing speckle in coherent light
According to one embodiment, a method for reducing speckle in an image produced from a coherent light source includes directing a beam of coherent light at an...
US-7,956,878 Pulse width modulation algorithm
In display systems employing spatial light modulators, the OFF-state light from OFF-state pixels of the spatial light modulator can be captured and directed...
US-7,956,456 Thermal interface material design for enhanced thermal performance and improved package structural integrity
An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device...
US-7,956,445 Packaged integrated circuit having gold removed from a lead frame
A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top...
US-7,956,357 Test pads coupled with leads unconnected with die pads
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding...
US-7,955,956 Method for recycling/reclaiming a monitor wafer
The invention provides a method for recycling/reclaiming a monitor or test wafer and a method for testing an integrated circuit manufacturing process. After a...
US-7,955,041 Quick changeover apparatus and methods for wafer handling
Quick changeover apparatus for wafer handlers capable of handling at least two sizes of wafer frames and methods of using such apparatus are disclosed.
US-7,954,030 Automatable scan partitioning for low power using external control
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
US-7,954,027 Reduced signaling interface method and apparatus
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,954,026 TAM controller connected with TAM and functional core wrapper circuit
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard...
US-7,954,024 Selecting scan test/TAP with FF receiving lock in and update-IR
A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an...
US-7,952,378 Tunable stress technique for reliability degradation measurement
Apparatus and methods are disclosed for examining how reliability in an RF power amplifier circuit changes as a function of variation of the input to output...
US-7,952,178 Package for an integrated circuit
According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of...
US-7,952,145 MOS transistor device in common source configuration
A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the...
US-7,949,920 DFT techniques to reduce test time and power for SoCs
A technique for reducing the overhead of daisy chain test mode in divide-and-conquer testing using intermediate test modes that do not span all cores or all...
US-7,949,917 Maintaining data coherency in multi-clock systems
A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a...
US-7,949,323 Local oscillator leakage counterbalancing in a receiver
The present invention provides a local oscillator (LO) leakage controller for use with a receiver. In one embodiment, the LO leakage controller includes a...
US-7,949,064 Codebook and pre-coder selection for closed-loop mimo
A method of transmitting a communication signal (FIG. 1) is disclosed. The method includes receiving a data signal (102). The method further includes receiving...
US-7,948,866 Low complexity design of primary synchronization sequence for OFDMA
The present disclosure provides a base station transmitter, a user equipment receiver and methods of operating a base station transmitter and a user equipment...
US-7,948,499 Color control algorithm for use in display systems
A color control algorithm compensates variations in the display system so as to maintain color consistency in the projected images on the screen by constructing...
US-7,948,410 Multibit recyclic pipelined ADC architecture
An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit...
US-7,948,319 Current-mirroring systems and methods
One embodiment of the invention includes a current-mirror system. The system includes a current-mirror circuit configured to conduct an input current through a...
US-7,948,316 Low bias current amplifier
An amplifier is provided that includes an output portion that sources and sinks current associated with an output load and an amplification portion that is...
US-7,948,199 Single-ended gain stage and disk drive
An electrical apparatus comprising an amplifier having a first input, a second input, and an output. The apparatus further comprises a first electrical path...
US-7,947,602 Conductive pattern formation method
The objective of the present invention is to offer a method for forming a conductive pattern on a substrate and solder protrusions on the conductive pattern....
US-7,945,875 Methodology for hierarchy separation at asynchronous clock domain boundaries for multi-voltage optimization...
This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and...
US-7,945,838 Parity check decoder architecture
A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder...
US-7,945,832 Interface to full and reduced pin JTAG devices
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced...
US-7,945,831 Gating TDO from plural JTAG circuits
Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan...
US-7,945,008 Systems and methods for lattice enumeration-aided detection
Embodiments provide systems and methods for improved multiple-input, multiple-output (MIMO) detection comprising generating at least one list of candidate...
US-7,944,904 Systems and methods for managing timing functions in multiple timing protocols
One embodiment of the present invention includes a system for managing timing functions associating with at least one timing protocol. The system comprises a...
US-7,944,819 System and method for transmission and acknowledgment of blocks of data frames in distributed wireless networks
The present application describes a system and method for transmitting and acknowledging a block of frames in a wireless network. According to an embodiment, a...
US-7,944,503 Interlaced-to-progressive video processing
An edge direction vector determination, which can be used for video interlaced-to-progressive conversion by motion-adaptive interpolation, has a coarse edge...
US-7,944,379 SAR ADC and method with INL compensation
An apparatus for analog-to-digital conversion using successive approximation is provided. There is a successive approximation register or SAR controller for...
US-7,944,348 Tire monitoring device and tire problem detecting device
A device to accurately identify the wheel position where each tire has a radio wave transmitter installed without special means or operation during application...
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