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Patent # Description
US-7,892,957 Gate CD trimming beyond photolithography
A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a...
US-7,892,931 Use of a single mask during the formation of a transistor's drain extension and recessed strained epi regions
A method 300 for forming a transistor's drain extension 70 and recessed strained epi regions 150 with a single mask step 306. In an example embodiment, the...
US-7,892,930 Method to improve transistor tox using SI recessing with no additional masking steps
A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure...
US-7,892,908 Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon...
Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as...
US-7,892,906 Method for forming CMOS transistors having FUSI gate electrodes and targeted work functions
A method for making CMOS transistors that includes forming a NMOS transistor and a PMOS transistor having an undoped polysilicon gate electrode and a hardmask....
US-7,892,889 Array-processed stacked semiconductor packages
One embodiment of the invention is a semiconductor system (1400) of arrays (1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate...
US-7,891,937 Adjustable width cassette for wafer film frames
An expandable width cassette for storing and transporting thin planar objects of different widths is provided. The cassette 10 includes two side panels 12 of...
US-7,890,914 Layout data reduction for use with electronic design automation tools
A system and method which stores a three dimensional physical representation of an electrical circuit such as an integrated circuit design uses a database having...
US-7,890,912 Treatment of trim photomask data for alternating phase shift lithography
In accordance with the invention, there is a method of designing a lithography mask. The method can comprise generating initial phase photomask data and initial...
US-7,890,829 Reduced signaling interface method and apparatus
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,890,825 Data summing boundary cell
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one...
US-7,890,753 Secure mode for processors supporting MMU and interrupts
A digital system is provided with a secure mode (3.sup.rd level of privilege) built in a non-invasive way on a processor system that includes a processor core,...
US-7,890,735 Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0,...
US-7,890,566 Microprocessor with rounding dot product instruction
A functional unit in a digital system is provided with a rounding DOT product instruction, wherein a product of first pair of elements is combined with a product...
US-7,890,335 Sharing wavelet domain components among encoded signals
A system for sharing wavelet domain components among encoded signals receives a set of signals decomposed and encoded according to a wavelet transform. The...
US-7,890,316 Synchronizing on-chip data processor trace and timing information for export
Emulation information indicative of internal operations of a data processor can be provided for use by an apparatus external to the data processor. A stream of...
US-7,889,807 Scalable VLSI architecture for K-best breadth-first decoding
In some embodiments, a device includes a multiple-input multiple-output ("MIMO") decoder module coupled to a first log-likelihood-ratio ("LLR") computing unit....
US-7,889,737 Locally administered MAC address based method for selectively and efficiently identifying enhanced version...
Embodiments of the invention provide a method for selectively identifying nodes implemented enhanced version of a standard by creating a random locally...
US-7,889,635 Versatile system for dual carrier transformation in orthogonal frequency division multiplexing
The present invention provides a versatile system for selectively spreading carrier data across multiple carrier paths within an Orthogonal Frequency Division...
US-7,889,535 F-SRAM margin screen
A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to...
US-7,889,452 Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers
Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers are disclosed. A timer in a hard disk drive preamplifier...
US-7,889,011 Output short circuit and load detection
One embodiment of an apparatus for testing an amplifier includes an amplifier having a driver and a filter, the filter being connected between an output of the...
US-7,889,001 Systems and methods of reduced distortion in a class D amplifier
Systems and methods for reduced distortion in a class D amplifier are provided. An "ideal" digital output signal is produced. The "ideal" digital output signal...
US-7,888,996 Chopper stabilized operational amplifier
Chopper stabilized operational amplifiers are in common use. One drawback of these amplifiers, however, is that there is an inherent tone present at the chopper...
US-7,888,993 Bias current generator for multiple supply voltage circuit
An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current...
US-7,888,965 Defining a default configuration for configurable circuitry in an integrated circuit
An integrated circuit with a configurable portion, such as an input/output port, that can be placed in a default configuration prior to actual configuration of...
US-7,888,924 Combination continuous and discontinuous control of a power regulator
A power regulator system is described. The system includes a switching system comprising at least one switch and an inductor, the switching system being...
US-7,888,923 Dynamic phase manager for multi-phase switching regulators
An apparatus is provided. The apparatus comprises a current sensor, an error amplifier, a comparator, an analog-to-digital converter (ADC), control logic, and...
US-7,888,776 Capacitor-based method for determining and characterizing scribe seal integrity and integrity loss
One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an...
US-7,888,732 Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric
An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top...
US-7,888,227 Integrated circuit inductor with integrated vias
Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous...
US-7,888,225 Method of manufacturing an electronic device including a PNP bipolar transistor
A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an...
US-7,888,196 Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom
A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in...
US-7,888,192 Process for forming integrated circuits with both split gate and common gate FinFET transistors
A method is disclosed for forming an integrated circuit including a common gate FinFET device and a split gate FinFET device. Taller fins and shorter fins of...
US-7,887,875 Method to reduce photoresist poisoning
A silicon rich anti-reflective coating (30) is formed on a layer (10) in which narrow linewidth features are to be formed. Prior to the formation of a...
US-7,886,271 Embedding event information in the timing stream
When events are traced, the timing stream is used to associate events with instructions and indicate pipeline advances precluding the recording of stall cycles....
US-7,886,255 Method for design of programmable data processors
A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters,...
US-7,886,198 Method and system of identifying overlays used by a program
A method and system of identifying overlays used by a program. The overlays may be executable overlays (e.g., overlay programs and dynamically linked library...
US-7,886,194 Event-generating instructions
An information carrier medium containing debugging software that, when executed by a processor, causes the processor to generate an event signal and an event...
US-7,886,134 Loop iteration prediction by supplying pseudo branch instruction for execution at first iteration and storing...
This invention combines a loop support mechanism and a branch prediction mechanism. After an instruction execution unit executes an end block instruction of a...
US-7,886,096 Throughput measurement of a total number of data bits communicated during a communication period
A method, system, and apparatus to hardware initiated throughput (HITM) measurement inside an OCP system using OCP side band signals are disclosed. In one...
US-7,885,687 Device for updating configuration information in a wireless network
In one aspect, a digital device comprises a wireless station, a universal serial bus (USB) port, a memory, and a processor. The processor is configured to detect...
US-7,885,625 RF A/D converter with phased feedback to low noise amplifier
Methods and apparatus to perform radio frequency (RF) analog-to-digital conversion are described. According to one example, a receiver includes an amplifier to...
US-7,885,473 Method of CABAC coefficient magnitude and sign decoding suitable for use on VLIW data processors
This invention decodes coefficient magnitudes in compressed video data using a selected context and speculatively decodes a coefficient sign. The next context...
US-7,885,414 Band-selectable stereo synthesizer using strictly complementary filter pair
A new method is proposed that produces stereophonic sound image out of monaural signal within a selected frequency regions. The system employs a strictly...
US-7,885,211 Selective rank CQI and PMI feedback in wireless networks
Within a wireless network, feedback information is used to determine channel quality. A node in the network receives a configuration message indicating at least...
US-7,885,144 Time-dependant gain control for an amplifier used in receiving echoes
An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an...
US-7,884,988 Supplemental reset pulse
A micromechanical device and system utilizing a supplemental reset pulse to ensure deflectable members deflect to the desired position. After loading data into a...
US-7,884,746 Noise limitation of a signal dependent multibit digital to analog signal conversion
Several methods and a system of noise limitation of a signal dependent multibit digital to analog signal conversion are disclosed. An exemplary embodiment...
US-7,884,651 Comparator
An electronic device compares a first voltage with a selected first reference voltage or second reference voltage. The electronic device includes a comparator...
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