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Method of manufacturing an electronic device including a PNP bipolar
A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an...
Trench isolation comprising process having multiple gate dielectric
thicknesses and integrated circuits therefrom
A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in...
Process for forming integrated circuits with both split gate and common
gate FinFET transistors
A method is disclosed for forming an integrated circuit including a common gate FinFET device and a split gate FinFET device. Taller fins and shorter fins of...
Method to reduce photoresist poisoning
A silicon rich anti-reflective coating (30) is formed on a layer (10) in which narrow linewidth features are to be formed. Prior to the formation of a...
Embedding event information in the timing stream
When events are traced, the timing stream is used to associate events with instructions and indicate pipeline advances precluding the recording of stall cycles....
Method for design of programmable data processors
A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters,...
Method and system of identifying overlays used by a program
A method and system of identifying overlays used by a program. The overlays may be executable overlays (e.g., overlay programs and dynamically linked library...
An information carrier medium containing debugging software that, when executed by a processor, causes the processor to generate an event signal and an event...
Loop iteration prediction by supplying pseudo branch instruction for
execution at first iteration and storing...
This invention combines a loop support mechanism and a branch prediction mechanism. After an instruction execution unit executes an end block instruction of a...
Throughput measurement of a total number of data bits communicated during
a communication period
A method, system, and apparatus to hardware initiated throughput (HITM) measurement inside an OCP system using OCP side band signals are disclosed. In one...
Device for updating configuration information in a wireless network
In one aspect, a digital device comprises a wireless station, a universal serial bus (USB) port, a memory, and a processor. The processor is configured to detect...
RF A/D converter with phased feedback to low noise amplifier
Methods and apparatus to perform radio frequency (RF) analog-to-digital conversion are described. According to one example, a receiver includes an amplifier to...
Method of CABAC coefficient magnitude and sign decoding suitable for use
on VLIW data processors
This invention decodes coefficient magnitudes in compressed video data using a selected context and speculatively decodes a coefficient sign. The next context...
Band-selectable stereo synthesizer using strictly complementary filter
A new method is proposed that produces stereophonic sound image out of monaural signal within a selected frequency regions. The system employs a strictly...
Selective rank CQI and PMI feedback in wireless networks
Within a wireless network, feedback information is used to determine channel quality. A node in the network receives a configuration message indicating at least...
Time-dependant gain control for an amplifier used in receiving echoes
An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an...
Supplemental reset pulse
A micromechanical device and system utilizing a supplemental reset pulse to ensure deflectable members deflect to the desired position. After loading data into a...
Noise limitation of a signal dependent multibit digital to analog signal
Several methods and a system of noise limitation of a signal dependent multibit digital to analog signal conversion are disclosed. An exemplary embodiment...
An electronic device compares a first voltage with a selected first reference voltage or second reference voltage. The electronic device includes a comparator...
Setting operating mode of an interface using multiple protocols
This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention includes a plurality of operational units...
Process for precision placement of integrated circuit overcoat material
The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without...
Poison-free and low ULK damage integration scheme for damascene
A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra...
Semiconductor device with an improved solder joint
A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and...
Advanced CMOS using super steep retrograde wells
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer...
Method of forming semiconductor wells
A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a...
Gate dielectric/isolation structure formation in high/low voltage regions
of semiconductor device
A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed...
Multi layer low cost cavity substrate fabrication for PoP packages
In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to...
Method to measure ion beam angle
A device and method for measuring ion beam angle with respect to a substrate is disclosed. The method includes forming a plurality of shadowing structures...
Graded lithographic mask
In one aspect there is provided a gray scale lithographic mask that comprises a transparent substrate and a metallic layer located over the substrate, wherein...
Method for preparing a source material for ion implantation
The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method...
System and method for displaying images
System and method for thin projection display systems. An embodiment comprises a light source, an array of light modulators optically coupled to the light...
Transfer mask in micro ball mounter
The objective of this invention is to provide a transfer mask that is able to accurately pass micro-balls onto terminal areas on a substrate. A thin plate...
Solid-state sensor and manufacturing method thereof
A sensor having photodiodes whose sensitivity and storage capacity can be increased is provided. The sensor is formed by arranging the photodiodes in an array...
IEEE 1149.1 and P1500 test interfaces combined circuits and processes
In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally...
Selectable JTAG or trace access with data store and output
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and...
Address and TMS gating circuitry for TAP control circuit
The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a...
Dual mode test access port method and apparatus
Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves...
Core circuit test architecture
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections....
Scalable distributed routing scheme for PCI express switches
A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first...
Quadrature receiver with correction engine, coefficient controller and
Methods and apparatus to compensate for I/Q mismatch in quadrature receivers are disclosed. An example apparatus disclosed herein comprises a correction engine...
High data rate closed loop MIMO scheme combining transmit diversity and
Closed loop multiple-antenna wireless communications system with antenna weights determined by maximizing a composite channel signal-to-interference-plus-noise...
Adaptive allocation of communications link channels to I- or Q-subchannel
System and method for adaptively allocating channels to subchannels and maintain balance on the subchannels. A preferred embodiment comprises an assignment unit...
Adaptive upstream bandwidth estimation and shaping
One embodiment of the present invention includes a method for adaptively estimating available upstream bandwidth in a network. The method comprises monitoring...
Pulse width modulation algorithm
In display systems employing spatial light modulators, the OFF-state light from OFF-state pixels of the spatial light modulator can be captured and directed back...
Control timing for spatial light modulator
A spatial light modulator clocking method, called fast-clear, which employs embedded clear hardware in the SLM to enable the fast-clear bit to generate...
Method and apparatus for unit interval calculation of displayport
auxilliary channel without CDR
A method for decoding a Manchester-II encoded DISPLAYPORT compatible signal is provided. In this method, several counters are reset. A unit interval (UI) counter...
Parallel scan distributors and collectors and process of testing
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
JTAG bus communication method and apparatus
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication...
PC-connectivity for on-chip memory
An interface for converting a traditional scan-chain interface into one where locations in the scan-chain can be read or written to from an addressed interface...
In package ESD protections of IC using a thin film polymer
A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear...