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Patent # Description
US-7,889,452 Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers
Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers are disclosed. A timer in a hard disk drive preamplifier...
US-7,889,011 Output short circuit and load detection
One embodiment of an apparatus for testing an amplifier includes an amplifier having a driver and a filter, the filter being connected between an output of the...
US-7,889,001 Systems and methods of reduced distortion in a class D amplifier
Systems and methods for reduced distortion in a class D amplifier are provided. An "ideal" digital output signal is produced. The "ideal" digital output signal...
US-7,888,996 Chopper stabilized operational amplifier
Chopper stabilized operational amplifiers are in common use. One drawback of these amplifiers, however, is that there is an inherent tone present at the chopper...
US-7,888,993 Bias current generator for multiple supply voltage circuit
An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current...
US-7,888,965 Defining a default configuration for configurable circuitry in an integrated circuit
An integrated circuit with a configurable portion, such as an input/output port, that can be placed in a default configuration prior to actual configuration of...
US-7,888,924 Combination continuous and discontinuous control of a power regulator
A power regulator system is described. The system includes a switching system comprising at least one switch and an inductor, the switching system being...
US-7,888,923 Dynamic phase manager for multi-phase switching regulators
An apparatus is provided. The apparatus comprises a current sensor, an error amplifier, a comparator, an analog-to-digital converter (ADC), control logic, and...
US-7,888,776 Capacitor-based method for determining and characterizing scribe seal integrity and integrity loss
One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an...
US-7,888,732 Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric
An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top...
US-7,888,227 Integrated circuit inductor with integrated vias
Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous...
US-7,888,225 Method of manufacturing an electronic device including a PNP bipolar transistor
A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an...
US-7,888,196 Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom
A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in...
US-7,888,192 Process for forming integrated circuits with both split gate and common gate FinFET transistors
A method is disclosed for forming an integrated circuit including a common gate FinFET device and a split gate FinFET device. Taller fins and shorter fins of...
US-7,887,875 Method to reduce photoresist poisoning
A silicon rich anti-reflective coating (30) is formed on a layer (10) in which narrow linewidth features are to be formed. Prior to the formation of a...
US-7,886,271 Embedding event information in the timing stream
When events are traced, the timing stream is used to associate events with instructions and indicate pipeline advances precluding the recording of stall cycles....
US-7,886,255 Method for design of programmable data processors
A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters,...
US-7,886,198 Method and system of identifying overlays used by a program
A method and system of identifying overlays used by a program. The overlays may be executable overlays (e.g., overlay programs and dynamically linked library...
US-7,886,194 Event-generating instructions
An information carrier medium containing debugging software that, when executed by a processor, causes the processor to generate an event signal and an event...
US-7,886,134 Loop iteration prediction by supplying pseudo branch instruction for execution at first iteration and storing...
This invention combines a loop support mechanism and a branch prediction mechanism. After an instruction execution unit executes an end block instruction of a...
US-7,886,096 Throughput measurement of a total number of data bits communicated during a communication period
A method, system, and apparatus to hardware initiated throughput (HITM) measurement inside an OCP system using OCP side band signals are disclosed. In one...
US-7,885,687 Device for updating configuration information in a wireless network
In one aspect, a digital device comprises a wireless station, a universal serial bus (USB) port, a memory, and a processor. The processor is configured to detect...
US-7,885,625 RF A/D converter with phased feedback to low noise amplifier
Methods and apparatus to perform radio frequency (RF) analog-to-digital conversion are described. According to one example, a receiver includes an amplifier to...
US-7,885,473 Method of CABAC coefficient magnitude and sign decoding suitable for use on VLIW data processors
This invention decodes coefficient magnitudes in compressed video data using a selected context and speculatively decodes a coefficient sign. The next context...
US-7,885,414 Band-selectable stereo synthesizer using strictly complementary filter pair
A new method is proposed that produces stereophonic sound image out of monaural signal within a selected frequency regions. The system employs a strictly...
US-7,885,211 Selective rank CQI and PMI feedback in wireless networks
Within a wireless network, feedback information is used to determine channel quality. A node in the network receives a configuration message indicating at least...
US-7,885,144 Time-dependant gain control for an amplifier used in receiving echoes
An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an...
US-7,884,988 Supplemental reset pulse
A micromechanical device and system utilizing a supplemental reset pulse to ensure deflectable members deflect to the desired position. After loading data into a...
US-7,884,746 Noise limitation of a signal dependent multibit digital to analog signal conversion
Several methods and a system of noise limitation of a signal dependent multibit digital to analog signal conversion are disclosed. An exemplary embodiment...
US-7,884,651 Comparator
An electronic device compares a first voltage with a selected first reference voltage or second reference voltage. The electronic device includes a comparator...
US-7,884,641 Setting operating mode of an interface using multiple protocols
This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention includes a plurality of operational units...
US-7,884,449 Process for precision placement of integrated circuit overcoat material
The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without...
US-7,884,019 Poison-free and low ULK damage integration scheme for damascene interconnects
A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra...
US-7,884,009 Semiconductor device with an improved solder joint
A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and...
US-7,883,977 Advanced CMOS using super steep retrograde wells
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer...
US-7,883,973 Method of forming semiconductor wells
A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a...
US-7,883,955 Gate dielectric/isolation structure formation in high/low voltage regions of semiconductor device
A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed...
US-7,883,936 Multi layer low cost cavity substrate fabrication for PoP packages
In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to...
US-7,883,909 Method to measure ion beam angle
A device and method for measuring ion beam angle with respect to a substrate is disclosed. The method includes forming a plurality of shadowing structures...
US-7,883,822 Graded lithographic mask
In one aspect there is provided a gray scale lithographic mask that comprises a transparent substrate and a metallic layer located over the substrate, wherein...
US-7,883,573 Method for preparing a source material for ion implantation
The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method...
US-7,883,219 System and method for displaying images
System and method for thin projection display systems. An embodiment comprises a light source, an array of light modulators optically coupled to the light...
US-7,882,625 Transfer mask in micro ball mounter
The objective of this invention is to provide a transfer mask that is able to accurately pass micro-balls onto terminal areas on a substrate. A thin plate...
US-7,879,642 Solid-state sensor and manufacturing method thereof
A sensor having photodiodes whose sensitivity and storage capacity can be increased is provided. The sensor is formed by arranging the photodiodes in an array...
US-7,877,658 IEEE 1149.1 and P1500 test interfaces combined circuits and processes
In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally...
US-7,877,654 Selectable JTAG or trace access with data store and output
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and...
US-7,877,653 Address and TMS gating circuitry for TAP control circuit
The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a...
US-7,877,651 Dual mode test access port method and apparatus
Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves...
US-7,877,650 Core circuit test architecture
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections....
US-7,877,536 Scalable distributed routing scheme for PCI express switches
A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first...
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