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Patent # Description
US-7,923,976 Fault protection circuit, method of operating a fault protection circuit and a voltage regulator employing the same
Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one...
US-7,921,465 Nanotip repair and characterization using field ion microscopy
A system (100) for characterizing surfaces can include a nanotip microscope (104) in a first pressure envelope (102) at a first pressure with an electrically...
US-7,920,708 Low computation mono to stereo conversion using intra-aural differences
A method of converting single channel audio (mono) signals to two channel audio (stereo) signals using simple filters and an Intra-aural Time Difference (ITD)...
US-7,920,535 Idle connection state power consumption reduction in a wireless local area network using beacon delay advertisement
A novel and useful apparatus for and method of improving idle connection state power consumption in wireless local area network (WLAN) system. Beacon...
US-7,920,404 Ferroelectric memory devices with partitioned platelines
One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in...
US-7,920,213 Method for maintaining the phase difference of a positioning mirror as a constant with respect to a high speed...
System and method for synchronizing the low speed mirror movement of a mirror display system with incoming frame or video signals, and synchronizing buffered...
US-7,920,081 Digital phase locked loop with dithering
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked...
US-7,920,020 System and method for auto-power gating synthesis for active leakage reduction
A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power...
US-7,920,015 Methods and apparatus to sense a PTAT reference in a fully isolated NPN-based bandgap reference
In a traditional, fully-isolated bandgap reference circuits, it was difficult to detect currents that are proportional to absolute temperature (PTAT). Here, a...
US-7,919,986 Power up biasing in a system having multiple input biasing modes
This invention is an input bias control for a module input. A clock detect circuit generates a signal indicating whether an external clock signal is detected....
US-7,919,958 Methods and apparatus for controlling a digital power supply
Methods and apparatus for controlling a digital power supply are disclosed. An example method includes storing a first set of coefficients for controlling a...
US-7,919,860 Semiconductor device having wafer level chip scale packaging substrate decoupling
One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the...
US-7,919,842 Structure and method for sealing cavity of micro-electro-mechanical device
A cavity package (100) for micrometer-scale MEMS devices surrounding the cavity (210) with the MEMS device (220) with a rim (232) of solder-wettable metal, and...
US-7,919,775 Semiconductor device and method comprising a high voltage reset driver and an isolated memory array
A method of operating a semiconductor device, a semiconductor device and a digital micromirror system are presented. In an embodiment, the semiconductor device...
US-7,919,368 Area-efficient electrically erasable programmable memory cell
Electrically erasable programmable "read-only" memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell...
US-7,918,563 System and method for utilizing a scanning beam to display an image
A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first...
US-7,918,018 Method of fabricating a semiconductor device
In a method and apparatus for fabricating a semiconductor device having a flexible tape substrate, a hole is punched in the flexible tape substrate. The...
US-7,917,824 Scan path adaptor with state machine, counter, and gate circuitry
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan...
US-7,917,822 Serial I/O using JTAG TCK and TMS signals
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus....
US-7,917,753 Transferring control between programs of different security levels
Systems and methods for transferring control between programs of different security levels are described herein. Some embodiments include a processor capable of...
US-7,916,824 Loop bandwidth enhancement technique for a digital PLL and a HF divider that enables this technique
A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first...
US-7,916,808 8PSK modulator
A modulation circuit uses pre-calculated and stored data to generate the modulated output. The modulator architecture uses pre-calculated, Gaussian filtered sine...
US-7,916,672 RF processor having internal calibration mode
The present invention pertains to a method of calibrating reception properties of a radio frequency (RF) processor. The application describes two embodiments of...
US-7,916,127 Method and circuitry for self testing of connectivity of touch screen panel
A touch screen digitizing system includes a first resistive screen and a touch screen controller including an ADC and self-test circuitry having a driver switch...
US-7,916,104 Increased intensity resolution for pulse-width modulation-based displays with light emitting diode illumination
A method for increasing intensity resolution (bit-depth) using LED illumination. A preferred embodiment comprises determining a display time for a bit to be...
US-7,916,058 Digital-to-analog converter (DAC) with reference-rotated DAC elements
In accordance with at least some embodiments, an electronic device comprises a digital-to-analog converter (DAC) having a DAC element array. Reference-rotated...
US-7,916,050 Time-interleaved-dual channel ADC with mismatch compensation
Previously, when designing receivers for radio frequency (RF) or wireless communications, designers chose between time-interleaved (TI) analog-to-digital...
US-7,915,905 Process and temperature insensitive flicker noise monitor circuit
In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit...
US-7,915,882 Start-up circuit and method for a self-biased zero-temperature-coefficient current reference
A current reference circuit is disclosed. A small startup current is defined as the base current into a bipolar transistor with its collector-emitter path...
US-7,915,087 Method of arranging dies in a wafer for easy inkless partial wafer process
In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle...
US-7,915,080 Bonding IC die to TSV wafers
A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that...
US-7,914,694 Semiconductor wafer handler
A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor...
US-7,914,151 Multi-function light modulators for optical systems
In one embodiment, a method includes transmitting one or more light beams by a first portion of a light modulator formed outwardly from a substrate. The one or...
US-7,913,135 Interconnections for plural and hierarchical P1500 test wrappers
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing...
US-7,911,679 Hinge design for enhanced optical performance for a digital micro-mirror device
An apparatus for use with a digital micro-mirror 100 includes a hinge 116 disposed outwardly from a substrate 102. The hinge 116 is capable of at least partially...
US-7,911,256 Dual integrator circuit for analog front end (AFE)
A circuit includes a generating circuit that generates a current signal in response to an input signal, a first one of a plurality of integrators that generates...
US-7,911,243 Driver with programmable power commensurate with data-rate
One embodiment of the invention includes a driver circuit. The driver circuit comprises an output transistor that is biased to provide an output signal in...
US-7,911,190 Regulator with automatic power output device detection
A switching regulator (20) including an on-chip power output function (24) and also an interface (26) to which off-chip power output devices (42PU, 42PD) may be...
US-7,910,936 N2 based plasma treatment for enhanced sidewall smoothing and pore sealing of porous low-k dielectric films
A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k...
US-7,910,918 Gated resonant tunneling diode
A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably...
US-7,910,477 Etch residue reduction by ash methodology
Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a...
US-7,910,471 Bumpless wafer scale device and board assembly
A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact...
US-7,910,422 Reducing gate CD bias in CMOS processing
A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a...
US-7,910,417 Distributed high voltage JFET
A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially...
US-7,910,289 Use of dual mask processing of different composition such as inorganic/organic to enable a single poly etch...
In accordance with the invention, there are methods of making an integrated circuit, an integrated circuit device, and a computer readable medium. A method can...
US-7,908,537 Boundary scan path method and system with functional and non-functional scan cell memories
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a...
US-7,908,535 Scan testable register file
Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test...
US-7,907,456 Memory having circuitry controlling the voltage differential between the word line and array supply voltage
An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also...
US-7,907,429 Circuit and method for a fully integrated switched-capacitor step-down power converter
A circuit and method for providing a fully integrated DC-DC converter using on-chip switched capacitors is disclosed. A switched capacitor matrix is coupled as a...
US-7,907,015 Circuit for compensation of leakage current-induced offset in a single-ended op-amp
An electronic device includes an operational amplifier, with the operational amplifier having an amplifier input stage coupled with a first output node to an...
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