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Patent # Description
US-7,824,824 Composite phase shifting lithography mask including etch stop layer
The formation of a lithographic mask (100) is disclosed, where the mask (100) can be used in forming integrated circuits onto a semiconductor substrate. A layer...
US-7,823,044 Method for streamlining error connection code computation while reading or programming a NAND flash memory
A method for streamlining error correction code computation while reading or programming a NAND flash memory. At least some of the illustrative embodiments are...
US-7,823,038 Connecting analog response to separate strobed comparator input on IC
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test....
US-7,823,037 Optimized JTAG interface
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
US-7,823,036 Low power testing of very large circuits
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...
US-7,822,996 Method for implementing thermal management in a processor and/or apparatus and/or system employing the same
A method for detecting temperature associated with a processor, results of the detecting being used for controlling power dissipation associated with the...
US-7,822,890 Bidirectional data repeater switch
A bidirectional repeater and data multiplexer for serial data has A-side 12C port devices A1-A4 coupled to comparators 302-308 and pull-downs to ground 316-322....
US-7,822,389 Methods and apparatus to provide an auxiliary receive path to support transmitter functions
Methods and apparatus to provide an auxiliary receive path to support transmitter functions are disclosed. An example transceiver includes an antenna and a...
US-7,822,146 System and method for digitally correcting a non-linear element
System and methods for a digital linearization of a non-linear element. Preferred embodiments provide digital predistortion methods and circuitry that addresses...
US-7,822,021 Systems, processes and integrated circuits for rate and/or diversity adaptation for packet communications
A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice...
US-7,822,011 Self-synchronized streaming architecture
Synchronization of downlink streaming data is performed by estimating the likelihood of an underflow or an overflow in an output buffer upon receipt of each...
US-7,821,843 Partial write-back in read and write-back of a memory
An integrated circuit having a functional memory and methods of operating and reducing an operating power of the integrated circuit are provided. The functional...
US-7,821,816 Method for constructing Shmoo plots for SRAMs
A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that...
US-7,821,491 LED driver circuit for a backlight device
A backlight device that is not affected by offset voltage. Driving transistor (41) operates such that current flows in LED circuit (11), and the detection...
US-7,821,333 High-voltage differential amplifier and method using low voltage amplifier and dynamic voltage selection
A differential amplifier (1D) includes circuitry (5,R1,R2,52) coupling a common mode component of an input voltage (Vin.sup.+-Vin.sup.-) to a maximum voltage...
US-7,821,328 Dynamic charge pump system for front end protection circuit
Various apparatuses, methods and systems for a front end protection circuit with a dynamic charge pump system are disclosed herein. For example, some embodiments...
US-7,821,307 Bandgap referenced power on reset (POR) circuit with improved area and power performance
In an apparatus for monitoring a supply voltage, a current mirror coupled to the supply voltage provides a pair of matching currents. A resistor divider that...
US-7,821,113 Leadframe having delamination resistant die pad
A lead frame (410) including a die pad (100) for mounting at least one integrated circuit (405) thereon and a plurality of lead fingers (413). The die pad (100)...
US-7,821,111 Semiconductor device having grooved leads to confine solder wicking
A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes...
US-7,820,924 Multi-direction switch for a cursor device
A directional controller for a device is provided. The directional controller consists of keypad contacts, a keyboard, and a button. The keypad contacts are on a...
US-7,820,063 Micromirror device and a method of making the same
A reflective and deformable micromirror device comprises a reflective micromirror plate attached to a deformable hinge that is formed on and held by a hinge post...
US-7,818,711 System and method for making photomasks
The present application is directed a method for determining the position of photomask patterns in a mask making process. The method comprises providing one or...
US-7,818,641 Interface to full and reduce pin JTAG devices
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced...
US-7,818,604 Pipelined clock stretching circuitry and method for I2C logic system
A system for increasing the data throughput of an I2C bus including a serial clock conductor (3) for conducting a serial clock signal (SCK) and a serial data...
US-7,818,468 Method and system for processing control information
In one aspect, an integrated circuit device including a first-level module configurable to receive and transmit control information, said first level module...
US-7,817,747 Precise delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter
A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides...
US-7,817,736 Correcting for carrier frequency offset in multi-carrier communication systems
A multi-carrier (MC) receiver receives a multi-carrier signal containing data symbols as well as pilot symbols. The MC receiver estimates a carrier frequency...
US-7,817,490 Low-power operation of static memory in a read-only mode
A static random access memory (SRAM) operable that is biased at lower power supply voltages in a read-only mode than in a read/write mode. The SRAM can be...
US-7,817,393 Power distribution switch circuits with fast responses to hard short-circuits
Methods and apparatus to provide power distribution switch circuits with fast responses to hard short-circuits are disclosed. In one example, a power...
US-7,817,341 Integrated TIR prism and lens element
Disclosed is an optical component, which comprises a prism element adjacent to a lens element, where the two elements are separated by a small air gap. In...
US-7,817,323 Optical structure and an imaging system using the same
An optical architecture comprises an optical scanning mechanism for use in imaging systems. With the optical scanning mechanism, illumination light from an...
US-7,816,740 Memory cell layout structure with outer bitline
An integrated circuit (IC) includes a memory cell having source/drain regions for defining source/drains of a first pull-up or pull-down (PU/PD) transistor for a...
US-7,815,738 Deposition tool cleaning process having a moving plasma zone
The present invention provides, in one embodiment, a process for cleaning a deposition chamber (100). The process includes a step (100) of forming a reactive...
US-RE41,830 Oversampling analog-to-digital converter and method with reduced chopping residue noise
A delta-sigma modulator includes a chopper-stabilized integrator, a quantizer having an input coupled to an output of the integrator, an input signal acquiring...
US-7,814,478 Methods and apparatus for use in updating application programs in memory of a network device
An illustrative method of the present application is for use in updating an application program in memory of a network device. An application program having a...
US-7,814,450 Active skew control of a digital phase-lock loop using delay lock-loops
Systems and methods for transmitting a signal having a desired phase at the device are disclosed. The systems and methods further include determining a signal...
US-7,814,386 Built in self test for input/output characterization
A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage...
US-7,814,258 PCI bus burst transfer sizing
Various apparatuses, methods and systems for specifying memory transaction sizes on a PCI bus are disclosed herein. For example, some embodiments of the present...
US-7,813,601 Reconfigurable optical add/drop multiplexer
Disclosed is an add-drop multiplexer that receives an optical signal having a plurality of channels. The multiplexer spatially separates the channels, and a...
US-7,813,567 Method of CABAC significance MAP decoding suitable for use on VLIW data processors
This invention decodes a next significance symbol using a selected context. The invention operates in a loop for each symbol decode for a whole block until the...
US-7,813,462 Method of defining semiconductor fabrication process utilizing transistor inverter delay period
A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on...
US-7,813,198 System and method for reading memory
One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to...
US-7,813,193 Ferroelectric memory brake for screening and repairing bits
A method (300) of identifying failing bits in a ferroelectric memory device including at least one ferroelectric capacitor includes (302) writing same state data...
US-7,813,177 Analog single-poly EEPROM incorporating two tunneling regions for programming the memory device
A single-poly EEPROM memory device comprises a control gate isolated within a well of a first conductivity type in a semiconductor body of a second conductivity...
US-7,813,068 Degauss control for magnetic disk-drive preamplifier
One embodiment of the invention includes a preamplifier system for a magnetic disk-drive. The system includes a current distributor configured to generate a...
US-7,812,830 Touch-initiated power-saving clock system and method for touch screen controller
A touch screen controller circuit (1A) including means for generating a first and second levels of a pen touch signal (PENTOUCH) if a touch point (Q) is present...
US-7,812,649 Low power, power on reset circuit with accurate supply voltage detection
The power on reset circuit includes: a comparator; a resistor string having a first end coupled to a first supply node of the comparator, a first tap point node...
US-7,812,646 Low-leakage switch for sample and hold
An integrated electronic device includes a sample and hold stage. The sample and hold stage has a sampling capacitor (C) for an input voltage at an input node...
US-7,812,401 MOS device and process having low resistance silicide interface using additional source/drain implant
An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source...
US-7,811,942 Tri-layer plasma etch resist rework
Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch...
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