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Patent # Description
US-7,843,246 Clamp control circuit having current feedback
In accordance with an aspect of the present invention, an external FET driving circuit includes a driving portion, a drain-to-gate clamp portion and a current...
US-7,843,207 Methods and apparatus to test electronic devices
Methods and apparatus to test electronic devices are disclosed. An example method includes setting a first controlled switch to prevent a current detect signal...
US-7,843,183 Real time clock (RTC) voltage regulator and method of regulating an RTC voltage
A real time clock (RTC) voltage regulator, a method of regulating an RTC voltage and a power management integrated circuit (PMIC). In one embodiment, an RTC...
US-7,843,150 Power regulation for LED strings
One embodiment of the invention includes a power regulator system. The system comprises at least one current regulator configured to maintain a substantially...
US-7,842,955 Carbon nanotube transistors on a silicon or SOI substrate
A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically...
US-7,842,949 IC with comparator receiving expected and mask data from pads
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the...
US-7,842,567 Dual work function CMOS devices utilizing carbide based electrodes
Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low...
US-7,840,932 Defocus determination method using sub-resolution feature (SRF) printing
The present application is directed to apparatus and methods for determining a magnitude of defocus and a direction of defocus for a photolithography process. A...
US-7,840,827 Display power management
An apparatus and method for power management of a display system. A display controller couples to a memory storage device. A frame buffer in the memory storage...
US-7,840,784 Test and skip processor instruction having at least one register operand
A processor may execute a test and skip instruction that includes or otherwise specifies at least two operands that are used in a comparison operation. Based on...
US-7,840,782 Mixed stack-based RISC processor
A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based...
US-7,840,302 Methods of analyzing integrated circuit equivalency and manufacturing an integrated circuit
Methods of analyzing equivalency with respect to split and limited release lots of wafers of integrated circuits. One embodiment of the split-lot method...
US-7,840,239 Distributed power management
A power management bus for controlling power over multiple device subsystems includes a master power bus controller which transmits power management information...
US-7,839,762 Method and apparatus for vector based walsh code bit sequence generation
A vector-based Walsh code sequence generator provides for a general architecture that can be easily adapted to any random length sequence and any random number...
US-7,839,670 F-RAM device with current mirror sense amp
A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator....
US-7,839,589 Write current waveform asymmetry compensation
A write current circuit (300, 400) adapted to drive a thin film write head (202) of a mass media information storage device. The write current circuit (300, 400)...
US-7,839,560 Packaged spatial light modulator and a display system using the same
A spatial light modulator comprises an array of individually addressable pixels enclosed within a space formed by a package lid and a package substrate. An...
US-7,839,316 Chopping technique for continuous time sigma-delta ADCs without Q-noise folding
A chopping transconductor includes an transconductor input stage coupled with input signals of the chopping transconductor; a chopping switch coupled with an...
US-7,839,155 Methods and apparatus to analyze on-chip controlled integrated circuits
Methods and apparatus for analyzing an integrated circuit are disclosed. An example method includes supplying power to an on-chip supply power regulator of...
US-7,838,988 Stud bumps as local heat sinks during transient power operations
A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding...
US-7,838,924 MOS device with substrate potential elevation
An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the...
US-7,838,429 Method to manufacture a thin film resistor
A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material...
US-7,838,376 Non-destructive inline epi pattern shift monitor using selective epi
Integrated circuits using buried layers under epitaxial layers present a challenge in aligning patterns for surface components to the buried layers, because the...
US-7,838,370 Highly selective liners for semiconductor fabrication
A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The...
US-7,838,356 Gate dielectric first replacement gate processes and integrated circuits therefrom
A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the...
US-7,835,574 System and method to generate multiprimary signals
System and method for generating multiprimary signals for use in display devices. A preferred embodiment comprises converting a color signal into an intermediate...
US-7,835,535 Virtualizer with cross-talk cancellation and reverb
Audio loudspeaker and headphone virtualizers and cross-talk cancellers and methods use separate virtual speaker locations for different Bark frequency bands and...
US-7,835,391 Protocol DMA engine
Apparatus and method for accelerating data handling in the protocol stack of a networked device. Embodiments of the disclosed invention may be used to increase...
US-7,835,262 Multi-band OFDM communications system
System and method for providing multiple access in a multi-band, orthogonal frequency division multiplexed (multi-band-OFDM) communications system. A preferred...
US-7,835,098 Automatic gain control for magnetic disk-drive preamplifier
One embodiment of the invention includes a preamplifier system for a magnetic disk-drive. The system comprises a read amplifier configured to generate a read...
US-7,835,054 Optical architecture having a rotating polygon for use in imaging systems
An optical architecture comprises a refractive cylinder that is movable relative to the incident light. By moving the refractive cylinder, the output light from...
US-7,834,703 Amplifier with single-ended input and differential output
An amplifier provided according to an aspect of the present invention includes a set of passive impedances forming a tuned load to a gain stage and also to...
US-7,834,686 Power amplifier
Methods to implement power control in a digital power amplifier are described.
US-7,834,636 Methods and apparatus to facilitate ground fault detection with a single coil
A ground fault detection device includes a sense coil including a primary winding and a secondary winding to detect current in a line conductor and a neutral...
US-7,834,615 Bist DDR memory interface circuit and method for self-testing the same using phase relationship between a data...
An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a...
US-7,834,608 Feed-forward compensation for a hysteretic switching regulator
One embodiment of the invention includes a hysteretic power regulator system. The system includes a switching stage configured to periodically couple an input...
US-7,833,895 TSVS having chemically exposed TSV tips for integrated circuit devices
A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate...
US-7,832,870 Projection system using reflected light from a color wheel
According to one embodiment, a projection system includes a color wheel operable to filter light into a passed component and a reflected component. The...
US-7,831,878 Integrated circuit with JTAG port, tap linking module, and off-chip tap interface port
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP...
US-7,831,875 Interconnections for plural and hierarchical P1500 test wrappers
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing...
US-7,830,906 Variable time division multiplex transmission system
A time division multiplex transmission system transmits information on multiple channels by using a transmission path with variable time division multiplexing....
US-7,830,765 Methods and apparatus to monitor and control hard-disk head position
Methods and apparatus to monitor and control hard-disk drive head position are described. In one example, a hard-disk drive system includes a hard-disk drive...
US-7,830,183 Comparator with reduced power consumption
A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected...
US-7,829,430 Methods for preparing and devices with treated dummy moats
Devices and methods are presented to fabricate dummy moats in an isolation region on a substrate. Presently, dummy moats are prone to losing impedance after the...
US-7,829,405 Lateral bipolar transistor with compensated well regions
Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar...
US-7,829,389 Roll-on encapsulation method for semiconductor packages
A low-viscosity resin is deposited using an apparatus with a movable and heatable wheel and a heater stage. A tape is provided, which includes a layer (140) of...
US-7,827,453 Core test circuits controlling boundary and general external scan circuits
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test...
US-7,827,342 Readback registers
A method reading bank register values is provided. Register values are stored in a readback bank. The register values are output sequentially from the serial...
US-7,827,225 Methods and systems for a multi-channel Fast Fourier Transform (FFT)
In at least some embodiments, a method is provided. The method includes receiving samples from a first input channel and a second input channel. The method...
US-7,826,572 Dynamic optimization of overlap-and-add length
A method of adjusting overlap-and-add length for zero-padded suffixes. The method includes, based on a channel impulse response, estimating an effective channel...
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