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Behavior of trace in non-emulatable code
Code will switch to secure code via an exception only. All PC and data trace will be turned off during secure code. This will occur regardless of trace being in...
Method for generating timing data packet
During a trace the timing stream has the active and stall information, PC stream has all the discontinuity information, and the data stream has all the data log...
Compressor/decompressor circuits coupled with TDO-TMS/TDI die channel
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
Scalable multi-threaded sequencing/synchronizing processor architecture
A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared...
Flexible connection scheme between multiple masters and slaves
The present invention describes a flexible routing scheme between masters and slaves in complex digital systems. The routing scheme is optimized for maximum...
Parallel architecture for matrix transposition
An extension to current multiple memory bank video processing architecture is presented. A more powerful memory controller is incorporated, allowing computation...
Automute detection in digital audio amplifiers
A digital audio processor for a digital audio receiver having an improved automute sequence is disclosed. The digital audio processor includes automute detection...
Post-processing technique for noise reduction of DCT-based compressed
A new post-processing methodology reduces the unwanted noise artifacts present in the output images of DCT-based compressed signals. The method determines noise...
3D graphics rendering includes texture compression including joint compression of related textures by using one texture to predict the other, object-based...
High speed, symmetrical prescaler
Over the years, ring counter and prescalers have been used in a variety of microelectronic applications, including Phased Locked Loops or PLLs. All of these...
Eliminating narrowband interference in a receiver
A wireless device receives an input signal representing a signal of interest (e.g., one or more portions of a packet) on a wireless medium. The input signal may,...
System and method for providing additional channels to an existing
System and method for providing additional channels to an existing communications system. A preferred embodiment comprises a coprocessor (such as coprocessor...
Multi-carrier reception for ultra-wideband (UWB) systems
System and method for receiving transmissions in a wireless communications system. A preferred embodiment comprises a receiver (such as receiver 400) that can...
Methods and apparatus to perform dynamic channel management and dynamic
bandwidth changes in wireless local...
Methods and apparatus to perform dynamic channel management and dynamic bandwidth changes in wireless local area networks are disclosed. A disclosed example...
High speed high resolution ADC using successive approximation technique
An analog to digital converter (ADC) containing a sub-ADC to resolve at least some of the bits using successive approximation principle (SAP), while providing...
System and method for common mode translation
System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC...
Circuits and methods to minimize nonlinearity errors in interpolating
Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein. A disclosed example circuit comprises first and second...
Reduction of dead-time distortion in class D amplifiers
Pulse-width-modulating class D amplifier with an H-bridge output stage, and method of operating the same. in which output stage dead-time is compensated. Offset...
Minimizing changes in common mode voltage at inputs of an operational
amplifier used in a switched capacitor...
A reference generation circuit provided according to an aspect of the present invention generates a reference potential at different levels in the hold phase of...
Multi format video filter design
Current generation digital media processors support multi-format video resolutions, SDTV, Progressive Scan and HDTV. Built-in video encoders directly support...
Integrated circuit device and layout design method therefor
An integrated circuit device has multiple first circuit elements arranged in a first area. A signal distribution circuit that has multiple drive circuits is...
Adjusting output buffer timing based on drive strength
This invention operates to select a drive code for an adjustable drive strength transistor in a drive buffer. The drive code is determined employing a...
Antimony ion implantation for semiconductor components
A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating...
Semiconductor device manufactured by removing sidewalls during replacement
gate integration scheme
One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor...
Intentional pocket shadowing to compensate for the effects of
cross-diffusion in SRAMs
Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning...
Structure and method of high performance two layer ball grid array
A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an...
Semiconductor device including an amorphous nitrided silicon adhesion
layer and method of manufacture therefor
Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a...
System and method for increasing the extent of built-in self-testing of
memory and circuitry
An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one...
TAP domain selection circuit with selected TDI/TDO or TDO lead
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
Cell supporting scan-based tests and with reduced time delay in functional
A memory cell supporting scan-based tests and with reduced time delay in functional mode. The memory cell generates separate clocks for latching functional and...
Zero-bit scans defining command window and control level
A method comprises performing at least one zero-bit scan across an interface. The at least one zero-bit scan defines a command window. Further, the method...
Adaptive voltage scaling with age compensation
One embodiment of the present invention includes an adaptive voltage scaling system associated with an integrated circuit (IC). The system comprises at least one...
Apparatus for and method of automatic radio link establishment
A novel and useful mechanism for automatically establishing a radio link between a communications device and a commercially available FM radio receiver, thereby...
SEU hardening circuit and method
An SEU hardening circuit and method is disclosed. In one embodiment, a method includes providing a semiconductor memory component having a pair of pMOS...
Semiconductor manufacturing peripheral verification tool
Apparatus and methods for verification of the dimensions of a semiconductor manufacturing peripheral are disclosed, in which the peripheral, e.g., a wafer...
Flicker noise reduction in continuous time (CT) sigma delta modulators
Embodiments of a system for processing a signal may include a receiver configured to receive an input analog signal and an up converter coupled with the receiver...
Technique for improving antialiasing and adjacent channel interference
filtering using cascaded passive IIR...
A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and...
A square-function circuit includes an input field-effect transistor (FET) having a gate that is driven by an input voltage and is configured to conduct an output...
AC-powered, microprocessor-based, dimming LED power supply
A dimmable, light-emitting diode (LED) power supply adapted to provide a direct current (DC), constant current ("constant current source") from a conventional,...
Solder cap application process on copper bump using solder powder film
A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post,...
Gate sidewall spacer and method of manufacture therefor
The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit...
Method of achieving dense-pitch interconnect patterning in integrated
Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal...
Method for fine-pitch, low stress flip-chip interconnect
Attaching a semiconductor chip to a substrate by applying mechanical vibrations (150) to a polymeric compound (130) and the contacting areas (114, 124) of a...
Semiconductor die collet and method
Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of...
Method for fabricating a leadframe
A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (402) and a plurality of...
Method for guaranteeing timing precision for randomly arriving
The timing stream is used to capture pipeline advances and to record stall cycles. Timing streams may be in standard or compressed formats. The stalls are traced...
Displaying cache information using mark-up techniques
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
Test access mechanisms, associated controllers and a selector
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE...
Event and stall selection
A method comprising generating status signals comprising stall and event information associated with a hardware system. The method also comprises multiplexing...
Method for measuring utilization of a power managed CPU
An extremely low overhead method calculates CPU load in the presence of both CPU idling and frequency scaling. The method measures time the CPU is idled while...