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Patent # Description
US-7,897,447 Use of in-situ HCL etch to eliminate by oxidation recrystallization border defects generated during solid phase...
A method for reducing defects at an interface between a amorphized, recrystallized cleaved wafer layer and an unamorphized cleaved wafer layer can comprise an...
US-7,897,410 Close proximity scanning surface contamination analyzer
Reducing chemical contaminants is increasingly important for maintaining competitive production costs during fabrication of electronic devices. There is...
US-7,895,554 Verification method with the implementation of well voltage pseudo diodes
A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a...
US-7,895,551 Generation of standard cell library components with increased signal routing resources
Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed....
US-7,895,489 Matrix system and method for debugging scan structure
An aspect of the present invention is drawn to a system that includes an automatic test engine, a decompressor, a first scan chain, a second scan chain, a...
US-7,894,864 Estimation of power level in a communication device
A system comprising a first communication device and a second communication device adapted to determine a property of communications between the first and second...
US-7,894,787 Method and system for controlling carrier leakage in a direct conversion wireless device
A system for controlling carrier leakage in a communications device includes a first mixer unit operable to receive and convert a first signal into a second...
US-7,894,685 Method and apparatus for reducing ringing artifacts
A method and apparatus for ringing artifacts reduction for compressed video signals. The method includes receiving luma data to the digital signal processor,...
US-7,894,536 Calibration model to mitigate data conversion errors
An error model can be utilized to mitigate errors associated with a conversion system, such as an analog-to-digital or digital-to analog converter. The error...
US-7,894,517 Self-calibrated adaptive equalization system and methods of performing the same
A self-calibrating, adaptive equalization system for generating an ideal digital signal is disclosed. The adaptive equalization system includes an equalizer and...
US-7,894,503 System and method of flexible channel allocation in an ultra wideband (UWB) frequency hopping communication system
A system and method of flexible channel allocation in an ultra wideband frequency hopping communication system is disclosed. In one embodiment, a method includes...
US-7,894,491 Data transfer circuit
A data transfer circuit is provided for sending digital data at high rates across short but significant distances within an integrated circuit. The data is sent...
US-7,894,284 Ferroelectric memory bake for screening and repairing bits
A method (300) of identifying failing bits in a ferroelectric memory device including at least one ferroelectric capacitor includes (302) writing same state data...
US-7,894,280 Asymmetrical SRAM cell with separate word lines
An integrated circuit includes a memory array having a plurality of SRAM memory cells arranged in a plurality of rows and columns, the array also having a...
US-7,894,235 F-RAM device with current mirror sense amp
A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator....
US-7,894,234 F-SRAM before package solid data write
A process of polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation and...
US-7,894,226 Content addressable memory based on a ripple search scheme
A scheme for ultra-low power content addressable memory based on a ripple search is disclosed. In one embodiment, a system for content addressable memory (CAM),...
US-7,894,121 Light valve assembly with a holographic optical element and a method of making the same
A light valve assembly comprises a holographic optical element and a light valve that comprises an array of individually addressable pixels. The light valve...
US-7,893,945 Color mapping techniques for color imaging devices
Disclosed embodiments relate to techniques for color gamut mapping when an input signal transmitting color visual images has a different color gamut than does...
US-7,893,768 Automatic gain control
A method and system for providing automatic gain control for a differential amplifier are provided. An impedance network is set to have a first impedance that...
US-7,893,765 Current canceling variable gain amplifier and transmitter using same
A current canceling CMOS variable gain amplifier includes a first leg and a second leg. The first leg has a first input line, a first output line, a first ON...
US-7,893,746 High speed intra-pair de-skew circuit
For differential signal transmission (especially in high speed applications), intra-pair skew between paths carrying complementary portions of a differential...
US-7,893,734 Power-on reset circuit
An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a...
US-7,893,723 Minimizing leakage in logic designs
Devices and methods are disclosed for logic gate devices to provide reduced leakage while improving performance. The device is configured for low leakage logic...
US-7,893,720 Bus low voltage differential signaling (BLVDS) circuit
A differential signaling circuit and a control circuit. The differential signaling circuit includes a first positive driver and a first negative driver. The...
US-7,893,675 Current mode controlled DC-to-DC converter
An apparatus having an input voltage and an output voltage is provided. The apparatus comprises a switch that receives the input voltage and that is adapted to...
US-7,893,672 Technique to improve dropout in low-dropout regulators by drive adjustment
An electronic device includes a low drop-out regulator for providing a regulated output voltage. The low drop-out regulator generally comprises a power MOSFET...
US-7,893,671 Regulator with improved load regulation
A regulator to provide an output voltage of a constant level at an output node. In an embodiment, the regulator contains a pass transistor to provide a...
US-7,893,544 Semiconductor device having improved contacts
A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across...
US-7,893,499 MOS transistor with gate trench adjacent to drain extension field insulation
An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source...
US-7,892,957 Gate CD trimming beyond photolithography
A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a...
US-7,892,931 Use of a single mask during the formation of a transistor's drain extension and recessed strained epi regions
A method 300 for forming a transistor's drain extension 70 and recessed strained epi regions 150 with a single mask step 306. In an example embodiment, the...
US-7,892,930 Method to improve transistor tox using SI recessing with no additional masking steps
A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure...
US-7,892,908 Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon...
Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as...
US-7,892,906 Method for forming CMOS transistors having FUSI gate electrodes and targeted work functions
A method for making CMOS transistors that includes forming a NMOS transistor and a PMOS transistor having an undoped polysilicon gate electrode and a hardmask....
US-7,892,889 Array-processed stacked semiconductor packages
One embodiment of the invention is a semiconductor system (1400) of arrays (1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate...
US-7,891,937 Adjustable width cassette for wafer film frames
An expandable width cassette for storing and transporting thin planar objects of different widths is provided. The cassette 10 includes two side panels 12 of...
US-7,890,914 Layout data reduction for use with electronic design automation tools
A system and method which stores a three dimensional physical representation of an electrical circuit such as an integrated circuit design uses a database having...
US-7,890,912 Treatment of trim photomask data for alternating phase shift lithography
In accordance with the invention, there is a method of designing a lithography mask. The method can comprise generating initial phase photomask data and initial...
US-7,890,829 Reduced signaling interface method and apparatus
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,890,825 Data summing boundary cell
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one...
US-7,890,753 Secure mode for processors supporting MMU and interrupts
A digital system is provided with a secure mode (3.sup.rd level of privilege) built in a non-invasive way on a processor system that includes a processor core,...
US-7,890,735 Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0,...
US-7,890,566 Microprocessor with rounding dot product instruction
A functional unit in a digital system is provided with a rounding DOT product instruction, wherein a product of first pair of elements is combined with a product...
US-7,890,335 Sharing wavelet domain components among encoded signals
A system for sharing wavelet domain components among encoded signals receives a set of signals decomposed and encoded according to a wavelet transform. The...
US-7,890,316 Synchronizing on-chip data processor trace and timing information for export
Emulation information indicative of internal operations of a data processor can be provided for use by an apparatus external to the data processor. A stream of...
US-7,889,807 Scalable VLSI architecture for K-best breadth-first decoding
In some embodiments, a device includes a multiple-input multiple-output ("MIMO") decoder module coupled to a first log-likelihood-ratio ("LLR") computing unit....
US-7,889,737 Locally administered MAC address based method for selectively and efficiently identifying enhanced version...
Embodiments of the invention provide a method for selectively identifying nodes implemented enhanced version of a standard by creating a random locally...
US-7,889,635 Versatile system for dual carrier transformation in orthogonal frequency division multiplexing
The present invention provides a versatile system for selectively spreading carrier data across multiple carrier paths within an Orthogonal Frequency Division...
US-7,889,535 F-SRAM margin screen
A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to...
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