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Patent # Description
US-7,795,958 Minimizing changes in common mode voltage at inputs of an operational amplifier used in a switched capacitor...
A reference generation circuit provided according to an aspect of the present invention generates a reference potential at different levels in the hold phase of...
US-7,795,956 Multi format video filter design
Current generation digital media processors support multi-format video resolutions, SDTV, Progressive Scan and HDTV. Built-in video encoders directly support...
US-7,795,943 Integrated circuit device and layout design method therefor
An integrated circuit device has multiple first circuit elements arranged in a first area. A signal distribution circuit that has multiple drive circuits is...
US-7,795,918 Adjusting output buffer timing based on drive strength
This invention operates to select a drive code for an adjustable drive strength transistor in a drive buffer. The drive code is determined employing a...
US-7,795,122 Antimony ion implantation for semiconductor components
A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating...
US-7,795,097 Semiconductor device manufactured by removing sidewalls during replacement gate integration scheme
One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor...
US-7,795,085 Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs
Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning...
US-7,795,072 Structure and method of high performance two layer ball grid array substrate
A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an...
US-7,795,070 Semiconductor device including an amorphous nitrided silicon adhesion layer and method of manufacture therefor
Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a...
US-7,793,186 System and method for increasing the extent of built-in self-testing of memory and circuitry
An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one...
US-7,793,182 TAP domain selection circuit with selected TDI/TDO or TDO lead
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,793,178 Cell supporting scan-based tests and with reduced time delay in functional mode
A memory cell supporting scan-based tests and with reduced time delay in functional mode. The memory cell generates separate clocks for latching functional and...
US-7,793,152 Zero-bit scans defining command window and control level
A method comprises performing at least one zero-bit scan across an interface. The at least one zero-bit scan defines a command window. Further, the method...
US-7,793,119 Adaptive voltage scaling with age compensation
One embodiment of the present invention includes an adaptive voltage scaling system associated with an integrated circuit (IC). The system comprises at least one...
US-7,792,498 Apparatus for and method of automatic radio link establishment
A novel and useful mechanism for automatically establishing a radio link between a communications device and a commercially available FM radio receiver, thereby...
US-7,791,926 SEU hardening circuit and method
An SEU hardening circuit and method is disclosed. In one embodiment, a method includes providing a semiconductor memory component having a pair of pMOS...
US-7,791,720 Semiconductor manufacturing peripheral verification tool
Apparatus and methods for verification of the dimensions of a semiconductor manufacturing peripheral are disclosed, in which the peripheral, e.g., a wafer...
US-7,791,518 Flicker noise reduction in continuous time (CT) sigma delta modulators (SDMS)
Embodiments of a system for processing a signal may include a receiver configured to receive an input analog signal and an up converter coupled with the receiver...
US-7,791,407 Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR...
A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and...
US-7,791,400 Square-function circuit
A square-function circuit includes an input field-effect transistor (FET) having a gate that is driven by an input voltage and is configured to conduct an output...
US-7,791,326 AC-powered, microprocessor-based, dimming LED power supply
A dimmable, light-emitting diode (LED) power supply adapted to provide a direct current (DC), constant current ("constant current source") from a conventional,...
US-7,790,597 Solder cap application process on copper bump using solder powder film
A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post,...
US-7,790,561 Gate sidewall spacer and method of manufacture therefor
The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit...
US-7,790,525 Method of achieving dense-pitch interconnect patterning in integrated circuits
Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal...
US-7,790,509 Method for fine-pitch, low stress flip-chip interconnect
Attaching a semiconductor chip to a substrate by applying mechanical vibrations (150) to a polymeric compound (130) and the contacting areas (114, 124) of a...
US-7,790,507 Semiconductor die collet and method
Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of...
US-7,788,800 Method for fabricating a leadframe
A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (402) and a plurality of...
US-7,788,645 Method for guaranteeing timing precision for randomly arriving asynchronous events
The timing stream is used to capture pipeline advances and to record stall cycles. Timing streams may be in standard or compressed formats. The stalls are traced...
US-7,788,642 Displaying cache information using mark-up techniques
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
US-7,788,559 Test access mechanisms, associated controllers and a selector
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE...
US-7,788,538 Event and stall selection
A method comprising generating status signals comprising stall and event information associated with a hardware system. The method also comprises multiplexing...
US-7,788,511 Method for measuring utilization of a power managed CPU
An extremely low overhead method calculates CPU load in the presence of both CPU idling and frequency scaling. The method measures time the CPU is idled while...
US-7,788,422 Interface and interrupt circuitry coupling data to host DMA circuitry
A method includes generating a transfer configuration descriptor ("TCD"), the TCD includes information pertaining to data to be transferred. The method further...
US-7,788,091 Methods, devices and systems for improved pitch enhancement and autocorrelation in voice codecs
An electronic circuit includes a storage circuit and a microprocessor operable together with the storage circuit as a speech coder. The speech coder has a...
US-7,787,630 FM stereo decoder incorporating Costas loop pilot to stereo component phase correction
A novel system and method for correcting the residual phase offset between a recovered pilot signal and the received stereo signal. The invention uses a Costas...
US-7,787,563 Transmitter for wireless applications incorporation spectral emission shaping sigma delta modulator
A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of...
US-7,787,560 Smart antenna interface using only digital I/O supporting both mode A and mode B antenna operation as per CEA...
This invention samples and transmits the CEA-909 standard smart antenna analog pulse train waveforms using only a digital I/O pin for both mode A and mode B...
US-7,787,558 Rapid re-synchronization of communication channels
A method of synchronizing a receiver with a transmitter. The method includes determining number of bits, j, for adjusting a bit stream, where the bit stream is...
US-7,787,550 Combined frame alignment and timing recovery in digital subscriber line (DSL) communications systems
Timing recovery circuitry for a digital subscriber line (DSL) modem, including a combined frame and timing function for adjusting frame alignment, and for...
US-7,787,541 Dynamic pre-filter control with subjective noise detector for video compression
Pre filtering is commonly used in video encoding to remove undesirable noise from video sources. Without a pre filter, the noise degrades the performance of a...
US-7,787,499 Maintaining synchronization of multiple data channels with a common clock signal
Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g.,...
US-7,787,369 Flexible Ethernet bridge
Congestion is minimized on a desired port in an Ethernet bridge. A packet with a destination address and a source address is received on an incoming port. An...
US-7,787,263 Methods and apparatus to control a digital power supply
Methods and apparatus to control a digital power supply are disclosed. An example method includes controlling a power factor controller by: receiving a first...
US-7,787,170 Micromirror array assembly with in-array pillars
The present invention provides a microstructure device comprising multiple substrates with the components of the device formed on the substrates. In order to...
US-7,787,021 Programmable architecture for flexible camera image pipe processing
This invention is a programmable image pipe processing architecture that offers full software flexibility to implement latest and greatest algorithms at fully...
US-7,786,920 Method and device for controlling a successive approximation register analog to digital converter
A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator...
US-7,786,915 Adaptive digital audio pre-distortion in an audio digital to analog converter
An adaptive digital pre-distortion block is used to cancel device nonlinearities to improve the overall linearity of a Delta-Sigma DAC system. In particular, the...
US-7,786,913 Digital phase locked loop with dithering
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked...
US-7,786,909 Analog to digital converter with improved input overload recovery
With high speed analog to digital converters (ADCs), components within the ADC can enter a saturation region when an input exceeded the input range of the ADC,...
US-7,786,758 Asynchronous clock gate with glitch protection
A tristate buffer circuit includes a tristate buffer switchable into a high impedance state in response to configuration signal, a delay stage delays the an...
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