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Patent # Description
US-7,778,813 Video coding quantization
Modify H.263-type quantization with an adaptive quantization parameter floor; this limits clipping of quantized DCT coefficients and consequent artifacts. The...
US-7,778,610 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using XOR operation with jitter...
A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF...
US-7,778,494 FIR-based interpolation in advanced video codecs on VLIW processor
A half sample and quarter sample pixel value interpolation calculation classifies a set of all possible half sample and quarter sample pixel value interpolation...
US-7,778,408 Method and apparatus for acoustic echo cancellation utilizing dual filters
Hands-free phones with echo cancellation using dual filters, one fast adapting filter and one slow adapting filter; the choice of filters includes switching with...
US-7,778,361 Feed forward method for NICAM decode
A method and apparatus for decoding digital quadrature phase shift keying data includes converting and intermediate frequency signal from an analog signal to a...
US-7,778,355 Space-time transmit diversity
A linear transformation of parallel space-time transmit diversity encoded streams; also, asymmetrical symbol mapping of parallel streams. Separately or together,...
US-7,778,345 Distortion compensation in a communication system
In one embodiment of the invention, a modulator mixes a transmit-path signal based on a local oscillator (LO) signal and an amplifier amplifies the mixed...
US-7,778,327 H.264 quantization
Low complexity (16 bit arithmetic) H.264 video compression replaces a single quantization table for all quantization parameters with multiple quantization tables...
US-7,778,314 Apparatus for and method of far-end crosstalk (FEXT) detection and estimation
A novel and useful mechanism for the detection and estimation of far-end cross talk (FEXT) caused by transmissions over adjacent wire pairs or cables. The...
US-7,778,151 Efficient scheduling request channel for wireless networks
In a method for transmitting a contention free scheduling request in a cellular network, a set of N frequency opportunities is defined within a scheduling...
US-7,777,744 Systems and methods for multiple equation graphing
Various systems and methods for equation graphing are disclosed herein. For example, some embodiments of the present invention provide methods for graphing...
US-7,777,702 System and method for driving solid-state light sources
System and method for driving solid-state light sources utilizing saturation mode current drivers. A preferred embodiment comprises charging a first drive...
US-7,777,655 Wideband switched current source
Traditionally, constant current source circuits (and, in particular, constant current source circuits that include cascoded current sources) had numerous...
US-7,777,577 Dual path phase locked loop (PLL) with digitally programmable damping
In a method and apparatus for controlling damping and bandwidth in a phase locked loop (PLL), a loop filter is configured to have a dual path for charge pump...
US-7,777,576 Digital phase locked loop with gear shifting
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked...
US-7,777,574 Closed loop ramp up for pop and click reduction in an amplifier
To reduce pop or click during turn-on, a method and apparatus are provided. Initially, a plurality of current sources in the amplifier is actuated. The amplifier...
US-7,777,572 Integrated power amplifier
Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high...
US-7,777,569 Anti-pop method and apparatus for class AB amplifiers
A method for actuating an amplifier to generally eliminate a pop is provided. Accordingly, a plurality of current sources is actuated in an input stage, and a...
US-7,777,531 Low power low voltage differential signaling (LVDS) output drivers
A method and apparatus for providing a low power low voltage differential signaling driver are disclosed. In an example, a low voltage differential signaling...
US-7,777,525 Input buffer in ultradeep submicron process
An input buffer for an Ultradeep Sub Micron (UDSM) process which allows the UDSM process to interface with a 3V input. The input voltage is applied to a...
US-7,777,514 Methods for transferring integrated circuits to a printed circuit board
The present invention implements a mechanism using an inter-connection layer to couple a plurality of integrated circuit devices to a printed circuit board,...
US-7,777,470 System and method for controlling a hysteretic mode converter
A system and method for controlling a conversion frequency of a hysteretic mode voltage converter. A digital control loop comprises a timing measure unit having...
US-7,776,653 Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices
A device has a first semiconductor chip (101) with contact pads in an interior first set (102) and a peripheral second set (103). A deformed sphere (104) of...
US-7,776,625 Method for locating a sub-surface feature using a scatterometer
The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may...
US-7,774,758 Systems and methods for secure debugging and profiling of a computer system
The present disclosure describes methods and systems for secure debugging and profiling of a computer system. Some illustrative embodiments may include a system...
US-7,774,739 Methods for adjusting shifter width of an alternating phase shifter having variable width
In accordance with an embodiment of the invention, there is a method of designing a lithography mask. The method can comprise determining a maximum width of a...
US-7,774,664 Separate scan cell in series with TAP instruction register
An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports...
US-7,773,692 System and methods for digitally correcting a non-linear element using a digital filter for predistortion
System and methods for a digital linearization of a non linear element. Digital predistortion methods and circuitry for linearizing a non-linear element that...
US-7,773,639 Synchronization of voice packet generation with transmission opportunities in a wireless network
One embodiment of the present invention includes a method for synchronizing packet production and receipt from a digital signal processor (DSP) with polled...
US-7,773,560 Repeated channel adaptive frequency hopping
The invention provides systems, devices, and methods for frequency hopping. In one method embodiment, the invention hops between frequencies by using the same...
US-7,773,431 Systems and methods for reading data from a memory array
One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that...
US-7,773,359 Overcurrent protection system and method
An overcurrent protection system and method are disclosed. In one embodiment the overcurrent protection system includes a first switch connected between a supply...
US-7,773,358 Output current control and overload protection in digital audio amplifiers
Overcurrent and overload protection for the power output of a pulse-width-modulated digital audio system is disclosed. The overcurrent protection circuitry...
US-7,773,115 Method and system for deblurring digital camera images using reference image and motion estimation
Deblur digital camera image captured in low-light, long-integration-time conditions by deconvolution based on motion estimation from preceding and following...
US-7,773,024 SAR analog-to-digital converter with large input range
A method for analog-to-digital conversion is provided using successive approximation and a plurality of capacitors including a first set of capacitors and a...
US-7,773,011 Self-testing digital-to-analog converter
One embodiment of the invention includes a digital-to-analog converter (DAC) circuit. The DAC circuit includes a DAC portion configured to generate an output...
US-7,772,890 Systems and methods for dynamic logic keeper optimization
Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide dynamic logic...
US-7,772,867 Structures for testing and locating defects in integrated circuits
A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically...
US-7,772,830 Test handler automatic contactor cleaner methods and surrogate cleaning device
Methods and devices are disclosed for cleaning contactors equipped with contact pins such as pogo pins include steps which may be performed in concert with...
US-7,772,644 Vertical diffused MOSFET
A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS...
US-7,772,075 Formation of a MOSFET using an angled implant
A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS...
US-7,772,060 Integrated SiGe NMOS and PMOS transistors
A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method...
US-7,772,059 Method for fabricating graphene transistors on a silicon or SOI substrate
A method of fabricating graphene transistors, comprising providing an SOI substrate, performing an optional threshold implant on the SOI substrate, forming an...
US-7,772,057 Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate...
An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor...
US-7,772,014 Semiconductor device having reduced single bit fails and a method of manufacture thereof
One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an...
US-7,771,157 Bi-directional wafer transfer mechanism and method
A wafer transfer machine transfers wafers from either of a first wafer cassette (55) and a second wafer cassette (56) having incompatible registration features...
US-7,770,084 Selectable JTAG or trace access with data store and output
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and...
US-7,770,083 DDR register circuitry input to IC test controller circuitry
A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The...
US-7,770,081 Interface circuit for a single logic input pin of an electronic system
An interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse coded signal applied to said pin to a...
US-7,769,098 Low complexity precoding matrix selection
A method of determining indices for matrix codewords in a matrix codeword codebook. The matrix codewords are adapted for communicating information between a...
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