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Patent # Description
US-7,804,328 Source/emitter follower buffer driving a switching load and having improved linearity
A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a...
US-7,803,703 Metal-germanium physical vapor deposition for semiconductor device defect reduction
The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by...
US-7,801,262 All digital phase locked loop architecture for low power cellular applications
A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector....
US-7,801,247 Multiple input, multiple output system and method
A linear transformation of parallel multiple input, multiple output (MIMO) encoded streams; also, space-time diversity and asymmetrical symbol mapping of...
US-7,801,204 Estimation of BER performance
A method to determine bit error rate (BER) for a given channel of a communication system includes determining a first statistical representation of at least one...
US-7,800,975 Digital data buffer with phase aligner
A digital data buffer has at least one data path and a parallel reference data path. The data path includes a first and second data register, and the reference...
US-7,800,454 Digital controlled oscillator
A digital controlled oscillator including a programmable current source, a first variable capacitor and a second variable capacitor. A comparator compares the...
US-7,800,409 Logic block, a multi-track standard cell library, a method of designing a logic block and an asic employing the...
A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of...
US-7,799,669 Method of forming a high-k gate dielectric layer
A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon...
US-7,799,668 Formation of uniform silicate gate dielectrics
The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one...
US-7,799,649 Method for forming multi gate devices using a silicon oxide masking layer
The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer...
US-7,799,632 Method of forming an isolation structure by performing multiple high-density plasma depositions
One embodiment of the present invention relates to a method of forming an isolation structure. During this method, an isolation trench is formed within a...
US-7,799,582 Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean
A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A...
US-7,797,991 Rocking Y-shaped probe for critical dimension atomic force microscopy
Measuring surface profiles of structures on integrated circuits is difficult when feature sizes are less than 100 nanometers. Atomic force microscopy provides...
US-7,797,686 Behavior of trace in non-emulatable code
Code will switch to secure code via an exception only. All PC and data trace will be turned off during secure code. This will occur regardless of trace being in...
US-7,797,685 Method for generating timing data packet
During a trace the timing stream has the active and stall information, PC stream has all the discontinuity information, and the data stream has all the data log...
US-7,797,602 Compressor/decompressor circuits coupled with TDO-TMS/TDI die channel circuitry
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-7,797,514 Scalable multi-threaded sequencing/synchronizing processor architecture
A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared...
US-7,797,476 Flexible connection scheme between multiple masters and slaves
The present invention describes a flexible routing scheme between masters and slaves in complex digital systems. The routing scheme is optimized for maximum...
US-7,797,362 Parallel architecture for matrix transposition
An extension to current multiple memory bank video processing architecture is presented. A more powerful memory controller is incorporated, allowing computation...
US-7,797,065 Automute detection in digital audio amplifiers
A digital audio processor for a digital audio receiver having an improved automute sequence is disclosed. The digital audio processor includes automute detection...
US-7,796,834 Post-processing technique for noise reduction of DCT-based compressed images
A new post-processing methodology reduces the unwanted noise artifacts present in the output images of DCT-based compressed signals. The method determines noise...
US-7,796,823 Texture compression
3D graphics rendering includes texture compression including joint compression of related textures by using one texture to predict the other, object-based...
US-7,796,721 High speed, symmetrical prescaler
Over the years, ring counter and prescalers have been used in a variety of microelectronic applications, including Phased Locked Loops or PLLs. All of these...
US-7,796,716 Eliminating narrowband interference in a receiver
A wireless device receives an input signal representing a signal of interest (e.g., one or more portions of a packet) on a wireless medium. The input signal may,...
US-7,796,649 System and method for providing additional channels to an existing communications device
System and method for providing additional channels to an existing communications system. A preferred embodiment comprises a coprocessor (such as coprocessor...
US-7,796,574 Multi-carrier reception for ultra-wideband (UWB) systems
System and method for receiving transmissions in a wireless communications system. A preferred embodiment comprises a receiver (such as receiver 400) that can...
US-7,796,566 Methods and apparatus to perform dynamic channel management and dynamic bandwidth changes in wireless local...
Methods and apparatus to perform dynamic channel management and dynamic bandwidth changes in wireless local area networks are disclosed. A disclosed example...
US-7,796,077 High speed high resolution ADC using successive approximation technique
An analog to digital converter (ADC) containing a sub-ADC to resolve at least some of the bits using successive approximation principle (SAP), while providing...
US-7,796,066 System and method for common mode translation
System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC...
US-7,796,060 Circuits and methods to minimize nonlinearity errors in interpolating circuits
Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein. A disclosed example circuit comprises first and second...
US-7,795,970 Reduction of dead-time distortion in class D amplifiers
Pulse-width-modulating class D amplifier with an H-bridge output stage, and method of operating the same. in which output stage dead-time is compensated. Offset...
US-7,795,958 Minimizing changes in common mode voltage at inputs of an operational amplifier used in a switched capacitor...
A reference generation circuit provided according to an aspect of the present invention generates a reference potential at different levels in the hold phase of...
US-7,795,956 Multi format video filter design
Current generation digital media processors support multi-format video resolutions, SDTV, Progressive Scan and HDTV. Built-in video encoders directly support...
US-7,795,943 Integrated circuit device and layout design method therefor
An integrated circuit device has multiple first circuit elements arranged in a first area. A signal distribution circuit that has multiple drive circuits is...
US-7,795,918 Adjusting output buffer timing based on drive strength
This invention operates to select a drive code for an adjustable drive strength transistor in a drive buffer. The drive code is determined employing a...
US-7,795,122 Antimony ion implantation for semiconductor components
A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating...
US-7,795,097 Semiconductor device manufactured by removing sidewalls during replacement gate integration scheme
One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor...
US-7,795,085 Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs
Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning...
US-7,795,072 Structure and method of high performance two layer ball grid array substrate
A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an...
US-7,795,070 Semiconductor device including an amorphous nitrided silicon adhesion layer and method of manufacture therefor
Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a...
US-7,793,186 System and method for increasing the extent of built-in self-testing of memory and circuitry
An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one...
US-7,793,182 TAP domain selection circuit with selected TDI/TDO or TDO lead
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,793,178 Cell supporting scan-based tests and with reduced time delay in functional mode
A memory cell supporting scan-based tests and with reduced time delay in functional mode. The memory cell generates separate clocks for latching functional and...
US-7,793,152 Zero-bit scans defining command window and control level
A method comprises performing at least one zero-bit scan across an interface. The at least one zero-bit scan defines a command window. Further, the method...
US-7,793,119 Adaptive voltage scaling with age compensation
One embodiment of the present invention includes an adaptive voltage scaling system associated with an integrated circuit (IC). The system comprises at least one...
US-7,792,498 Apparatus for and method of automatic radio link establishment
A novel and useful mechanism for automatically establishing a radio link between a communications device and a commercially available FM radio receiver, thereby...
US-7,791,926 SEU hardening circuit and method
An SEU hardening circuit and method is disclosed. In one embodiment, a method includes providing a semiconductor memory component having a pair of pMOS...
US-7,791,720 Semiconductor manufacturing peripheral verification tool
Apparatus and methods for verification of the dimensions of a semiconductor manufacturing peripheral are disclosed, in which the peripheral, e.g., a wafer...
US-7,791,518 Flicker noise reduction in continuous time (CT) sigma delta modulators (SDMS)
Embodiments of a system for processing a signal may include a receiver configured to receive an input analog signal and an up converter coupled with the receiver...
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