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Patent # Description
US-9,548,199 Method of forming a thin film that eliminates air bubbles
A method, which forms an air-bubble-free thin film with a high-viscosity fluid resin, initially dispenses the fluid resin on an outer region of a semiconductor...
US-9,547,617 PHY IC ACA bridge, RID.sub.--B resistance, and VBUS voltage circuits
A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus...
US-9,547,042 IR enabled gating of TAP and WSP shift, capture, transfer
In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500...
US-9,544,592 Methods and systems for encoding pictures associated with video data
Several methods and systems for encoding pictures are disclosed. In an embodiment, a method comprises dividing an LCU of a picture into a plurality of MERs...
US-9,544,231 Packet processing VLIW action unit with OR-multi-ported instruction memory
An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each...
US-9,544,027 Loop powered transmitter with a single tap data isolation transformer and unipolar voltage converters
A loop-powered transmitter includes a data isolation transformer including primary and secondary windings and an analog-to-digital converter (ADC) to convert a...
US-9,543,981 CRC-based forward error correction circuitry and method
A CRC (cyclic redundancy check) generator circuit (28) generates a first CRC code based on a message. The CRC code is amended to the message, creating a first...
US-9,543,972 Stability controlled high frequency chopper-based oscillator
Circuitry for providing an oscillating output signal. This circuitry includes a transconductance circuit having a first input, a second input, an output. The...
US-9,543,969 High-speed resistor-based charge pump for active loop filter-based phase-locked loops
Techniques are described for increasing the speed of a resistor-based charge pump for an active loop filter-based phase-locked loop (PLL). The techniques may...
US-9,543,944 Driver for normally on III-nitride transistors to get normally-off functionality
A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode...
US-9,543,891 Low-power low-phase-noise oscillator
The present disclosure describes a low-power, low-phase-noise (LPLPN) oscillator. The LPLPN oscillator includes a resonator load, an amplifier stage, and a loop...
US-9,543,735 Optoelectronic packages having through-channels for routing and vacuum
A stacked optoelectronic packaged device includes a plurality of stacked components within a package material having a package body providing side walls and a...
US-9,543,437 Integrated circuit with dual stress liner boundary
An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates...
US-9,543,430 Segmented power transistor
A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain...
US-9,543,374 Low temperature coefficient resistor in CMOS flow
A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of...
US-9,543,299 P-N bimodal conduction resurf LDMOS
RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is...
US-9,543,240 DC-DC converter having terminals of semiconductor chips directly attachable to circuit board
A power supply system has a leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable...
US-9,543,206 Wafer die separation
A method of singulating a wafer starts with fracturing the wafer. The method may also include attaching the dicing tape sheet to a ring frame; relatively...
US-9,543,149 High voltage lateral extended drain MOS transistor with improved drift layer contact
An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region...
US-9,542,521 Filler insertion in circuit layout
A method for filler insertions in a circuit layout having a cell row of standard cells and gaps between the standard cells is disclosed. First, a set of filler...
US-9,542,179 System and method for energy aware program development
A program optimizer includes an energy tracking system, an energy monitoring system, and a code generation control system. The energy tracking system measures a...
US-9,542,045 Detecting and tracking touch on an illuminated surface using a mean-subtracted image
A method for touch detection performed by a touch processor in an optical touch detection system is provided that includes receiving an image of an illuminated...
US-9,541,989 Power transfer estimation
A power conversion system includes a power transfer estimator that is operable to provide a determination of the cumulative amount of power transferred through...
US-9,538,311 Auto-provisioning for internet-of-things devices
A connectivity device includes a microcontroller, a network interface coupled to the microcontroller, and a non-transitory storage device coupled to the...
US-9,538,092 Methods and apparatus to generate wide dynamic range images
Methods and apparatus to generate wide dynamic range images are disclosed. An example apparatus includes a first processing block having first input, second...
US-9,537,533 PLC FCH unitary circle differential symbol and preamble encoding determination
Embodiments of the invention provide a method for discriminating between two types of encoding schemes for the frame control header (FCH) used in G3-type narrow...
US-9,536,822 Drawn dummy FeCAP, via and metal structures
An integrated circuit containing hydrogen permeable dummy vias configured in a linear or rectangular array and symmetrically positioned over a component in the...
US-9,536,781 Method of making integrated circuit
Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is...
US-9,536,753 Circuit substrate interconnect
A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the...
US-9,536,656 Systems and methods of reduction of parasitic losses in a wireless power system
Example embodiments of the systems and methods of reduction of parasitic losses in a wireless power system disclosed herein provide a practical means of...
US-9,536,025 Transmitting LSB timestamp datum in parallel and MSB in series
A timestamp generator generates a timestamp value having a predetermined number of most significant bits and a predetermined number of least significant bits....
US-9,535,439 LDO current limit control with sense and control transistors
A circuit and method for providing a current limiting feature in a low dropout ("LDO") linear voltage regulator. A pass element generates an output voltage that...
US-9,535,127 Tester, parallel scan paths, and comparators in same functional circuits
An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the...
US-9,535,126 Tap, test, CSU, scan circuitry with top and bottom contacts
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
US-9,535,125 Tap decay test circuitry having capture test strobe enable input
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits...
US-9,535,124 TAP gated updateDR output AUX test control of WSP update
In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture,...
US-9,535,123 Frequency scaled segmented scan chain for integrated circuits
A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a...
US-9,535,122 Serial/parallel control, separate tap, master reset synchronizer for tap domains
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
US-9,535,118 TAP addressable circuit with bi-directional TMS and second signal lead
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-9,533,618 Method, apparatus and system for processing a display from a surround view camera solution
A method, apparatus and a system multi-camera image processing method. The method includes performing geometric alignment to produce a geometric output,...
US-9,532,230 Method and apparatus for transmitting LTE waveforms in shared spectrum by carrier sensing
A method of operating a long term evolution (LTE) communication system on a shared frequency spectrum is disclosed. A user equipment (UE) is initialized on an...
US-9,531,563 Efficient fairness allocation in powerline CSMA/CA protocols
Transmission over a communication channel using carrier sense multiple access collision avoidance (CSMA/CA) may be performed by determining for each frame if...
US-9,531,372 Driver with transformer feedback
A driver circuit includes an input drive stage, an output drive stage, and a transformer. The input drive stage is configured to receive a differential input...
US-9,531,343 Systems and methods of variable fractional rate digital resampling
Example embodiments of the systems and methods of variable fractional rate digital resampling as disclosed herein achieve variable rate conversion. In the...
US-9,531,335 Method and circuitry for CMOS transconductor linearization
Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the...
US-9,531,267 DC-DC converter using internal ripple with the DCM function
A DC-DC converter, having an input voltage and an output voltage, includes an inductor and a switch switching the input voltage to an input side of the...
US-9,529,411 Power-saving mode for USB power delivery sourcing device
Methods of reducing power consumption in a USB power-delivery source device. In one such method, one or more source capabilities messages are sent by the USB...
US-9,529,375 Single inductor-multiple output DC-DC converter, method for operating the same and electronic device comprising...
Single inductor-multiple output (SIMO) DC-DC converter, having an output node which is coupled to one side of the single inductor to receive a load current. A...
US-9,529,334 Rotational transition based clock, rotational spectroscopy cell, and method of making same
Described examples include a millimeter wave atomic clock apparatus, chip scale vapor cell, and fabrication method in which a low pressure dipolar molecule gas...
US-9,529,045 Taps with class T0-T2, T4 capabilities and topology selection logic
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data...
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