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Patent # Description
US-9,484,858 Inductive coupled pass transistor quadrature voltage controlled oscillator
A quadrature voltage controlled oscillator (QVCO) for providing an oscillating output signal. The QVCO includes a first oscillating circuit for producing a...
US-9,484,630 Chip to dielectric waveguide interface for sub-millimeter wave communications link
In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue....
US-9,484,614 Dielectric waveguide signal divider
A dielectric waveguide (DWG) has a longitudinal core member with a first dielectric constant value surrounded by a cladding with a cladding dielectric constant...
US-9,484,450 Integrated channel diode
A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over...
US-9,484,435 MOS transistor with varying channel width
One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the...
US-9,484,095 TCAM providing efficient move contents operation
An embodiment of the invention includes a Ternary Content Addressable Memory (TCAM) that includes a group of TCAM block. Each TCAM block stores a number of...
US-9,483,638 Method and system for preventing unauthorized processor mode switches
A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing...
US-9,483,429 Unified input/output controller for integrated wireless devices
A novel and useful apparatus for and method of a unified IO controller well suited for use in integrated wireless devices incorporating multiple functions. The...
US-9,483,065 Power regulation with load detection
One embodiment of the present invention includes a power regulator system. The system includes a power stage configured to provide an output voltage to a load...
US-9,482,718 Integrated circuit
Integrated circuits and methods for testing integrated circuits are disclosed herein. An embodiment of an integrated circuit includes a microprocessor and...
US-9,482,717 Wafer scale testing using a 2 signal JTAG interface
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-9,481,572 Optical electronic device and method of fabrication
An optical electronic device and method that forms cavities through an interposer wafer after bonding the interposer wafer to a window wafer. The cavities are...
US-RE46,193 Distributed power control for controlling power consumption based on detected activity of logic blocks
An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller...
US-9,479,932 ID-based control unit-key fob pairing
A key fob includes a transceiver to send and receive signals, a memory to store a key fob identification (KFID), and a processor coupled to said transceiver and...
US-9,479,882 Initial command to switch transistors disconnecting keys from microphone line
An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in...
US-9,479,867 Method and circuitry for direction of arrival estimation using microphone array with a sharp null
A device is configured for identifying a direction of a sound. The device includes a controller comprising circuitry. The circuitry is configured to receive a...
US-9,479,366 IIR DFE updating gain and time constants using LMS equations
A method for adapting a mixed signal Infinite Impulse Response (IIR) Decision Feedback Equalizer (DFE) using pivot taps and monitor taps is disclosed. The...
US-9,479,186 Gain and offset correction in an interpolation ADC
In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a...
US-9,479,134 Position detecting system
A position detecting system detects and responds to the movement of a target through a sensing domain area of a plane. The movement causes the amount of the...
US-9,478,510 Self-aligned under bump metal
An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with...
US-9,477,626 2-pin interface with data input, data output, address match input
A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One...
US-9,477,246 Low dropout voltage regulator circuits
In an embodiment, a voltage regulator is disclosed. The voltage regulator circuit includes a switch, a first feedback circuit and a second feedback circuit. The...
US-9,476,942 Divided scan path cells with first and state hold multiplexers
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan...
US-9,476,941 Low power Scan-BIST test data generator and compactor pass/fail output
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-9,476,933 Apparatus and methods for qualifying HEMT FET devices
A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain...
US-9,474,055 Allocation and logical to physical mapping of scheduling request indicator channel in wireless networks
A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is...
US-9,474,035 Computer generated sequences for downlink and uplink signals in wireless communication systems
The present disclosure provides a base station transmitter, a user equipment transmitter and methods of operating the base station and user equipment...
US-9,473,792 Method and system to improve the performance of a video encoder
Method and system to improve the performance of a video encoder. The method includes processing an initial video signal in a front-end image pre-processor to...
US-9,473,784 Sample adaptive offset (SAO) filtering in video coding
A method for sample adaptive offset (SAO) filtering of largest coding units (LCUs) of a video frame in an SAO component is provided that includes receiving, by...
US-9,473,782 Loop filtering managing storage of filtered and unfiltered pixels
A video encoder comprises a loop filter to filter luminance and chrominance pixel values, first and second loop filter working buffers accessible to the loop...
US-9,473,769 Method and system for reducing slice header parsing overhead in video coding
A method for encoding a picture of a video sequence in a bit stream that reduces slice header parsing overhead is provided. The method includes determining...
US-9,473,219 Enabling coordinated multi-point reception
This invention measures the propagation delay .tau..sub.1 between the user equipment and a first cooperating unit and the propagation delay .tau..sub.2 between...
US-9,473,155 Software reconfigurable digital phase lock loop architecture
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit...
US-9,473,140 Series arranged multiplexers specification support enablement circuit and method
Several circuits and methods that may be implemented to enable specification support of a plurality of interface components in an IC are disclosed. In an...
US-9,473,092 Reconfigurable amplifier
An amplifier receives a differential signal and, in response, generates a first negative input current and a first positive input current. In a first operating...
US-9,473,078 Tunable power amplifier with wide frequency range
A circuit includes an amplifier configured to amplify an input signal and generate an output signal. The circuit also includes a tuning network configured to...
US-9,473,023 Switched mode assisted linear regulator with seamless transition between power tracking configurations
A Switch Node Assisted Linear architecture, including a linear amplifier in parallel with a switched converter, is configurable in two tracking modes: (a) a...
US-9,472,840 Dielectric waveguide comprised of a core, a cladding surrounding the core and cylindrical shape conductive...
A dielectric waveguide (DWG) has a dielectric core member that has a length L and an oblong cross section. The core member has a first dielectric constant...
US-9,472,571 Isolated semiconductor layer over buried isolation layer
An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of...
US-9,472,478 Die testing using top surface test pads
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding...
US-9,472,440 Integrated circuit package strip insert assembly
A plurality of inserts adapted are to be received in a plurality of holes in a support plate having a first surface adapted to engage a first surface of an...
US-9,472,268 SRAM with buffered-read bit cells and its testing
An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a...
US-9,471,320 Using L1 cache as re-order buffer
A method is shown that eliminates the need for a dedicated reorder buffer register bank or memory space in a multi level cache system. As data requests from the...
US-9,471,317 Execution of additional instructions in conjunction atomically as specified in instruction field
A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a...
US-9,471,278 Low area full adder with shared transistors
A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input...
US-9,471,140 Valid context status retention in processor power mode management
A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining...
US-9,471,121 Microprocessor based power management system architecture
An electronic system is disposed on a single integrated circuit including a plurality of power domains and a power control manager. Each power domain may be...
US-9,470,886 Split phosphor/slit color wheel segment for color generation in solid-state illumination system
Apparatus for generating blue color illumination for use in a projection system a color wheel with segments of respective different color light emitting...
US-9,470,758 Embedded parallel scan paths, stimulus formatter, and control interface circuitry
The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and...
US-9,470,710 Capacitive MEMS sensor devices
A packaged capacitive MEMS sensor device includes at least one capacitive MEMS sensor element with at least one capacitive MEMS sensor cell including a first...
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