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Patent # Description
US-7,809,961 Standby mode for power management
An apparatus and method for controlling standby mode in an electronic device. In standby mode, power and clock signals are reduced or stopped to conserve power....
US-7,809,934 Security measures for preventing attacks that use test mechanisms
A system comprising processing logic adapted to determine a type of boot performed by the system and a storage coupled to the processing logic. The processing...
US-7,809,927 Computation parallelization in software reconfigurable all digital phase lock loop
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit...
US-7,809,889 High performance multilevel cache hierarchy
A digital system is provided with a hierarchical memory system having at least a first and second level cache and a higher level memory. If a requested data item...
US-7,809,346 Digital audio receiver with reduced AM interference
A digital audio system including a digital audio amplifier with reduced AM interference. The digital audio amplifier includes a pulse-width-modulation (PWM)...
US-7,809,338 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using wideband modulation...
A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF...
US-7,809,188 Digital camera and method
Digital camera contrast enhancement with piecewise-linear transform with lower and upper cutoffs for the transform determined from histogram analysis with a...
US-7,809,082 GMSK/EDGE modulator with switching transition smoothing
To minimize abrupt changes in modulated signal amplitude when switching between modulation types in a multi-modulation system, a "smoothing" circuit is used....
US-7,808,449 Method and system for multi-channel viewing applications
Methods and apparatus for rendering plural channels on a common display are provided. In a method embodiment, a method for allowing sharing of a display by a...
US-7,808,327 Method and apparatus to provide digitally controlled crystal oscillators
Methods and systems to provide digitally controlled crystal oscillators are disclosed. One example method includes determining a state of an oscillator system...
US-7,808,325 System and method for frequency pushing/pulling compensation
A system and method for frequency pushing/pulling compensation in phase-locked loops including a method for cancelling frequency push/pull in an oscillator of a...
US-7,808,266 Method and apparatus for evaluating the effects of stress on an RF oscillator
Apparatus and methods are disclosed for evaluating degradation of a transistor in a cross coupled pair of an RF oscillator independently. A MOS device can be...
US-7,808,264 Isolated conductive leads extending across to opposite sides of IC
An integrated circuit includes switching circuits for selectively connecting the bond pads to functional core logic and isolating the bond pads from second...
US-7,808,244 System and method for determining state of charge of a battery utilizing initial voltage and current...
A processor executes a program to calculate values of the internal resistance R of a battery and updates a database of parameters defining the dependence of...
US-7,808,218 Duty-cycle independent current limit for a power regulator
One embodiment of the invention includes a power regulator system. The system comprises an error amplifier that provides an error voltage based on a comparison...
US-7,808,113 Flip chip semiconductor device having workpiece adhesion promoter layer for improved underfill adhesion
A semiconductor device assembly (200) includes a workpiece (205) having a surface including a die attach region corresponding to regions under an integrated...
US-7,808,088 Semiconductor device with improved high current performance
A semiconductor device comprises a die having a first surface and a second surface, a first leadframe connected to the first surface and the second surface, and...
US-7,808,071 Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of...
One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The...
US-7,807,978 Divergent charged particle implantation for improved transistor symmetry
The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for...
US-7,807,540 Back end thin film capacitor having plates at thin film resistor and first metallization layer levels
An integrated circuit back end capacitor structure includes a first dielectric layer on a substrate, a thin film bottom plate on the first dielectric layer, and...
US-7,807,522 Lanthanide series metal implant to control work function of metal gate electrodes
Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal nitride is formed above a...
US-7,807,343 EDA methodology for extending ghost feature beyond notched active to improve adjacent gate CD control using a...
In accordance with various embodiments, semiconductor devices and methods of forming semiconductor devices having non-rectangular active regions are provided. An...
US-7,805,708 Automatic tool to eliminate conflict cache misses
This invention simulates program to create a conflict graph of the cache accesses. The conflict graph is used to relay out relocatable functions to minimize...
US-7,805,647 System and method for testing a plurality of circuits
A system for, and method of, testing a plurality of circuits, which may be unsingulated die on a wafer. In one embodiment, the system includes: (1) a test data...
US-7,805,644 Multiple pBIST controllers
A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test...
US-7,805,122 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using digital mixing and...
A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF...
US-7,804,702 Ferroelectric memory cell with access transmission gate
One embodiment relates to an integrated circuit that includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric capacitor...
US-7,804,699 Segmented ternary content addressable memory search architecture
A segmented ternary content addressable memory (TCAM) search architecture is disclosed. In one embodiment, a TCAM device with a row of TCAM cells includes a...
US-7,804,433 Methods and apparatus for error cancelation in calibrated current sources
Methods and apparatus for error cancelation in calibrated current sources are disclosed. In an example, a digital to analog converter to convert digital bits...
US-7,804,337 Method and apparatus of SFDR enhancement
A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and...
US-7,804,336 Track-and-hold circuit with low distortion
A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input...
US-7,804,328 Source/emitter follower buffer driving a switching load and having improved linearity
A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a...
US-7,803,703 Metal-germanium physical vapor deposition for semiconductor device defect reduction
The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by...
US-7,801,262 All digital phase locked loop architecture for low power cellular applications
A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector....
US-7,801,247 Multiple input, multiple output system and method
A linear transformation of parallel multiple input, multiple output (MIMO) encoded streams; also, space-time diversity and asymmetrical symbol mapping of...
US-7,801,204 Estimation of BER performance
A method to determine bit error rate (BER) for a given channel of a communication system includes determining a first statistical representation of at least one...
US-7,800,975 Digital data buffer with phase aligner
A digital data buffer has at least one data path and a parallel reference data path. The data path includes a first and second data register, and the reference...
US-7,800,454 Digital controlled oscillator
A digital controlled oscillator including a programmable current source, a first variable capacitor and a second variable capacitor. A comparator compares the...
US-7,800,409 Logic block, a multi-track standard cell library, a method of designing a logic block and an asic employing the...
A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of...
US-7,799,669 Method of forming a high-k gate dielectric layer
A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon...
US-7,799,668 Formation of uniform silicate gate dielectrics
The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one...
US-7,799,649 Method for forming multi gate devices using a silicon oxide masking layer
The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer...
US-7,799,632 Method of forming an isolation structure by performing multiple high-density plasma depositions
One embodiment of the present invention relates to a method of forming an isolation structure. During this method, an isolation trench is formed within a...
US-7,799,582 Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean
A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A...
US-7,797,991 Rocking Y-shaped probe for critical dimension atomic force microscopy
Measuring surface profiles of structures on integrated circuits is difficult when feature sizes are less than 100 nanometers. Atomic force microscopy provides...
US-7,797,686 Behavior of trace in non-emulatable code
Code will switch to secure code via an exception only. All PC and data trace will be turned off during secure code. This will occur regardless of trace being in...
US-7,797,685 Method for generating timing data packet
During a trace the timing stream has the active and stall information, PC stream has all the discontinuity information, and the data stream has all the data log...
US-7,797,602 Compressor/decompressor circuits coupled with TDO-TMS/TDI die channel circuitry
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-7,797,514 Scalable multi-threaded sequencing/synchronizing processor architecture
A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared...
US-7,797,476 Flexible connection scheme between multiple masters and slaves
The present invention describes a flexible routing scheme between masters and slaves in complex digital systems. The routing scheme is optimized for maximum...
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