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Patent # Description
US-7,772,890 Systems and methods for dynamic logic keeper optimization
Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide dynamic logic...
US-7,772,867 Structures for testing and locating defects in integrated circuits
A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically...
US-7,772,830 Test handler automatic contactor cleaner methods and surrogate cleaning device
Methods and devices are disclosed for cleaning contactors equipped with contact pins such as pogo pins include steps which may be performed in concert with...
US-7,772,644 Vertical diffused MOSFET
A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS...
US-7,772,075 Formation of a MOSFET using an angled implant
A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS...
US-7,772,060 Integrated SiGe NMOS and PMOS transistors
A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method...
US-7,772,059 Method for fabricating graphene transistors on a silicon or SOI substrate
A method of fabricating graphene transistors, comprising providing an SOI substrate, performing an optional threshold implant on the SOI substrate, forming an...
US-7,772,057 Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate...
An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor...
US-7,772,014 Semiconductor device having reduced single bit fails and a method of manufacture thereof
One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an...
US-7,771,157 Bi-directional wafer transfer mechanism and method
A wafer transfer machine transfers wafers from either of a first wafer cassette (55) and a second wafer cassette (56) having incompatible registration features...
US-7,770,084 Selectable JTAG or trace access with data store and output
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and...
US-7,770,083 DDR register circuitry input to IC test controller circuitry
A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The...
US-7,770,081 Interface circuit for a single logic input pin of an electronic system
An interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse coded signal applied to said pin to a...
US-7,769,098 Low complexity precoding matrix selection
A method of determining indices for matrix codewords in a matrix codeword codebook. The matrix codewords are adapted for communicating information between a...
US-7,769,090 Active link cable diagnostics
A novel apparatus for and method of estimating the cable length of an active network link. The cable diagnostics mechanism of the invention is particularly...
US-7,768,850 System for bitcell and column testing in SRAM
A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The...
US-7,768,820 Feedback structure for an SRAM cell
Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the...
US-7,768,351 Variable gain current input amplifier and method
Variable gain circuitry includes a first input transistor (M1) having a source coupled to a first conductor (32), a gate coupled to a first input voltage (Vin+),...
US-7,768,305 Quad state to two state interface circuitry with clock input
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring...
US-7,767,995 Single-electron tunnel junction for complementary metal-oxide device and method of manufacturing the same
A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a...
US-7,767,897 Beat matching for portable audio
Beat matching for two audio streams extracts beats from each, computes a conversion ratio from one stream to the other stream by an initial beat alignment plus a...
US-7,767,511 Semiconductor device manufactured using a method to improve gate doping while maintaining good gate profile
In one aspect, there is provided a method of manufacturing a semiconductor device. This method includes forming gate structures over a substrate, wherein the...
US-7,767,510 Semiconductor device made by the method of producing hybrid orientnation (100) strained silicon with (110) silicon
There is provided a method of manufacturing a semiconductor device. In one aspect, the method includes providing a strained silicon layer having a crystal...
US-7,765,516 System and method for making photomasks
The present application is directed a method for preparing a mask pattern database for proximity correction. The method comprises receiving data from a design...
US-7,765,447 Selectively accessing test access ports in a multiple test access port environment
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-7,764,451 System and method for use in displaying modulated light
A system for use in displaying modulated light includes a light source operable to generate a light beam. The system also includes a color wheel for receiving...
US-7,764,418 Sloped cantilever beam electrode for a MEMS device
A method of tilting a micromirror includes providing a substrate, a sloped electrode outwardly from the substrate, and a sloped electrode positioning system...
US-7,764,210 System and method for converting an input signal
A video driver includes a current-to-voltage converter circuit that converts an analog input current to a corresponding analog voltage. Active termination...
US-7,763,975 Flip-chip assembly of protected micromechanical devices
A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated...
US-7,763,949 MEMS device with controlled gas space chemistry
A process for protecting a MEMS device used in a UV illuminated application from damage due to a photochemical activation between the UV flux and package gas...
US-7,763,540 Method of forming a silicided gate utilizing a CMP stack
A method for fabricating a semiconductor device includes forming a silicided gate utilizing a CMP stack. The CMP stack includes a first liner formed over the...
US-7,761,762 Adapter implemented background data transfers while tap in non-scan state
A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions...
US-7,761,617 Multi-threaded DMA
A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with "m" threads...
US-7,761,285 Data processing condition detector with table lookup
In support of data processing emulation, a data processing condition indicated by a predetermined number of digital data processing signals can be detected by...
US-7,761,068 System and method for a time alignment analog notch
System and method for creating a time alignment analog notch. An embodiment includes a digital power amplifier coupled to an enable signal line and to a digital...
US-7,760,118 Multiplexing aware sigma-delta analag-to-digital converter
The present invention relates to an electronic device for analog-to-digital conversion including a sigma-delta modulator (SD), a digital filter (FIL) for digital...
US-7,760,011 System and method for auto-power gating synthesis for active leakage reduction
A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power...
US-7,760,006 Method and system to reduce electromagnetic radiation from semiconductor devices
Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a...
US-7,759,182 Dummy active area implementation
Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in...
US-7,757,223 Method and system to construct a data-flow analyzer for a bytecode verifier
The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware...
US-7,757,140 IEEE 1149.1 and P1500 test interfaces combined circuits and processes
In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally...
US-7,757,067 Pre-decoding bytecode prefixes selectively incrementing stack machine program counter
A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the...
US-7,756,487 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using pulse generation and selection
A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF...
US-7,756,002 Time-frequency interleaved orthogonal frequency division multiplexing ultra wide band physical layer
A PHY entity for a UWB system utilizes the unlicensed 3.1-10.6 GHZ UWB band, as regulated in the United States by the Code of Federal Regulation, Title 47,...
US-7,755,949 Reset circuit for termination of tracking circuits in self timed compiler memories
A method and circuit for termination of internal cycle and its associated tracking circuits in high performance self timed compiler memories is disclosed. In one...
US-7,755,924 SRAM employing a read-enabling capacitance
Embodiments of the present disclosure provide a memory element, a method of constructing a memory element, a method of operating a memory cell, an SRAM cell and...
US-7,755,400 Systems and methods of digital isolation with AC/DC channel merging
Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example,...
US-7,755,330 Methods and systems for controlling an AC adapter and battery charger in a closed loop configuration
Disclosed are methods, circuits, and systems for implementing an AC voltage adapter and battery charger system in a closed loop topology. Embodiments of the...
US-7,754,528 Method for thin semiconductor packages
A semiconductor device (100) has one or more semiconductor chips (110) with active and passive surfaces, wherein the active surfaces include contact pads. The...
US-7,752,610 Method and system for thread abstraction
Systems, methods, and computer-readable media supporting thread abstraction in Java are provided. In some illustrative embodiments, a system is provided that...
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