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BIST scan path parts with test generator and compactor circuitry
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
JTAG bus communication method and apparatus
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication...
Auxiliary link control commands
Control commands are transmitted via an emulation interface holding a test clock signal at a constant value and switching a test mode select signal a number of...
Automatic gain control for a wideband signal
One embodiment of the present invention includes a method for controlling a gain of a wideband signal. The method comprises adding a virtual channel to the...
Apparatus and method of detection for a packet-based wireless receiver
employing multiple, concurrent...
The present invention provides a packet detector for use with a packet-based wireless receiver employing a receive antenna for P concurrently transmitted...
Methods and systems for communicating using transmitted symbols associated
with multiple time durations
In at least some embodiments, a system may comprise one or more devices configurable to communicate according to a first protocol that permits interpretation of...
Mesh deterministic access
A deterministic access system and method is provided that may be used for gaining access to a shared communication medium in a mesh or decentralized network. The...
Reliable packet detection in a wireless receiver when packets contain a
known repetitive sequence
A wireless receiver operating in a wireless communication environment in which a beginning of a packet contains a repetitive sequence. The wireless receiver may...
Output voltage independent overvoltage protection
One embodiment of the invention includes a power regulation system. The system comprises a power regulator configured to periodically generate a switch signal...
Methodology to guard ESD protection circuits against precharge effects
An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge...
Methods and apparatus to provide dynamically-biased write drivers for hard
disk drive (HDD) application
Methods and apparatus to provide dynamically biased write drivers for hard disk drive applications are described. According to one example, a hard disk drive...
Apparatus and method for acquisition and tracking bank cooperation in a
digitally controlled oscillator
A novel apparatus for and method of acquisition and tracking bank cooperation in a digitally controlled oscillator (DCO) within an all digital phase locked loop...
Systems and methods for voltage controlled oscillator calibration
Various systems, methods and apparatus for calibrating a clock generating circuit are discussed herein. As one example, a method for calibrating a voltage...
Self-biased bipolar ring-oscillator phase-locked loops with wide tuning
Self-biased bipolar ring-oscillator phase-locked loops with a wide tuning range are disclosed. In a particular example, an apparatus to provide a phase-locked...
Circuit and method for transistor turn-off with strong pulldown
In accordance with the present invention, there is provided a circuit and method for providing a switchable strong pulldown for a power FET in an off state to...
Switching system with reduced EMI
Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the...
Distributing time slots in parallel configured, switching power supplies
A multi-phase power system including a plurality of Pulse Width Modulation (PWM) controllers is provided, including a first PWM controller and at least one...
Integrated DRAM process/structure using contact pillars
A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The...
Semiconductor device and its manufacturing method
The object of the invention is to provide a semiconductor device that can form photodiodes that do not short circuit, without damage that causes leakage, despite...
Semiconductor device manufactured by reducing hillock formation in metal
A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species...
Methods of manufacturing trench isolated drain extended MOS (demos)
transistors and integrated circuits therefrom
A method of fabricating an integrated circuit (IC) including at least one drain extended MOS (DEMOS) transistor and ICs therefrom includes providing a substrate...
Gate self aligned low noise JFET
The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and...
Monitoring of temperature variation across wafers during processing
A method of measuring temperature across wafers during semiconductor processing includes the step of providing a correlation between a peak wafer temperature...
Method for performing place-and-route of contacts and vias in technologies
with forbidden pitch requirements
Provide is a method of making a mask layout, an integrated circuit device made by a method, a computer readable medium, and a mask for forming contact holes. The...
Method and system for implementing an interrupt handler
A system for interrupt handling in Java is provided that includes an execution flow class, an execution flow scheduler, a Java virtual machine (JVM), and an...
Die-to-die interconnect interface and protocol for stacked semiconductor
A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit...
Content-transformation power management of a mobile display
The present invention provides a video server. In one embodiment, the video server includes a perceptual analyzer configured to analyze frames of a video...
Image watermarking based on sequency and wavelet transforms
This invention is a new approach for the image watermarking in the wavelet transform domain based on sequency of the host and watermark image. For each sub-band...
An equalization circuit that allows particularly for lowpass filtering by transmission lines comprises a compensating equalizer controlled according to whether...
8T SRAM cell with higher voltage on the read WL
The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry...
Single prism aberration compensation
System and method for utilizing two prisms spatially separated is provided. The two prisms spatially separated allows the two prisms typically found in a TIR...
Reconfigurable circuit to compensate for a low noise amplification input
matching variation and a method for...
A method for changing an effective capacitance of an amplifier circuit having a match transistor and a coupled cascode transistor includes changing an on-state...
Amplifier system with dynamically-adjusted supply voltage
An amplifier system may include an output stage configured to provide an amplified output signal at an output thereof based on an input signal, the output stage...
Leadframe and mold compound interlock in packaged semiconductor device
An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined...
Method for reducing stress concentrations on a semiconductor wafer by
surface laser treatment
A method for treating an area of a semiconductor wafer surface with a laser for reducing stress concentrations is disclosed. The wafer treatment method discloses...
Integrated circuit package having integrated faraday shield
A packaged integrated circuit (IC) (100) includes a first substrate (110) including a first plurality of layers and first circuit coupling features (112) at an...
Plasma treatment and repair processes for reducing sidewall damage in
A method of forming an interconnect structure for an integrated circuit, including the steps of providing a substrate and forming a dielectric stack on the...
Integrated circuit having a top side wafer contact and a method of
The present invention provides an integrated circuit and a method of manufacture therefore therefor. The integrated circuit (100, 1000), in one embodiment...
Portable solution detector for identifying chemical solutions including
from chemical spills
A detector and detection method for identifying unknown chemical solutions following chemical spills includes a specific gravity detector including a detector...
Paced trace transmission
The trace interface and the trace receiver may be synchronized by the trace receiver controlling the pace of trace generation. The interface generates a clock...
Method and system of profiling applications that use virtual memory
A method and system of profiling applications that use virtual memory. At least some of the illustrative embodiments are methods comprising executing a traced...
Boundary scan path method and system with functional and non-functional
scan cell memories
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a...
Device and system for controlling parallel power sources coupled to a load
A device and system for controlling current from plural parallel power sources having inrush current hot-swapping capabilities to a load are disclosed. The...
Providing information associated with a cache
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
ATA HDD interface for personal media player with increased data transfer
This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media...
System and method for enhancing I2C bus data rate
A system for, and method of, enhancing I2C bus data rate and an electronic assembly including the system or the method. In one embodiment, the system includes:...
Interference canceller tap sharing in a communications transceiver
A novel mechanism for sharing filter taps across a plurality of interference cancellers. Each interference canceller may be directed to impairment, such as...
Baseline wander correction for communication receivers
A novel and useful baseline wander correction mechanism for use with transformer coupled baseband communication receivers. Parametric estimation of the...
Lubricating micro-machined devices using fluorosurfactants
A method of lubricating MEMS devices using fluorosurfactants 42. Micro-machined devices, such as a digital micro-mirror device (DMD.TM.) 940, which make repeated...
Content-dependent scan rate converter with adaptive noise reduction
A content-dependent scan rate converter with adaptive noise reduction that provides a highly integrated, implementation efficient de-interlacer. By identifying...