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Patent # Description
US-7,814,386 Built in self test for input/output characterization
A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage...
US-7,814,258 PCI bus burst transfer sizing
Various apparatuses, methods and systems for specifying memory transaction sizes on a PCI bus are disclosed herein. For example, some embodiments of the present...
US-7,813,601 Reconfigurable optical add/drop multiplexer
Disclosed is an add-drop multiplexer that receives an optical signal having a plurality of channels. The multiplexer spatially separates the channels, and a...
US-7,813,567 Method of CABAC significance MAP decoding suitable for use on VLIW data processors
This invention decodes a next significance symbol using a selected context. The invention operates in a loop for each symbol decode for a whole block until the...
US-7,813,462 Method of defining semiconductor fabrication process utilizing transistor inverter delay period
A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on...
US-7,813,198 System and method for reading memory
One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to...
US-7,813,193 Ferroelectric memory brake for screening and repairing bits
A method (300) of identifying failing bits in a ferroelectric memory device including at least one ferroelectric capacitor includes (302) writing same state data...
US-7,813,177 Analog single-poly EEPROM incorporating two tunneling regions for programming the memory device
A single-poly EEPROM memory device comprises a control gate isolated within a well of a first conductivity type in a semiconductor body of a second conductivity...
US-7,813,068 Degauss control for magnetic disk-drive preamplifier
One embodiment of the invention includes a preamplifier system for a magnetic disk-drive. The system includes a current distributor configured to generate a...
US-7,812,830 Touch-initiated power-saving clock system and method for touch screen controller
A touch screen controller circuit (1A) including means for generating a first and second levels of a pen touch signal (PENTOUCH) if a touch point (Q) is present...
US-7,812,649 Low power, power on reset circuit with accurate supply voltage detection
The power on reset circuit includes: a comparator; a resistor string having a first end coupled to a first supply node of the comparator, a first tap point node...
US-7,812,646 Low-leakage switch for sample and hold
An integrated electronic device includes a sample and hold stage. The sample and hold stage has a sampling capacitor (C) for an input voltage at an input node...
US-7,812,401 MOS device and process having low resistance silicide interface using additional source/drain implant
An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source...
US-7,811,942 Tri-layer plasma etch resist rework
Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch...
US-7,811,917 Systems and methods for maintaining performance at a reduced power
Systems and methods are provided for maintaining performance of an integrated circuit at a reduced power. The systems and methods employ a performance monitor...
US-7,811,893 Shallow trench isolation stress adjuster for MOS transistor
The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an...
US-7,811,882 Hardmask manufacture in ferroelectric capacitors
A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming...
US-7,810,001 Parallel test system
A method and a system for defining groups of tests that may be concurrently performed or overlapped are provided. Channel-independent test groups are determined...
US-7,809,987 Accepting link ID upon supplied and sampled bits matching
An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality...
US-7,809,961 Standby mode for power management
An apparatus and method for controlling standby mode in an electronic device. In standby mode, power and clock signals are reduced or stopped to conserve power....
US-7,809,934 Security measures for preventing attacks that use test mechanisms
A system comprising processing logic adapted to determine a type of boot performed by the system and a storage coupled to the processing logic. The processing...
US-7,809,927 Computation parallelization in software reconfigurable all digital phase lock loop
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit...
US-7,809,889 High performance multilevel cache hierarchy
A digital system is provided with a hierarchical memory system having at least a first and second level cache and a higher level memory. If a requested data item...
US-7,809,346 Digital audio receiver with reduced AM interference
A digital audio system including a digital audio amplifier with reduced AM interference. The digital audio amplifier includes a pulse-width-modulation (PWM)...
US-7,809,338 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using wideband modulation...
A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF...
US-7,809,188 Digital camera and method
Digital camera contrast enhancement with piecewise-linear transform with lower and upper cutoffs for the transform determined from histogram analysis with a...
US-7,809,082 GMSK/EDGE modulator with switching transition smoothing
To minimize abrupt changes in modulated signal amplitude when switching between modulation types in a multi-modulation system, a "smoothing" circuit is used....
US-7,808,449 Method and system for multi-channel viewing applications
Methods and apparatus for rendering plural channels on a common display are provided. In a method embodiment, a method for allowing sharing of a display by a...
US-7,808,327 Method and apparatus to provide digitally controlled crystal oscillators
Methods and systems to provide digitally controlled crystal oscillators are disclosed. One example method includes determining a state of an oscillator system...
US-7,808,325 System and method for frequency pushing/pulling compensation
A system and method for frequency pushing/pulling compensation in phase-locked loops including a method for cancelling frequency push/pull in an oscillator of a...
US-7,808,266 Method and apparatus for evaluating the effects of stress on an RF oscillator
Apparatus and methods are disclosed for evaluating degradation of a transistor in a cross coupled pair of an RF oscillator independently. A MOS device can be...
US-7,808,264 Isolated conductive leads extending across to opposite sides of IC
An integrated circuit includes switching circuits for selectively connecting the bond pads to functional core logic and isolating the bond pads from second...
US-7,808,244 System and method for determining state of charge of a battery utilizing initial voltage and current...
A processor executes a program to calculate values of the internal resistance R of a battery and updates a database of parameters defining the dependence of...
US-7,808,218 Duty-cycle independent current limit for a power regulator
One embodiment of the invention includes a power regulator system. The system comprises an error amplifier that provides an error voltage based on a comparison...
US-7,808,113 Flip chip semiconductor device having workpiece adhesion promoter layer for improved underfill adhesion
A semiconductor device assembly (200) includes a workpiece (205) having a surface including a die attach region corresponding to regions under an integrated...
US-7,808,088 Semiconductor device with improved high current performance
A semiconductor device comprises a die having a first surface and a second surface, a first leadframe connected to the first surface and the second surface, and...
US-7,808,071 Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of...
One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The...
US-7,807,978 Divergent charged particle implantation for improved transistor symmetry
The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for...
US-7,807,540 Back end thin film capacitor having plates at thin film resistor and first metallization layer levels
An integrated circuit back end capacitor structure includes a first dielectric layer on a substrate, a thin film bottom plate on the first dielectric layer, and...
US-7,807,522 Lanthanide series metal implant to control work function of metal gate electrodes
Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal nitride is formed above a...
US-7,807,343 EDA methodology for extending ghost feature beyond notched active to improve adjacent gate CD control using a...
In accordance with various embodiments, semiconductor devices and methods of forming semiconductor devices having non-rectangular active regions are provided. An...
US-7,805,708 Automatic tool to eliminate conflict cache misses
This invention simulates program to create a conflict graph of the cache accesses. The conflict graph is used to relay out relocatable functions to minimize...
US-7,805,647 System and method for testing a plurality of circuits
A system for, and method of, testing a plurality of circuits, which may be unsingulated die on a wafer. In one embodiment, the system includes: (1) a test data...
US-7,805,644 Multiple pBIST controllers
A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test...
US-7,805,122 Local oscillator with non-harmonic ratio between oscillator and RF frequencies using digital mixing and...
A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF...
US-7,804,702 Ferroelectric memory cell with access transmission gate
One embodiment relates to an integrated circuit that includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric capacitor...
US-7,804,699 Segmented ternary content addressable memory search architecture
A segmented ternary content addressable memory (TCAM) search architecture is disclosed. In one embodiment, a TCAM device with a row of TCAM cells includes a...
US-7,804,433 Methods and apparatus for error cancelation in calibrated current sources
Methods and apparatus for error cancelation in calibrated current sources are disclosed. In an example, a digital to analog converter to convert digital bits...
US-7,804,337 Method and apparatus of SFDR enhancement
A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and...
US-7,804,336 Track-and-hold circuit with low distortion
A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input...
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