Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: texas instruments





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,737,679 Poly phase solid state watt hour meters
An electronic energy meter includes a first sigma delta modulator having an electrically isolated digital data output. A power supply stage coupled to a first...
US-7,737,671 System and method for implementing high-resolution delay
A system and method is provided for providing a deadband switching time delay. One embodiment of the present invention includes a switching regulator system. The...
US-7,737,016 Two-print two-etch method for enhancement of CD control using ghost poly
According to various embodiments, two-print two-etch methods and devices are disclosed that can be used to form features, such as ghost features, on a substrate....
US-7,737,015 Formation of fully silicided gate with oxide barrier on the source/drain silicide regions
A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a...
US-7,736,986 Integrated stacked capacitor and method of fabricating same
An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide, a second capacitor film (48) and a first dielectric (26)...
US-7,736,983 High threshold NMOS source-drain formation with As, P and C to reduce damage
Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in...
US-7,736,961 High voltage depletion FET employing a channel stopping implant
A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well...
US-7,736,026 Lamp reflector cooling air deflector
To improve the cooling efficiency and ensure uniform cooling of all portions of the inside back surface of the reflector, a deflector (108) has been developed....
US-7,735,056 Automated circuit design dimension change responsive to low contrast condition determination in photomask phase...
The present application is directed to methods of forming a phase pattern for an integrated circuit feature described in a design database as having a first...
US-7,734,971 Scan output connection in tap and scan test port
Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves...
US-7,734,044 Method and apparatus for synchronous stream cipher encryption with reserved codes
A method and apparatus for a signal encryption device constructed to perform synchronous stream cipher encryption for a sequence of input words with restricted...
US-7,733,763 Memory-efficient ADSL transmission in the presence of TCM-ISDN interferers
A method of communicating data across a channel that experiences near-end cross talk (NEXT) interference and far-end cross talk (FEXT) interference in alternate...
US-7,733,686 Pulse width control for read and write assist for SRAM circuits
An exemplary system and methods implementing pulse width control in SRAM bit cell arrays that vary in size are described.
US-7,733,682 Plateline driver for a ferroelectric memory
One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory...
US-7,733,424 Method and apparatus for analog graphics sample clock frequency verification
A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for sampling...
US-7,733,261 Hybrid analog to digital converter circuit and method
A hybrid analog to digital converter circuit for a feedback input to a digital controller of a power supply includes a high resolution, analog to digital...
US-7,733,180 Amplifier for driving external capacitive loads
An apparatus having a zero-pole that is dependant on an equivalent series resistance (ESR) and a load is provided. The apparatus comprises an amplifier stage...
US-7,733,179 Combination trim and CMFB circuit and method for differential amplifiers
A differential amplifier (10-1,2) includes an input stage (7) including first (M1) and second (M2) input transistors and first (4A) and second (4B) load devices....
US-7,733,177 Method and system for calculating the pre-inverse of a nonlinear system
An apparatus is provided to determine pre-distortion for a nonlinear system. The apparatus comprises a datapath and a power amplifier. The datapath employs...
US-7,733,174 Feedback controlled power limiting for signal amplifiers
An apparatus is provided. The apparatus includes an amplifier, differential amplifiers, and FETs. The amplifier has an intermediate node and an output node, and...
US-7,733,169 Slew rate and settling time improvement circuitry and method for 3-stage amplifier
An operational amplifier (1B) amplifies an input signal (Vin) to produce an output signal (Vout), and includes a 3-stage amplifier (1C) including a first...
US-7,733,151 Operating clock generation system and method for audio applications
A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency...
US-7,733,135 High side boosted gate drive circuit
A high-side boosted gate drive circuit is disclosed. In a particular example, an output driver is described, comprising a switching device configured to...
US-7,733,110 Parallel scan distributors and collectors and process of testing integrated circuits
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-7,733,072 Step-down/step-up DC/DC converter apparatus and method with inductor current threshold value adjusting
The invention provides a switching power supply device that can restrain the variation in the ripple of the output voltage corresponding to the variation in the...
US-7,732,863 Laterally diffused MOSFET
A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS...
US-7,732,345 Method for using a modified post-etch clean rinsing agent
The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a...
US-7,732,324 Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer
One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor...
US-7,732,313 FUSI integration method using SOG as a sacrificial planarization layer
A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from...
US-7,732,312 FUSI integration method using SOG as a sacrificial planarization layer
A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from...
US-7,732,284 Post high-k dielectric/metal gate clean
A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal...
US-7,732,225 Method for measuring contamination in liquids at PPQ levels
A method of manufacturing a semiconductor device includes placing a sample of a liquid chemical containing a contaminant on a substantially impurity-free surface...
US-7,730,377 Layered decoding of low density parity check (LDPC) codes
A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a...
US-7,730,374 Self test circuit for a semiconductor intergrated circuit
A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105...
US-7,730,361 Aggregation of error messaging in multifunction PCI express devices
A method of aggregating events in a PCIe (Peripheral Component Interconnect Express) multifunction device minimizes reported error messages, where several...
US-7,730,248 Interrupt morphing and configuration, circuits, systems and processes
An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in...
US-7,729,446 System and method for digitally correcting a non-linear element using a multiply partitioned architecture for...
Digital predistortion system, methods and circuitry for linearizing a non-linear element using a multiply partitioned architecture that first addresses long or...
US-7,729,308 Optimal allocation of resources in a wireless communication system
Optimal allocation of a number of sub carriers to applications having diverse QoS requirements and executing on terminal devices (e.g., mobile stations). A base...
US-7,729,156 Cycling to mitigate imprint in ferroelectric memories
The method includes storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the...
US-7,728,840 Sliding data buffering for image processing
A method for managing image processing data buffers for processes having overlap input data between iterations includes loading a data buffer with an initial...
US-7,728,749 Multi-mode digital-to-analog converter
Various apparatuses, methods and systems for a multi-mode DAC with selectable output range, granularity and offset and controlled slew rate are disclosed herein....
US-7,728,575 Methods and apparatus for higher-order correction of a bandgap voltage reference
Methods and apparatus for higher-order correction of bandgap voltage references are disclosed. An example bandgap voltage reference circuit disclosed herein...
US-7,728,436 Method for selective deposition of a thin self-assembled monolayer
A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is...
US-7,728,349 Low capacitance SCR with trigger element
A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element. A first well region of a first conductivity...
US-7,727,885 Reduction of punch-thru defects in damascene processing
A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is...
US-7,727,842 Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related...
A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative...
US-7,727,838 Method to improve transistor Tox using high-angle implants with no additional masks
A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor...
US-7,727,801 Apparatus for improved power distribution in wirebond semiconductor packages
A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and...
US-7,725,791 Single lead alternating TDI/TMS DDR JTAG input
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface...
US-7,725,790 Selectable dual mode test access port method and apparatus
A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.