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Patent # Description
US-7,733,424 Method and apparatus for analog graphics sample clock frequency verification
A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for sampling...
US-7,733,261 Hybrid analog to digital converter circuit and method
A hybrid analog to digital converter circuit for a feedback input to a digital controller of a power supply includes a high resolution, analog to digital...
US-7,733,180 Amplifier for driving external capacitive loads
An apparatus having a zero-pole that is dependant on an equivalent series resistance (ESR) and a load is provided. The apparatus comprises an amplifier stage...
US-7,733,179 Combination trim and CMFB circuit and method for differential amplifiers
A differential amplifier (10-1,2) includes an input stage (7) including first (M1) and second (M2) input transistors and first (4A) and second (4B) load devices....
US-7,733,177 Method and system for calculating the pre-inverse of a nonlinear system
An apparatus is provided to determine pre-distortion for a nonlinear system. The apparatus comprises a datapath and a power amplifier. The datapath employs...
US-7,733,174 Feedback controlled power limiting for signal amplifiers
An apparatus is provided. The apparatus includes an amplifier, differential amplifiers, and FETs. The amplifier has an intermediate node and an output node, and...
US-7,733,169 Slew rate and settling time improvement circuitry and method for 3-stage amplifier
An operational amplifier (1B) amplifies an input signal (Vin) to produce an output signal (Vout), and includes a 3-stage amplifier (1C) including a first...
US-7,733,151 Operating clock generation system and method for audio applications
A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency...
US-7,733,135 High side boosted gate drive circuit
A high-side boosted gate drive circuit is disclosed. In a particular example, an output driver is described, comprising a switching device configured to...
US-7,733,110 Parallel scan distributors and collectors and process of testing integrated circuits
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-7,733,072 Step-down/step-up DC/DC converter apparatus and method with inductor current threshold value adjusting
The invention provides a switching power supply device that can restrain the variation in the ripple of the output voltage corresponding to the variation in the...
US-7,732,863 Laterally diffused MOSFET
A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS...
US-7,732,345 Method for using a modified post-etch clean rinsing agent
The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a...
US-7,732,324 Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer
One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor...
US-7,732,313 FUSI integration method using SOG as a sacrificial planarization layer
A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from...
US-7,732,312 FUSI integration method using SOG as a sacrificial planarization layer
A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from...
US-7,732,284 Post high-k dielectric/metal gate clean
A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal...
US-7,732,225 Method for measuring contamination in liquids at PPQ levels
A method of manufacturing a semiconductor device includes placing a sample of a liquid chemical containing a contaminant on a substantially impurity-free surface...
US-7,730,377 Layered decoding of low density parity check (LDPC) codes
A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a...
US-7,730,374 Self test circuit for a semiconductor intergrated circuit
A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105...
US-7,730,361 Aggregation of error messaging in multifunction PCI express devices
A method of aggregating events in a PCIe (Peripheral Component Interconnect Express) multifunction device minimizes reported error messages, where several...
US-7,730,248 Interrupt morphing and configuration, circuits, systems and processes
An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in...
US-7,729,446 System and method for digitally correcting a non-linear element using a multiply partitioned architecture for...
Digital predistortion system, methods and circuitry for linearizing a non-linear element using a multiply partitioned architecture that first addresses long or...
US-7,729,308 Optimal allocation of resources in a wireless communication system
Optimal allocation of a number of sub carriers to applications having diverse QoS requirements and executing on terminal devices (e.g., mobile stations). A base...
US-7,729,156 Cycling to mitigate imprint in ferroelectric memories
The method includes storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the...
US-7,728,840 Sliding data buffering for image processing
A method for managing image processing data buffers for processes having overlap input data between iterations includes loading a data buffer with an initial...
US-7,728,749 Multi-mode digital-to-analog converter
Various apparatuses, methods and systems for a multi-mode DAC with selectable output range, granularity and offset and controlled slew rate are disclosed herein....
US-7,728,575 Methods and apparatus for higher-order correction of a bandgap voltage reference
Methods and apparatus for higher-order correction of bandgap voltage references are disclosed. An example bandgap voltage reference circuit disclosed herein...
US-7,728,436 Method for selective deposition of a thin self-assembled monolayer
A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is...
US-7,728,349 Low capacitance SCR with trigger element
A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element. A first well region of a first conductivity...
US-7,727,885 Reduction of punch-thru defects in damascene processing
A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is...
US-7,727,842 Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related...
A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative...
US-7,727,838 Method to improve transistor Tox using high-angle implants with no additional masks
A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor...
US-7,727,801 Apparatus for improved power distribution in wirebond semiconductor packages
A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and...
US-7,725,791 Single lead alternating TDI/TMS DDR JTAG input
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface...
US-7,725,790 Selectable dual mode test access port method and apparatus
A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an...
US-7,725,687 Register file bypass with optional results storage and separate predication register file in a VLIW processor
This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register...
US-7,725,678 Method and apparatus for producing an index vector for use in performing a vector permute operation
A method for generating a permutation index vector includes receiving a condition vector and performing an index generation function using the condition vector...
US-7,725,522 High-speed integer multiplier unit handling signed and unsigned operands and occupying a small area
A high-speed integer multiplier unit multiplying operands, wherein each operand can be either signed or unsigned. Type data is received for each operand which...
US-7,724,832 MIMO decoding
In MIMO wireless communications employing LMMSE receiver, the symbols transmitted through a transmit antenna are estimated at the receiver in the presence of...
US-7,724,814 Methods and apparatus for decision feedback equalization with dithered updating
Methods and apparatus for decision feedback equalization with dithered updating are disclosed. An example method to equalize a received signal sample...
US-7,724,762 Efficient transmission of packets within a network communication device
Systems and methods for efficient transmission of packets within a network communication device are described herein. Some illustrative embodiments include a...
US-7,724,754 Device, system and/or method for managing packet congestion in a packet switching network
A network infrastructure device includes a receiver operable to receive packets when operably connected to a communication network; and a processor cooperatively...
US-7,724,432 Rear-projection screen for projection video display system, method of rear-projection collimation and...
Various embodiments of a rear-projection screen, a method of rear-projection collimation and a projection video display (PVD) system. In one embodiment, a...
US-7,724,166 A/D converter
An apparatus is provided. The apparatus comprises a sample and hold circuit, a converter, and an adjustable current circuit. The sample and hold circuit is...
US-7,724,101 Crystal oscillator circuit with amplitude control
A crystal oscillator circuit includes a capacitive load stage coupled to a crystal; an amplifier stage including an amplifying transistor coupled to the crystal...
US-7,724,042 Reducing power consumption in an amplification stage driving a sample and hold circuit while maintaining linearity
An input signal to be sampled by a sample and hold circuit is amplified separately by two amplifiers. The output of the first amplifier is provided to a boost...
US-7,724,014 On-chip servo loop integrated circuit system test circuitry and method
Internal servo loop circuitry is included on the same chip (10C) with an ADC (10B). Automatic test equipment (12) operates with the internal servo loop circuitry...
US-7,724,012 Contactless testing of wafer characteristics
Systems and methods are provided for contactless testing of a wafer containing at least one integrated circuit. A test component responds to a supply voltage to...
US-7,723,232 Full backside etching for pressure sensing silicon
The formation of a semiconductor sensing device is disclosed, where the device can be used to sense pressure, for example. The device is formed by etching the...
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