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Patent # Description
US-7,745,238 Monitoring of temperature variation across wafers during processing
A method of measuring temperature across wafers during semiconductor processing includes the step of providing a correlation between a peak wafer temperature...
US-7,745,067 Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements
Provide is a method of making a mask layout, an integrated circuit device made by a method, a computer readable medium, and a mask for forming contact holes. The...
US-7,743,384 Method and system for implementing an interrupt handler
A system for interrupt handling in Java is provided that includes an execution flow class, an execution flow scheduler, a Java virtual machine (JVM), and an...
US-7,743,172 Die-to-die interconnect interface and protocol for stacked semiconductor dies
A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit...
US-7,742,638 Content-transformation power management of a mobile display
The present invention provides a video server. In one embodiment, the video server includes a perceptual analyzer configured to analyze frames of a video...
US-7,742,619 Image watermarking based on sequency and wavelet transforms
This invention is a new approach for the image watermarking in the wavelet transform domain based on sequency of the host and watermark image. For each sub-band...
US-7,742,520 Equalization circuit
An equalization circuit that allows particularly for lowpass filtering by transmission lines comprises a compensating equalizer controlled according to whether...
US-7,742,326 8T SRAM cell with higher voltage on the read WL
The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry...
US-7,742,229 Single prism aberration compensation
System and method for utilizing two prisms spatially separated is provided. The two prisms spatially separated allows the two prisms typically found in a TIR...
US-7,741,916 Reconfigurable circuit to compensate for a low noise amplification input matching variation and a method for...
A method for changing an effective capacitance of an amplifier circuit having a match transistor and a coupled cascode transistor includes changing an on-state...
US-7,741,914 Amplifier system with dynamically-adjusted supply voltage
An amplifier system may include an output stage configured to provide an amplified output signal at an output thereof based on an input signal, the output stage...
US-7,741,704 Leadframe and mold compound interlock in packaged semiconductor device
An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined...
US-7,741,701 Method for reducing stress concentrations on a semiconductor wafer by surface laser treatment
A method for treating an area of a semiconductor wafer surface with a laser for reducing stress concentrations is disclosed. The wafer treatment method discloses...
US-7,741,567 Integrated circuit package having integrated faraday shield
A packaged integrated circuit (IC) (100) includes a first substrate (110) including a first plurality of layers and first circuit coupling features (112) at an...
US-7,741,224 Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics
A method of forming an interconnect structure for an integrated circuit, including the steps of providing a substrate and forming a dielectric stack on the...
US-7,741,205 Integrated circuit having a top side wafer contact and a method of manufacture therefor
The present invention provides an integrated circuit and a method of manufacture therefore therefor. The integrated circuit (100, 1000), in one embodiment...
US-7,739,902 Portable solution detector for identifying chemical solutions including from chemical spills
A detector and detection method for identifying unknown chemical solutions following chemical spills includes a specific gravity detector including a detector...
US-7,739,669 Paced trace transmission
The trace interface and the trace receiver may be synchronized by the trace receiver controlling the pace of trace generation. The interface generates a clock...
US-7,739,668 Method and system of profiling applications that use virtual memory
A method and system of profiling applications that use virtual memory. At least some of the illustrative embodiments are methods comprising executing a traced...
US-7,739,569 Boundary scan path method and system with functional and non-functional scan cell memories
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a...
US-7,739,525 Device and system for controlling parallel power sources coupled to a load
A device and system for controlling current from plural parallel power sources having inrush current hot-swapping capabilities to a load are disclosed. The...
US-7,739,453 Providing information associated with a cache
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
US-7,739,440 ATA HDD interface for personal media player with increased data transfer throughput
This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media...
US-7,739,435 System and method for enhancing I2C bus data rate
A system for, and method of, enhancing I2C bus data rate and an electronic assembly including the system or the method. In one embodiment, the system includes:...
US-7,738,655 Interference canceller tap sharing in a communications transceiver
A novel mechanism for sharing filter taps across a plurality of interference cancellers. Each interference canceller may be directed to impairment, such as...
US-7,738,567 Baseline wander correction for communication receivers
A novel and useful baseline wander correction mechanism for use with transformer coupled baseband communication receivers. Parametric estimation of the...
US-7,738,154 Lubricating micro-machined devices using fluorosurfactants
A method of lubricating MEMS devices using fluorosurfactants 42. Micro-machined devices, such as a digital micro-mirror device (DMD.TM.) 940, which make repeated...
US-7,738,038 Content-dependent scan rate converter with adaptive noise reduction
A content-dependent scan rate converter with adaptive noise reduction that provides a highly integrated, implementation efficient de-interlacer. By identifying...
US-7,737,989 System and method for computing color correction coefficients
System and method for computing coefficients for color correcting rendered colors used in displaying images. A preferred embodiment comprises measuring color...
US-7,737,986 Methods and systems for tiling video or still image data
The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing...
US-7,737,791 Spread spectrum clocking in fractional-N PLL
In applications that use fractional-N phase locked loops (PLLs), the use of spread spectrum clocking (SSC) to reduced electromagnetic interference (EMI) would be...
US-7,737,747 Scheme for controlling rise-fall times in signal transitions
A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a...
US-7,737,717 Current-voltage-based method for evaluating thin dielectrics based on interface traps
A method for evaluating gate dielectrics (100) includes providing a test structure (101). The test structure includes a gate stack that includes a gate electrode...
US-7,737,679 Poly phase solid state watt hour meters
An electronic energy meter includes a first sigma delta modulator having an electrically isolated digital data output. A power supply stage coupled to a first...
US-7,737,671 System and method for implementing high-resolution delay
A system and method is provided for providing a deadband switching time delay. One embodiment of the present invention includes a switching regulator system. The...
US-7,737,016 Two-print two-etch method for enhancement of CD control using ghost poly
According to various embodiments, two-print two-etch methods and devices are disclosed that can be used to form features, such as ghost features, on a substrate....
US-7,737,015 Formation of fully silicided gate with oxide barrier on the source/drain silicide regions
A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a...
US-7,736,986 Integrated stacked capacitor and method of fabricating same
An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide, a second capacitor film (48) and a first dielectric (26)...
US-7,736,983 High threshold NMOS source-drain formation with As, P and C to reduce damage
Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in...
US-7,736,961 High voltage depletion FET employing a channel stopping implant
A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well...
US-7,736,026 Lamp reflector cooling air deflector
To improve the cooling efficiency and ensure uniform cooling of all portions of the inside back surface of the reflector, a deflector (108) has been developed....
US-7,735,056 Automated circuit design dimension change responsive to low contrast condition determination in photomask phase...
The present application is directed to methods of forming a phase pattern for an integrated circuit feature described in a design database as having a first...
US-7,734,971 Scan output connection in tap and scan test port
Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves...
US-7,734,044 Method and apparatus for synchronous stream cipher encryption with reserved codes
A method and apparatus for a signal encryption device constructed to perform synchronous stream cipher encryption for a sequence of input words with restricted...
US-7,733,763 Memory-efficient ADSL transmission in the presence of TCM-ISDN interferers
A method of communicating data across a channel that experiences near-end cross talk (NEXT) interference and far-end cross talk (FEXT) interference in alternate...
US-7,733,686 Pulse width control for read and write assist for SRAM circuits
An exemplary system and methods implementing pulse width control in SRAM bit cell arrays that vary in size are described.
US-7,733,682 Plateline driver for a ferroelectric memory
One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory...
US-7,733,424 Method and apparatus for analog graphics sample clock frequency verification
A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for sampling...
US-7,733,261 Hybrid analog to digital converter circuit and method
A hybrid analog to digital converter circuit for a feedback input to a digital controller of a power supply includes a high resolution, analog to digital...
US-7,733,180 Amplifier for driving external capacitive loads
An apparatus having a zero-pole that is dependant on an equivalent series resistance (ESR) and a load is provided. The apparatus comprises an amplifier stage...
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