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Patent # Description
US-7,730,361 Aggregation of error messaging in multifunction PCI express devices
A method of aggregating events in a PCIe (Peripheral Component Interconnect Express) multifunction device minimizes reported error messages, where several...
US-7,730,248 Interrupt morphing and configuration, circuits, systems and processes
An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in...
US-7,729,446 System and method for digitally correcting a non-linear element using a multiply partitioned architecture for...
Digital predistortion system, methods and circuitry for linearizing a non-linear element using a multiply partitioned architecture that first addresses long or...
US-7,729,308 Optimal allocation of resources in a wireless communication system
Optimal allocation of a number of sub carriers to applications having diverse QoS requirements and executing on terminal devices (e.g., mobile stations). A base...
US-7,729,156 Cycling to mitigate imprint in ferroelectric memories
The method includes storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the...
US-7,728,840 Sliding data buffering for image processing
A method for managing image processing data buffers for processes having overlap input data between iterations includes loading a data buffer with an initial...
US-7,728,749 Multi-mode digital-to-analog converter
Various apparatuses, methods and systems for a multi-mode DAC with selectable output range, granularity and offset and controlled slew rate are disclosed herein....
US-7,728,575 Methods and apparatus for higher-order correction of a bandgap voltage reference
Methods and apparatus for higher-order correction of bandgap voltage references are disclosed. An example bandgap voltage reference circuit disclosed herein...
US-7,728,436 Method for selective deposition of a thin self-assembled monolayer
A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is...
US-7,728,349 Low capacitance SCR with trigger element
A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element. A first well region of a first conductivity...
US-7,727,885 Reduction of punch-thru defects in damascene processing
A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is...
US-7,727,842 Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related...
A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative...
US-7,727,838 Method to improve transistor Tox using high-angle implants with no additional masks
A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor...
US-7,727,801 Apparatus for improved power distribution in wirebond semiconductor packages
A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and...
US-7,725,791 Single lead alternating TDI/TMS DDR JTAG input
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface...
US-7,725,790 Selectable dual mode test access port method and apparatus
A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an...
US-7,725,687 Register file bypass with optional results storage and separate predication register file in a VLIW processor
This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register...
US-7,725,678 Method and apparatus for producing an index vector for use in performing a vector permute operation
A method for generating a permutation index vector includes receiving a condition vector and performing an index generation function using the condition vector...
US-7,725,522 High-speed integer multiplier unit handling signed and unsigned operands and occupying a small area
A high-speed integer multiplier unit multiplying operands, wherein each operand can be either signed or unsigned. Type data is received for each operand which...
US-7,724,832 MIMO decoding
In MIMO wireless communications employing LMMSE receiver, the symbols transmitted through a transmit antenna are estimated at the receiver in the presence of...
US-7,724,814 Methods and apparatus for decision feedback equalization with dithered updating
Methods and apparatus for decision feedback equalization with dithered updating are disclosed. An example method to equalize a received signal sample...
US-7,724,762 Efficient transmission of packets within a network communication device
Systems and methods for efficient transmission of packets within a network communication device are described herein. Some illustrative embodiments include a...
US-7,724,754 Device, system and/or method for managing packet congestion in a packet switching network
A network infrastructure device includes a receiver operable to receive packets when operably connected to a communication network; and a processor cooperatively...
US-7,724,432 Rear-projection screen for projection video display system, method of rear-projection collimation and...
Various embodiments of a rear-projection screen, a method of rear-projection collimation and a projection video display (PVD) system. In one embodiment, a...
US-7,724,166 A/D converter
An apparatus is provided. The apparatus comprises a sample and hold circuit, a converter, and an adjustable current circuit. The sample and hold circuit is...
US-7,724,101 Crystal oscillator circuit with amplitude control
A crystal oscillator circuit includes a capacitive load stage coupled to a crystal; an amplifier stage including an amplifying transistor coupled to the crystal...
US-7,724,042 Reducing power consumption in an amplification stage driving a sample and hold circuit while maintaining linearity
An input signal to be sampled by a sample and hold circuit is amplified separately by two amplifiers. The output of the first amplifier is provided to a boost...
US-7,724,014 On-chip servo loop integrated circuit system test circuitry and method
Internal servo loop circuitry is included on the same chip (10C) with an ADC (10B). Automatic test equipment (12) operates with the internal servo loop circuitry...
US-7,724,012 Contactless testing of wafer characteristics
Systems and methods are provided for contactless testing of a wafer containing at least one integrated circuit. A test component responds to a supply voltage to...
US-7,723,232 Full backside etching for pressure sensing silicon
The formation of a semiconductor sensing device is disclosed, where the device can be used to sense pressure, for example. The device is formed by etching the...
US-7,723,199 Method for cleaning post-etch noble metal residues
A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a...
US-7,723,173 Low temperature polysilicon oxide process for high-K dielectric/metal gate stack
A method for preventing oxidation in a high-k dielectric/metal gate stack in the manufacture of an integrated circuit device is disclosed. In a detailed...
US-7,723,129 Power semiconductor devices having integrated inductor
An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a...
US-7,721,267 Efficient protocol for encoding software pipelined loop when PC trace is enabled
A software pipelined loop tracing method involves inhibiting an output of trace data at a start of a software pipelined loop (SPLOOP). A skip in an output trace...
US-7,721,263 Debug event instruction
Last stall information is transmitted if the last stall standing function is enabled, one of the stall elements was active during the last clock cycle, no stall...
US-7,721,054 Speculative data loading using circular addressing or simulated circular addressing
This invention prevents illegal memory address faults on speculative data loads. Circular addressing of the address pointer limits memory access to a range of...
US-7,720,670 Saving resources by deducing the total prediction events
While PC trace is on, and the trace is in predication or general event profiling mode, trace hardware captures events in each cycle. Trace hardware inserts this...
US-7,720,496 Comma free codes for fast cell search using tertiary synchronization channel
A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a...
US-7,720,186 Plural circuit selection using role reversing control inputs
Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode...
US-7,720,180 Tracking error detection and correction methods and apparatus
The objective of this invention is to perform high-precision tracking error detection and tracking control using digital circuitry at relatively low speed and...
US-7,720,151 Motion estimation using early decision for goodness of estimation with quick convergence feedback
This invention is a method for speeding up block matching based motion estimation for video encoder. The invention 1) calculates statistics for a candidate...
US-7,720,130 Efficient receiver architecture for transmit diversity techniques
Transmit diversity (TD) has become a common technique used in modern wireless communications systems to improve performance. TD uses multiple antennas (e.g., 110...
US-7,720,104 Method to improve sensitivity of decoding time of a global positioning system receiver at low signal to noise ratio
A method and an apparatus to improve sensitivity of decoding time of a global positioning system (GPS) receiver at low signal to noise ratio is disclosed. In one...
US-7,719,766 Illumination source and method therefor
An illumination source and a method therefor. A light source includes a light circuit configured to process light and direct light, and a lighting element...
US-7,719,740 Hinge memory mitigation system and method
Provided are a system and method for reducing failures due to hinge memory. The method, in one embodiment, includes providing a torsional element having an...
US-7,719,369 Sigma delta digital to analog converter with wide output range and improved linearity
A sigma delta DAC using a single DAC to generate a first analog quantity portion and a second analog quantity portion, having a strength respectively...
US-7,719,365 Method and apparatus for reducing silicon area of a phase lock loop (PLL) filter without a noise penalty
In a method and system for filtering an input signal with a filter included in a phase locked loop (PLL), a unidirectional feedback path is configured from an...
US-7,719,332 Glitch reduced delay lock loop circuits and methods for using such
Delay lock loop circuits are described, which may include two or more delay stages that each includes a plurality of selectable delay elements. A reference...
US-7,719,299 Process and temperature insensitive flicker noise monitor circuit
In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit...
US-7,719,245 Methods and apparatus to provide self-tracking pre-driver controls
Methods and apparatus for a self-tracking high-side pre-driver control are described. In an example, a method is described comprising charging a first terminal...
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