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Automatic halting of a processor in debug mode due to reset
Disclosed herein is a system and method of operating a processor before and after a reset has been asserted. Prior to a reset being asserted the processor...
Image preprocessing with selective lowpass filtering from motion
Preprocessing for motion-compensated video encoding such as MPEG includes lowpass filtering, temporal (310) and/or spatial (312), locally per pixel in response...
Method and apparatus for regenerative based interference cancellation
within a communication system
Interference cancellation is performed in a communication system. A signal associated with the users is received to produce a received signal. A set of...
Crest factor reduction processor for wireless communications
A wireless base station (15) for transmitting spread spectrum signals is disclosed. The base station (15) includes a peak compression unit (16), which is...
Micromirror and post arrangements on substrates
A micromirror of a micromirror array of a spatial light modulator used in display systems comprises a mirror plate attached to a hinge that is supported by two...
Circuit for generating a temperature dependent current with high accuracy
An apparatus for adjusting a first signal with respect to a second signal includes: (a) A first converter receiving the first signal and employing n first...
Back end thin film capacitor having both plates of thin film resistor
material at single metallization layer
An integrated circuit back end capacitor structure includes a first dielectric layer on a substrate, a thin film bottom plate on the first dielectric layer, and...
Method to manufacture LDMOS transistors with improved threshold voltage
A double diffused region (65), (75), (85) is formed in a semiconductor substrate or in an epitaxial layer (20) formed on the semiconductor substrate. The double...
Semiconductor device manufactured using a non-contact implant metrology
A method of manufacturing a semiconductor device including calibrating an ion implant process. The calibration includes forming a dielectric layer over a...
Versatile system for conditioning slurry in CMP process
The present invention provides a system (100) for conditioning multi-component slurries utilized in chemical mechanical polishing (CMP) of semiconductor wafers...
Method for positioning sub-resolution assist features
The present application is directed to a method of selectively positioning sub-resolution assist features (SRAF) in a photomask pattern for an interconnect. The...
Three boundary scan cell switches controlling input to output buffer
A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is...
Hardware extension for accelerating fractional integer division within 3D
graphics and MP3 applications
An apparatus and method for allowing a digital signal processor (DSP) in a data processing system to perform high speed division operations. In one embodiment of...
Reducing computational complexity in determining the distance from each of
a set of input points to each of a...
An aspect of the present invention takes advantage of the fact that the coordinates of fixed points do not change, and thus the energy (sum of squares of the...
High dynamic range pre-power amplifier incorporating digital attenuator
A novel digital attenuator circuit and associated pre-power amplifier (PPA) that substantially increases the dynamic range of the amplifier. Increased dynamic...
If-to-baseband conversion for flexible frequency planning capability
An RF receiver apparatus (31) is provided physically separately from a cooperating baseband processor apparatus (32). The RF receiver includes a mixer circuit...
Channel length estimation and accurate FFT window placement for
high-mobility OFDM receivers in single...
A method of estimating a channel length (304) in a wireless receiver is disclosed. The receiver receives a signal (122) from a remote transmitter. The receiver...
Sending real-time and dependent information over separate network paths
In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer...
System and method for providing a pulse-width modulated signal to an
Systems and methods are disclosed that can be used to control an output signal, such as for controlling a heater for a hard disk drive. A system can include a...
System and method for regulating micromirror position
A system and method for regulating micromirror position in a digital micromirror device. The system and method adjusts micromirror operating temperature and/or a...
Passive entry and immobilizer at different frequencies using same antenna
A passive entry and immobilizer key for vehicles comprises an integrated front-end circuit (12b) with three battery-supplied receiver channels (14, 16, 18), each...
Oscillator system, method of providing a resonating signal and a
communications system employing the same
An n.sup.th-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment,...
Matched analog CMOS transistors with extension wells
One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a...
Semiconductor device having a dislocation loop located within a boundary
created by source/drain regions and a...
The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The...
Multi-stage implant to improve device characteristics
One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body....
Ceramic header method
A ceramic header configured to form a portion of an electronic device package includes a mounting portion configured to provide a mounting surface for an...
Technique for aging induced performance drift compensation in an
An improved compensation circuit that compensates for lifetime performance drifts due to aging of integrated circuits to improve the circuit performance. In one...
Polyphase electric energy meter
A polyphase electric energy meter is provided that includes a microcontroller with a front end that converts analog current input signals and analog voltage...
Time-division multiplex arbitration with fractional allocation
Disclosed embodiments reveal techniques for efficiently allocating time slots in a time-division multiplex (TDM) cycle among multiple channels of varying size,...
Reference voltage change in a digital power supply
An example disclosed method to handle a reference voltage change in a digital power supply includes receiving a first value associated with a first reference...
Latched comparator and methods for using such
Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with a...
CMOS output driver
A CMOS output driver is provided for driving a capacitive load over a circuit trace in high speed applications. The CMOS output driver comprises a signal input...
Body bias to facilitate transistor matching
One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a...
System and method for making a LDMOS device with electrostatic discharge
A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first...
Method for reducing line edge roughness for conductive features
The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the...
Method of forming silicided gates using buried metal layers
A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal...
Method for fabricating carbon nanotube transistors on a silicon or SOI
A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically...
Data system simulated event and matrix debug of pipelined processor
A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor...
Automatic input error recovery circuit and method for recursive digital
Recursive digital filter circuitry which avoids persistent unstable conditions therein provides a serial clock signal, a synchronization signal, and a serial...
Frequency hopping communication protocol
A Master-Slave Dwelling technique associated with modified Bluetooth hopping provides performance gains and extended ranges of operation for slow Doppler...
High performance, area efficient direct bitline sensing circuit
In a method and apparatus for reading a logic state stored in an 8 transistor memory cell (8TMC), a differential sense circuit includes a differential input...
Constant output common mode voltage of a pre-amplifier circuit
A method, apparatus and system of constant output common mode voltage of a pre-amplifier circuit are disclosed. In one embodiment, a system includes a first...
Feedback biasing technique for a stage of an amplifier that uses a
feedback control loop having low gain
According to an aspect of the present invention, a stage of an amplifier contains a positive feedback loop in addition to a negative feedback loop to maintain...
High performance clocked latches and devices therefrom
An integrated circuit (400) includes at least one clocked latch circuit (410). The clocked latch circuit (400) includes a first stage (415) including a latch...
AFSM circuit and method for low jitter PLL CMOS programmable divider
A frequency divider (10A) includes an asynchronous finite state machine (AFSM) configured as a counter (20) having an input coupled to an input clock signal...
Amplifier topology and method for connecting to printed circuit board
traces used as shunt resistors
An integrated circuit current shunt amplifier (2A) includes an amplifier (9) having a (+) input connected to a first terminal (5A) of a shunt resistor...
Memory device with memory cell including MuGFET and fin capacitor
One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of...
Gated quantum resonant tunneling diode using CMOS transistor with modified
pocket and LDD implants
A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an...
Formation of a silicon oxide interface layer during silicon carbide etch
stop deposition to promote better...
In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are...
Thermal treatment of nitrided oxide to improve negative bias thermal
A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated...