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MOS device and process having low resistance silicide interface using
additional source/drain implant
An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source...
Methods and system for determining pitch of lithographic features
A method is provided for determining pitch of lithographic features of a mask. The method includes determining a bias based on an interaction between a plurality...
TOD or time stamp inserted into trace recording stream
During trace recording, on-chip trace export mechanisms may schedule output from multiple sources out of order of execution. This makes the exact arrival of...
Method, system and device for handling a memory management fault in a
multiple processor device
A method or device handles memory management faults in a device having a digital signal processor ("DSP") and a microprocessor. The DSP includes a memory...
An adder that can detect the generation of overflow at a high speed. Carry signal c14 from the 15.sup.th digit to the 16.sup.th digit in the result of addition...
Integrated radio frequency filters for multiband transceivers
A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to...
Device and method for receiving and processing RF signals, a method for
providing digital calibration values...
A device for receiving a RF signal over multiple channels, a receiver incorporating the device, a method of providing digital calibration values for a...
Methods and apparatus to perform signal removal in a low intermediate
Methods, apparatus, and articles of manufacture are disclosed for removing an undesired component from a low intermediate frequency signal having an intermediate...
Binaural sound localization using a formant-type cascade of resonators and
This invention is a method for binaural localization using a cascade of resonators and anti-resonators to implement an HRTF (head-related transfer function). The...
Adaptive thresholds for high speed downlink shared control channel
(HS-SCCH) (part I) detection schemes
A technique is provided for implementing adaptive thresholds associated with HS-SCCH detection schemes; and when applied to any HS-SCCH detection scheme, the...
Virtual clear channel avoidance (CCA) mechanism for wireless
An arrangement avoids contention on a communication medium among devices including at least a transmitter and a receiver. The arrangement involves a first...
Merged camera and scanner
A narrow scanning aperture, lens, and mirror are added to a digital camera to enable image or text scanning. A motion sensor on the same face as the scanner...
Differential amplifier system
One embodiment of the invention includes a differential amplifier circuit. A first input stage generates first and second control voltages in response to a...
System and method for common mode translation
System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC...
Split-feedback technique for improving load regulation in amplifiers
A circuit arrangement and method for improving load regulation in an amplifier (e.g., LDO amplifier) uses a feedback circuit including a parallely connected...
Raised solder-mask-defined (SMD) solder ball pads for a laminate
electronic circuit board
A raised solder-mask-defined (SMD) pad configured for receiving a solder ball on a laminate electronic circuit board and a method of creating the raised SMD pad...
Semiconductive device having improved copper density for
In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is...
Energy beam treatment to improve packaging reliability
The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an...
Structure and method for a triple-gate transistor with reverse STI
Exemplary embodiments provide triple-gate semiconductor devices isolated by reverse STI structures and methodologies for their manufacture. In an exemplary...
CMOS fabrication process
Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with...
Method of forming an acceleration sensor
A method of forming a MEMS structure over active circuitry in a semiconductor body includes forming active circuitry in a semiconductor body, and forming the...
Spot heat wirebonding
Methods and systems are disclosed for forming secure wirebonds between electrical contacts in electronic device assemblies. Representative embodiments of the...
Self-test output for high-density BIST
A method, apparatus and system of a self-test output for high density BIST are disclosed. In one embodiment, an integrated circuit includes one or more memories,...
Apparatus and method for coupling a plurality of test access ports to
external test and debug facility
An interface unit is provided for selectively testing a plurality of processor/cores. The interface unit includes an interface test access port (TAP) unit...
Using a delay line to cancel clock insertion delays
A programmable delay is added to the data and clock data paths in order to cancel the effect of the clock insertion delays. This programmable delay is adjusted...
Graphic equalizer as a cascade of equalization filters with the gain of each individual filter compensated for the gain leakage from other filters. A linear...
Audio bandwidth expansion
Bandwidth expansion for audio signals by frequency band translations plus adaptive gains to create higher frequencies; use of a common channel for both stereo...
Orthogonal frequency division multiplexing access (OFDMA) ranging
A method for Orthogonal Frequency Division Multiplexing Access (OFDMA) ranging is provided. The method includes receiving a signal having OFDMA symbols. An FFT...
Methods and apparatus for proximity detection of hard disk drive read
Methods and apparatus for proximity detection of hard disk drive read heads are disclosed. A disclosed method comprises forming a first signal having a...
Magnetoresistive head preamplifier circuit with programmable input
A preamplifier circuit for a disk drive system is disclosed. The preamplifier circuit has first and second inputs that sense the voltage on either side of a...
Method and apparatus obtaining color values for a digital camera
Digital camera color correction with a linear transformation having coefficients computed from an optimization with preservation of gray levels. This preserves...
Hybrid stochastic gradient based digitally controlled oscillator gain
A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The...
Low-leakage level-shifters with supply detection
Low-leakage level-shifters with reduced leakage are disclosed. In one example, a level-shifter circuit to reduce leakage when there is an invalid supply voltage...
Output stage with low output impedance and operating from a low power
A low-impedance output stage which operates from a low voltage power supply. In an embodiment, the output stage contains an operational amplifier and two PMOS...
Output impedance compensation for linear voltage regulators
In a method and system for regulating an output voltage, a linear voltage regulator (LVR) includes an adjustable shunt regulator (ASR) having a limited gain, a...
Package-on-package semiconductor assembly
Disclosed are methods and devices for providing improved semiconductor packages and POP IC assemblies using the improved packages with reduced warping. According...
Manufacturable reliable diffusion-barrier
Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal...
Capacitor integration at top-metal level with a protective cladding for
copper surface protection
An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and...
Mechanism for pipelining loops with irregular loop control
This invention modifies an irregular software pipelined loop conditioned upon data in a condition register in a compiler scheduled very long instruction word...
Inter-cluster communication network and heirarchical register files for
clustered VLIW processors
A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files...
VLIW optional fetch packet header extends instruction set space
This invention is useful in a very long instruction word data processor that fetches a predetermined plural number of instructions each operation cycle. A...
Re-assigning cache line ways
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
Method to hide or reduce access latency of a slow peripheral in a
pipelined direct memory access system
A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent...
Concurrent read response acknowledge enhanced direct memory access unit
An enhanced direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response...
Electrical overstress protection
In one aspect, a method for protection of an integrated circuit device includes but is not limited to detecting a first current in the integrated circuit device,...
Rapidly activated current mirror system
One embodiment of the invention includes a current mirror system. The system comprises a master circuit configured to conduct a first current in response to an...
Tunable voltage controller for a sub-circuit and method of operating the
The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a ...
Glitch free 2-way clock switch
The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate...
Versatile system for charge dissipation in the formation of semiconductor
The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200),...
Methods for depositing, releasing and packaging micro-electromechanical
devices on wafer substrates
A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from...