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Patent # Description
US-7,682,892 MOS device and process having low resistance silicide interface using additional source/drain implant
An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source...
US-7,682,759 Methods and system for determining pitch of lithographic features
A method is provided for determining pitch of lithographic features of a mask. The method includes determining a bias based on an interaction between a plurality...
US-7,681,084 TOD or time stamp inserted into trace recording stream
During trace recording, on-chip trace export mechanisms may schedule output from multiple sources out of order of execution. This makes the exact arrival of...
US-7,681,012 Method, system and device for handling a memory management fault in a multiple processor device
A method or device handles memory management faults in a device having a digital signal processor ("DSP") and a microprocessor. The DSP includes a memory...
US-7,680,874 Adder
An adder that can detect the generation of overflow at a high speed. Carry signal c14 from the 15.sup.th digit to the 16.sup.th digit in the result of addition...
US-7,680,477 Integrated radio frequency filters for multiband transceivers
A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to...
US-7,680,472 Device and method for receiving and processing RF signals, a method for providing digital calibration values...
A device for receiving a RF signal over multiple channels, a receiver incorporating the device, a method of providing digital calibration values for a...
US-7,680,456 Methods and apparatus to perform signal removal in a low intermediate frequency receiver
Methods, apparatus, and articles of manufacture are disclosed for removing an undesired component from a low intermediate frequency signal having an intermediate...
US-7,680,289 Binaural sound localization using a formant-type cascade of resonators and anti-resonators
This invention is a method for binaural localization using a cascade of resonators and anti-resonators to implement an HRTF (head-related transfer function). The...
US-7,680,216 Adaptive thresholds for high speed downlink shared control channel (HS-SCCH) (part I) detection schemes
A technique is provided for implementing adaptive thresholds associated with HS-SCCH detection schemes; and when applied to any HS-SCCH detection scheme, the...
US-7,680,150 Virtual clear channel avoidance (CCA) mechanism for wireless communications
An arrangement avoids contention on a communication medium among devices including at least a transmitter and a receiver. The arrangement involves a first...
US-7,679,792 Merged camera and scanner
A narrow scanning aperture, lens, and mirror are added to a digital camera to enable image or text scanning. A motion sensor on the same face as the scanner...
US-7,679,444 Differential amplifier system
One embodiment of the invention includes a differential amplifier circuit. A first input stage generates first and second control voltages in response to a...
US-7,679,443 System and method for common mode translation
System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC...
US-7,679,437 Split-feedback technique for improving load regulation in amplifiers
A circuit arrangement and method for improving load regulation in an amplifier (e.g., LDO amplifier) uses a feedback circuit including a parallely connected...
US-7,679,190 Raised solder-mask-defined (SMD) solder ball pads for a laminate electronic circuit board
A raised solder-mask-defined (SMD) pad configured for receiving a solder ball on a laminate electronic circuit board and a method of creating the raised SMD pad...
US-7,679,002 Semiconductive device having improved copper density for package-on-package applications
In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is...
US-7,678,713 Energy beam treatment to improve packaging reliability
The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an...
US-7,678,675 Structure and method for a triple-gate transistor with reverse STI
Exemplary embodiments provide triple-gate semiconductor devices isolated by reverse STI structures and methodologies for their manufacture. In an exemplary...
US-7,678,637 CMOS fabrication process
Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with...
US-7,678,601 Method of forming an acceleration sensor
A method of forming a MEMS structure over active circuitry in a semiconductor body includes forming active circuitry in a semiconductor body, and forming the...
US-7,677,432 Spot heat wirebonding
Methods and systems are disclosed for forming secure wirebonds between electrical contacts in electronic device assemblies. Representative embodiments of the...
US-7,676,709 Self-test output for high-density BIST
A method, apparatus and system of a self-test output for high density BIST are disclosed. In one embodiment, an integrated circuit includes one or more memories,...
US-7,676,698 Apparatus and method for coupling a plurality of test access ports to external test and debug facility
An interface unit is provided for selectively testing a plurality of processor/cores. The interface unit includes an interface test access port (TAP) unit...
US-7,676,697 Using a delay line to cancel clock insertion delays
A programmable delay is added to the data and clock data paths in order to cancel the effect of the clock insertion delays. This programmable delay is adjusted...
US-7,676,048 Graphic equalizers
Graphic equalizer as a cascade of equalization filters with the gain of each individual filter compensated for the gain leakage from other filters. A linear...
US-7,676,043 Audio bandwidth expansion
Bandwidth expansion for audio signals by frequency band translations plus adaptive gains to create higher frequencies; use of a common channel for both stereo...
US-7,675,888 Orthogonal frequency division multiplexing access (OFDMA) ranging
A method for Orthogonal Frequency Division Multiplexing Access (OFDMA) ranging is provided. The method includes receiving a signal having OFDMA symbols. An FFT...
US-7,675,706 Methods and apparatus for proximity detection of hard disk drive read heads
Methods and apparatus for proximity detection of hard disk drive read heads are disclosed. A disclosed method comprises forming a first signal having a...
US-7,675,704 Magnetoresistive head preamplifier circuit with programmable input impedance
A preamplifier circuit for a disk drive system is disclosed. The preamplifier circuit has first and second inputs that sense the voltage on either side of a...
US-7,675,551 Method and apparatus obtaining color values for a digital camera
Digital camera color correction with a linear transformation having coefficients computed from an optimization with preservation of gray levels. This preserves...
US-7,675,368 Hybrid stochastic gradient based digitally controlled oscillator gain K.sub.DCO estimation
A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The...
US-7,675,345 Low-leakage level-shifters with supply detection
Low-leakage level-shifters with reduced leakage are disclosed. In one example, a level-shifter circuit to reduce leakage when there is an invalid supply voltage...
US-7,675,315 Output stage with low output impedance and operating from a low power supply
A low-impedance output stage which operates from a low voltage power supply. In an embodiment, the output stage contains an operational amplifier and two PMOS...
US-7,675,272 Output impedance compensation for linear voltage regulators
In a method and system for regulating an output voltage, a linear voltage regulator (LVR) includes an adjustable shunt regulator (ASR) having a limited gain, a...
US-7,675,152 Package-on-package semiconductor assembly
Disclosed are methods and devices for providing improved semiconductor packages and POP IC assemblies using the improved packages with reduced warping. According...
US-7,674,707 Manufacturable reliable diffusion-barrier
Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal...
US-7,674,682 Capacitor integration at top-metal level with a protective cladding for copper surface protection
An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and...
US-7,673,294 Mechanism for pipelining loops with irregular loop control
This invention modifies an irregular software pipelined loop conditioned upon data in a condition register in a compiler scheduled very long instruction word...
US-7,673,120 Inter-cluster communication network and heirarchical register files for clustered VLIW processors
A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files...
US-7,673,119 VLIW optional fetch packet header extends instruction set space
This invention is useful in a very long instruction word data processor that fetches a predetermined plural number of instructions each operation cycle. A...
US-7,673,101 Re-assigning cache line ways
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
US-7,673,091 Method to hide or reduce access latency of a slow peripheral in a pipelined direct memory access system
A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent...
US-7,673,076 Concurrent read response acknowledge enhanced direct memory access unit
An enhanced direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response...
US-7,672,102 Electrical overstress protection
In one aspect, a method for protection of an integrated circuit device includes but is not limited to detecting a first current in the integrated circuit device,...
US-7,671,667 Rapidly activated current mirror system
One embodiment of the invention includes a current mirror system. The system comprises a master circuit configured to conduct a first current in response to an...
US-7,671,663 Tunable voltage controller for a sub-circuit and method of operating the same
The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a ...
US-7,671,633 Glitch free 2-way clock switch
The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate...
US-7,671,445 Versatile system for charge dissipation in the formation of semiconductor device structures
The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200),...
US-7,671,428 Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from...
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