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Patent # Description
US-7,692,889 System and method for providing a pulse-width modulated signal to an output system
Systems and methods are disclosed that can be used to control an output signal, such as for controlling a heater for a hard disk drive. A system can include a...
US-7,692,841 System and method for regulating micromirror position
A system and method for regulating micromirror position in a digital micromirror device. The system and method adjusts micromirror operating temperature and/or a...
US-7,692,529 Passive entry and immobilizer at different frequencies using same antenna coil
A passive entry and immobilizer key for vehicles comprises an integrated front-end circuit (12b) with three battery-supplied receiver channels (14, 16, 18), each...
US-7,692,504 Oscillator system, method of providing a resonating signal and a communications system employing the same
An n.sup.th-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment,...
US-7,692,217 Matched analog CMOS transistors with extension wells
One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a...
US-7,691,714 Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a...
The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The...
US-7,691,700 Multi-stage implant to improve device characteristics
One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body....
US-7,690,106 Ceramic header method
A ceramic header configured to form a portion of an electronic device package includes a mounting portion configured to provide a mounting surface for an...
US-7,689,377 Technique for aging induced performance drift compensation in an integrated circuit
An improved compensation circuit that compensates for lifetime performance drifts due to aging of integrated circuits to improve the circuit performance. In one...
US-7,689,374 Polyphase electric energy meter
A polyphase electric energy meter is provided that includes a microcontroller with a front end that converts analog current input signals and analog voltage...
US-7,688,776 Time-division multiplex arbitration with fractional allocation
Disclosed embodiments reveal techniques for efficiently allocating time slots in a time-division multiplex (TDM) cycle among multiple channels of varying size,...
US-7,688,608 Reference voltage change in a digital power supply
An example disclosed method to handle a reference voltage change in a digital power supply includes receiving a first value associated with a first reference...
US-7,688,125 Latched comparator and methods for using such
Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with a...
US-7,688,115 CMOS output driver
A CMOS output driver is provided for driving a capacitive load over a circuit trace in high speed applications. The CMOS output driver comprises a signal input...
US-7,687,856 Body bias to facilitate transistor matching
One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a...
US-7,687,853 System and method for making a LDMOS device with electrostatic discharge protection
A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first...
US-7,687,407 Method for reducing line edge roughness for conductive features
The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the...
US-7,687,396 Method of forming silicided gates using buried metal layers
A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal...
US-7,687,308 Method for fabricating carbon nanotube transistors on a silicon or SOI substrate
A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically...
US-7,685,467 Data system simulated event and matrix debug of pipelined processor
A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor...
US-7,685,216 Automatic input error recovery circuit and method for recursive digital filters
Recursive digital filter circuitry which avoids persistent unstable conditions therein provides a serial clock signal, a synchronization signal, and a serial...
US-7,684,465 Frequency hopping communication protocol
A Master-Slave Dwelling technique associated with modified Bluetooth hopping provides performance gains and extended ranges of operation for slow Doppler...
US-7,684,274 High performance, area efficient direct bitline sensing circuit
In a method and apparatus for reading a logic state stored in an 8 transistor memory cell (8TMC), a differential sense circuit includes a differential input...
US-7,683,716 Constant output common mode voltage of a pre-amplifier circuit
A method, apparatus and system of constant output common mode voltage of a pre-amplifier circuit are disclosed. In one embodiment, a system includes a first...
US-7,683,715 Feedback biasing technique for a stage of an amplifier that uses a feedback control loop having low gain
According to an aspect of the present invention, a stage of an amplifier contains a positive feedback loop in addition to a negative feedback loop to maintain...
US-7,683,688 High performance clocked latches and devices therefrom
An integrated circuit (400) includes at least one clocked latch circuit (410). The clocked latch circuit (400) includes a first stage (415) including a latch...
US-7,683,679 AFSM circuit and method for low jitter PLL CMOS programmable divider
A frequency divider (10A) includes an asynchronous finite state machine (AFSM) configured as a counter (20) having an input coupled to an input clock signal...
US-7,683,604 Amplifier topology and method for connecting to printed circuit board traces used as shunt resistors
An integrated circuit current shunt amplifier (2A) includes an amplifier (9) having a (+) input connected to a first terminal (5A) of a shunt resistor...
US-7,683,417 Memory device with memory cell including MuGFET and fin capacitor
One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of...
US-7,683,364 Gated quantum resonant tunneling diode using CMOS transistor with modified pocket and LDD implants
A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an...
US-7,682,989 Formation of a silicon oxide interface layer during silicon carbide etch stop deposition to promote better...
In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are...
US-7,682,988 Thermal treatment of nitrided oxide to improve negative bias thermal instability
A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated...
US-7,682,892 MOS device and process having low resistance silicide interface using additional source/drain implant
An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source...
US-7,682,759 Methods and system for determining pitch of lithographic features
A method is provided for determining pitch of lithographic features of a mask. The method includes determining a bias based on an interaction between a plurality...
US-7,681,084 TOD or time stamp inserted into trace recording stream
During trace recording, on-chip trace export mechanisms may schedule output from multiple sources out of order of execution. This makes the exact arrival of...
US-7,681,012 Method, system and device for handling a memory management fault in a multiple processor device
A method or device handles memory management faults in a device having a digital signal processor ("DSP") and a microprocessor. The DSP includes a memory...
US-7,680,874 Adder
An adder that can detect the generation of overflow at a high speed. Carry signal c14 from the 15.sup.th digit to the 16.sup.th digit in the result of addition...
US-7,680,477 Integrated radio frequency filters for multiband transceivers
A system and method integrates signal filters in a multiband transceiver. A preferred embodiment comprises an amplifier with a first tunable capacitor coupled to...
US-7,680,472 Device and method for receiving and processing RF signals, a method for providing digital calibration values...
A device for receiving a RF signal over multiple channels, a receiver incorporating the device, a method of providing digital calibration values for a...
US-7,680,456 Methods and apparatus to perform signal removal in a low intermediate frequency receiver
Methods, apparatus, and articles of manufacture are disclosed for removing an undesired component from a low intermediate frequency signal having an intermediate...
US-7,680,289 Binaural sound localization using a formant-type cascade of resonators and anti-resonators
This invention is a method for binaural localization using a cascade of resonators and anti-resonators to implement an HRTF (head-related transfer function). The...
US-7,680,216 Adaptive thresholds for high speed downlink shared control channel (HS-SCCH) (part I) detection schemes
A technique is provided for implementing adaptive thresholds associated with HS-SCCH detection schemes; and when applied to any HS-SCCH detection scheme, the...
US-7,680,150 Virtual clear channel avoidance (CCA) mechanism for wireless communications
An arrangement avoids contention on a communication medium among devices including at least a transmitter and a receiver. The arrangement involves a first...
US-7,679,792 Merged camera and scanner
A narrow scanning aperture, lens, and mirror are added to a digital camera to enable image or text scanning. A motion sensor on the same face as the scanner...
US-7,679,444 Differential amplifier system
One embodiment of the invention includes a differential amplifier circuit. A first input stage generates first and second control voltages in response to a...
US-7,679,443 System and method for common mode translation
System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC...
US-7,679,437 Split-feedback technique for improving load regulation in amplifiers
A circuit arrangement and method for improving load regulation in an amplifier (e.g., LDO amplifier) uses a feedback circuit including a parallely connected...
US-7,679,190 Raised solder-mask-defined (SMD) solder ball pads for a laminate electronic circuit board
A raised solder-mask-defined (SMD) pad configured for receiving a solder ball on a laminate electronic circuit board and a method of creating the raised SMD pad...
US-7,679,002 Semiconductive device having improved copper density for package-on-package applications
In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is...
US-7,678,713 Energy beam treatment to improve packaging reliability
The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an...
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