Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: texas instruments





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,678,675 Structure and method for a triple-gate transistor with reverse STI
Exemplary embodiments provide triple-gate semiconductor devices isolated by reverse STI structures and methodologies for their manufacture. In an exemplary...
US-7,678,637 CMOS fabrication process
Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with...
US-7,678,601 Method of forming an acceleration sensor
A method of forming a MEMS structure over active circuitry in a semiconductor body includes forming active circuitry in a semiconductor body, and forming the...
US-7,677,432 Spot heat wirebonding
Methods and systems are disclosed for forming secure wirebonds between electrical contacts in electronic device assemblies. Representative embodiments of the...
US-7,676,709 Self-test output for high-density BIST
A method, apparatus and system of a self-test output for high density BIST are disclosed. In one embodiment, an integrated circuit includes one or more memories,...
US-7,676,698 Apparatus and method for coupling a plurality of test access ports to external test and debug facility
An interface unit is provided for selectively testing a plurality of processor/cores. The interface unit includes an interface test access port (TAP) unit...
US-7,676,697 Using a delay line to cancel clock insertion delays
A programmable delay is added to the data and clock data paths in order to cancel the effect of the clock insertion delays. This programmable delay is adjusted...
US-7,676,048 Graphic equalizers
Graphic equalizer as a cascade of equalization filters with the gain of each individual filter compensated for the gain leakage from other filters. A linear...
US-7,676,043 Audio bandwidth expansion
Bandwidth expansion for audio signals by frequency band translations plus adaptive gains to create higher frequencies; use of a common channel for both stereo...
US-7,675,888 Orthogonal frequency division multiplexing access (OFDMA) ranging
A method for Orthogonal Frequency Division Multiplexing Access (OFDMA) ranging is provided. The method includes receiving a signal having OFDMA symbols. An FFT...
US-7,675,706 Methods and apparatus for proximity detection of hard disk drive read heads
Methods and apparatus for proximity detection of hard disk drive read heads are disclosed. A disclosed method comprises forming a first signal having a...
US-7,675,704 Magnetoresistive head preamplifier circuit with programmable input impedance
A preamplifier circuit for a disk drive system is disclosed. The preamplifier circuit has first and second inputs that sense the voltage on either side of a...
US-7,675,551 Method and apparatus obtaining color values for a digital camera
Digital camera color correction with a linear transformation having coefficients computed from an optimization with preservation of gray levels. This preserves...
US-7,675,368 Hybrid stochastic gradient based digitally controlled oscillator gain K.sub.DCO estimation
A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The...
US-7,675,345 Low-leakage level-shifters with supply detection
Low-leakage level-shifters with reduced leakage are disclosed. In one example, a level-shifter circuit to reduce leakage when there is an invalid supply voltage...
US-7,675,315 Output stage with low output impedance and operating from a low power supply
A low-impedance output stage which operates from a low voltage power supply. In an embodiment, the output stage contains an operational amplifier and two PMOS...
US-7,675,272 Output impedance compensation for linear voltage regulators
In a method and system for regulating an output voltage, a linear voltage regulator (LVR) includes an adjustable shunt regulator (ASR) having a limited gain, a...
US-7,675,152 Package-on-package semiconductor assembly
Disclosed are methods and devices for providing improved semiconductor packages and POP IC assemblies using the improved packages with reduced warping. According...
US-7,674,707 Manufacturable reliable diffusion-barrier
Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal...
US-7,674,682 Capacitor integration at top-metal level with a protective cladding for copper surface protection
An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and...
US-7,673,294 Mechanism for pipelining loops with irregular loop control
This invention modifies an irregular software pipelined loop conditioned upon data in a condition register in a compiler scheduled very long instruction word...
US-7,673,120 Inter-cluster communication network and heirarchical register files for clustered VLIW processors
A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files...
US-7,673,119 VLIW optional fetch packet header extends instruction set space
This invention is useful in a very long instruction word data processor that fetches a predetermined plural number of instructions each operation cycle. A...
US-7,673,101 Re-assigning cache line ways
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
US-7,673,091 Method to hide or reduce access latency of a slow peripheral in a pipelined direct memory access system
A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent...
US-7,673,076 Concurrent read response acknowledge enhanced direct memory access unit
An enhanced direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response...
US-7,672,102 Electrical overstress protection
In one aspect, a method for protection of an integrated circuit device includes but is not limited to detecting a first current in the integrated circuit device,...
US-7,671,667 Rapidly activated current mirror system
One embodiment of the invention includes a current mirror system. The system comprises a master circuit configured to conduct a first current in response to an...
US-7,671,663 Tunable voltage controller for a sub-circuit and method of operating the same
The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a ...
US-7,671,633 Glitch free 2-way clock switch
The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate...
US-7,671,445 Versatile system for charge dissipation in the formation of semiconductor device structures
The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200),...
US-7,671,428 Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from...
US-7,671,408 Vertical drain extended MOSFET transistor with vertical trench field plate
A vertical drain extended metal-oxide semiconductor field effect (MOSFET) transistor or a vertical double diffused metal-oxide semiconductor (VDMOS) transistor...
US-7,670,952 Method of manufacturing metal silicide contacts
A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also...
US-7,670,920 Methods and apparatus for forming a polysilicon capacitor
An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a...
US-7,670,917 Semiconductor device made by using a laser anneal to incorporate stress into a channel region
In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming...
US-7,670,913 Method for forming ultra-thin low leakage multiple gate devices using a masking layer over the semiconductor...
The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment,...
US-7,670,892 Nitrogen based implants for defect reduction in strained silicon
A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain...
US-7,670,890 Silicide block isolated junction field effect transistor source, drain and gate
An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain...
US-7,670,888 Low noise JFET
Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the...
US-7,669,313 Method for fabricating a thin film resistor semiconductor structure
A method is provided of fabricating a thin film resistor semiconductor structure. In one aspect of the invention, the method includes forming a dielectric layer...
US-7,669,243 Method and system for detection and neutralization of buffer overflow attacks
A method for detecting a stack buffer overflow attack is provided that includes receiving a memory access request from a processor core of a system, and...
US-7,669,109 Hardware-efficient low density parity check code for digital communications
A low density parity check (LDPC) code for a belief propagation decoder circuit is disclosed. LDPC code is arranged as a macro matrix (H) representing block...
US-7,669,099 Optimized JTAG interface
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
US-7,668,564 Slow uplink power control
Embodiments of the invention provide embodiments of the invention provide and method, network entity and user equipment for slow uplink power control of user...
US-7,668,321 Automatic power foldback for audio applications
A power foldback circuit to automatically control the power of an audio amplifier by using the volume inputs to a pre-amp source which drives the audio...
US-7,668,313 Recipient-encrypted session key cryptography
A method for protecting secret keys, such as HDCP device key sets, during the manufacturing process is disclosed. In particular, the present invention comprises...
US-7,668,265 Ultra wideband interference cancellation for orthogonal frequency division multiplex transmitters by...
A method of wirelessly communicating is disclosed. The method comprises determining a matrix W based in part on limiting a plurality of active interference...
US-7,668,251 Scalable post-channel estimate phase corrector, method of correction and MIMO communication system employing...
The present invention provides a post-channel estimate phase corrector for use with a multiple-input, multiple-output (MIMO) receiver employing M receive...
US-7,668,248 High-performance LDPC coding for digital communications in a multiple-input, multiple-output environment
Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.