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Patent # Description
US-7,646,804 System and method for improving bit-loading in discrete multitone-based digital subscriber line modems
A system and method for improving bit-loading in discrete multitone (DMT)-based digital subscriber line (DSL) modems. In one embodiment, the system includes: (1)...
US-7,646,323 Clock generator
The present invention relates to controlling the timing of a clock signal in high speed circuits, such as an analogue-digital converter (ADC). In some high speed...
US-7,646,219 Translator circuit having internal positive feedback
An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher...
US-7,646,204 Method and system for testing a settling time for a device-under-test
A system and method are disclosed for testing a settling time of a device-under-test (DUT). A method for determining a settling time of a device-under-test (DUT)...
US-7,646,186 Holdover circuit for a power converter using a bi-directional switching regulator
A holdover circuit is configured with a holdover capacitor, preferably an aluminum electrolytic capacitor, to provide uninterruptible operation for an electrical...
US-7,645,704 Methods and apparatus of etch process control in fabrications of microstructures
The present invention provides a method for removing sacrificial materials in fabrications of microstructures using a selected spontaneous vapor phase chemical...
US-7,644,383 Method and system for correcting signal integrity crosstalk violations
A system and method for repairing crosstalk delays are disclosed herein. By modeling the change in effective capacitance, one may determine the delay...
US-7,644,330 Adapting scan architectures for low power operation
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
US-7,644,135 Method of improving communications data throughput on embedded systems and reducing the load on the operating...
A method is provided for dramatically improving communications data throughput on embedded systems and reducing the load on the operating system and central...
US-7,643,964 Method, system and apparatus for measuring an idle value of a central processing unit
In a method, system and apparatus for measuring an idle value of a Central Processing Unit (CPU) in an embedded system, the CPU increments a hardware counter in...
US-7,643,630 Echo suppression with increment/decrement, quick, and time-delay counter updating
Hands-free phones with voice activity detection using a comparison of frame power estimate with an adaptive frame noise power estimate, automatic gain control...
US-7,643,259 Substrate, with ESD magnetically induced wires, bound to passives/product ICS
A device is protected from induced or unexpected current spikes or surges, by receiving the current spikes through a conducting wire. The conducting wire is...
US-7,642,938 Gray code to sign and magnitude converter
The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital...
US-7,642,852 Resistor self-trim circuit for increased performance
In a method and apparatus for trimming values of load resistors to reduce variations there between, a common mode feedback loop (CMFBL) included in a...
US-7,642,830 Method and delay circuit with accurately controlled duty cycle
A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal...
US-7,642,819 High speed current mode write driver
An integrated circuit (100) includes a current mode write driver (105). The write driver (105) includes a switching control circuit (110) including (i) a DC...
US-7,642,814 Leakage compensation circuit using limiting current inverter
The leakage compensation circuit includes: a replica circuit of a circuit to be compensated, the replica circuit provides a replica leakage current equal to a...
US-7,642,729 Light-emitting device driving gear
When an APC selection signal FA is set to H level to start an APC operation, a monitor voltage V.sub.A is immediately generated from a monitor voltage generating...
US-7,642,725 Unbalanced plural string LED driver with common return resistor
The present disclosure describes systems and methods for driving light emitting diodes (LEDs). At least some embodiments include an LED driver system that...
US-7,642,649 Support structure for low-k dielectrics
A semiconductor device employs a support structure to mitigate damage to dielectric layers having a low dielectric constant (k). The semiconductor device...
US-7,642,619 Air gap in integrated circuit inductor fabrication
A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops,...
US-7,642,197 Method to improve performance of secondary active components in an esige CMOS technology
According to various embodiments, there are eSiGe CMOS devices and methods of making them. The method of making a substrate for a CMOS device can include...
US-7,642,153 Methods for forming gate electrodes for integrated circuits
A method of forming an integrated circuit can include the steps of providing a substrate having a semiconducting surface and forming a plurality of...
US-7,642,146 Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage...
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS...
US-7,642,144 Transistors with recessed active trenches for increased effective gate width
A method of manufacturing a semiconductor device having recessed active trenches by providing a substrate with STI and active regions, forming a first oxide...
US-7,642,021 Method of mapping lithography focus errors
The present application is directed to a method for determining photolithography focus errors during production of a device. The method comprises providing a...
US-7,640,475 At-speed transition fault testing with low speed scan enable
A method and/or a system of at-speed transition fault testing with low speed scan enable is disclosed. In one embodiment, a digital system includes any number of...
US-7,640,474 System and method for input/output characterization
A test system in an integrated circuit includes a boundary scan cell. The boundary scan cell includes a first storage element and a second storage element...
US-7,640,471 On-board FIFO memory module for high speed digital sourcing and capture to/from DUT (device under test) using a...
In a method and system for testing, a tester (110) is operable to communicate test signals (124, 126) at a tester clock speed, and a device (190) to be tested is...
US-7,640,185 Dispensing system and method with radio frequency customer identification
A system and method for providing a fuel dispenser with radio frequency customer identification capabilities. The system and method determines whether a...
US-7,639,745 Serial data link with automatic power down
A serial data link (10) includes a transmitter (12) using a differential transmitter cell (20) to transmit data using differential signals and a receiver (14)...
US-7,639,626 Built in self test
There is provided a method for Loss of Signal Built In Self Test, and corresponding apparatus comprising: a loopback driver for receiving test signals, and for...
US-7,639,463 Apparatus and method for reducing leakage between an input terminal and power rail
An apparatus for reducing current leakage between an input locus and at least one power rail for a system includes, for each respective power rail: (a) A first...
US-7,639,442 Methods and apparatus to perform hard-disk drive head proximity detection in a preamplifier
Methods and apparatus to perform hard-disk drive head proximity detection in a preamplifier are described. One example method of detecting head position in a...
US-7,639,082 System and method for amplifier gain measurement and compensation
A system and method for amplifier gain measurement and compensation. A method for compensating a signal gain of an amplifier circuit includes determining a...
US-7,639,070 Switching circuit in a phase locked loop (PLL) to minimize current leakage in integrated circuits
In an apparatus and method for reducing current leakage in a phase locked loop (PLL), a pair of resistive divider circuit is coupled to receive a pair of...
US-7,639,056 Ultra low area overhead retention flip-flop for power-down applications
In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for...
US-7,638,843 Integrating high performance and low power multi-gate devices
A semiconductor device comprises a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprises a...
US-7,638,415 Method for reducing dislocation threading using a suppression implant
The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device...
US-7,638,412 Method and system for reducing charge damage in silicon-on-insulator technology
According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain...
US-7,638,402 Sidewall spacer pullback scheme
A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made...
US-7,638,401 Memory device with surface-channel peripheral transistors
A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates...
US-7,637,658 Systems and methods for PWM clocking in a temperature measurement circuit
Various systems and methods for pulse width modulated clocking in a temperature measurement are disclosed. For example, some embodiments of the present invention...
US-7,636,875 Low noise coding for digital data interface
A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a...
US-7,636,190 Method of projecting an image from a reflective light valve
Disclosed herein is a method of projecting images using reflective light valves. Pixel patterns generated of the light valve pixels based on image data are...
US-7,635,914 Multi layer low cost cavity substrate fabrication for pop packages
In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to...
US-7,635,613 Semiconductor device having firmly secured heat spreader
A semiconductor device comprising a leadframe (903), which has first (903a) and second (903b) surfaces, a planar pad (910) of a certain size, and a plurality of...
US-7,634,643 Stack register reference control bit in source operand of instruction
A processor is disclosed herein that may execute an instruction that includes an immediate value and a reference to a register accessible to the processor. The...
US-7,634,226 Propagation of data throughout an area using distributed transponders and scanners with relative movement
A method is provided for propagating data among multiple locations in an area. The method includes using a plurality of transponders distributed throughout the...
US-7,634,020 Preamble for a TFI-OFDM communications system
System and method for simplifying preamble detection and reducing power consumption in receivers. A preferred embodiment comprises a preamble made up of two...
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