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Patent # | Description |
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US-7,973,523 |
Reverse current sensing regulator system and method A reverse current sensing (RCS) regulator system and method is provided. One embodiment of the invention includes a RCS regulator system. The system comprises a... |
US-7,973,487 |
Power supply circuit A power supply circuit is proposed for supplying current to a pair of white LEDs connected in series. The circuit comprises a DC-DC power converter, with a... |
US-7,973,416 |
Thru silicon enabled die stacking scheme A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully... |
US-7,972,905 |
Packaged electronic device having metal comprising self-healing die attach
material A method of assembling an electronic device and electronic packages therefrom. A die attach adhesive precursor is placed between a top surface of a workpiece... |
US-7,972,020 |
Apparatus and method for reducing speckle in display of images An apparatus and method of reducing speckle in projection of images is provided that includes the elements or features of producing a first image and displacing... |
US-7,972,004 |
System and method for uniform light generation A system and method for uniform light generation in projection display systems. An illumination source comprises a light source to produce colored light, and a... |
US-7,972,001 |
Projection illumination device and method for projection visual display
system using multiple controlled light... A method for compensating for a shift in color in a light source and a system of color illumination for a projection visual display (PVD) system. In one... |
US-7,971,351 |
Method of manufacturing a semiconductor device The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips... |
US-7,970,230 |
Image processing with minimization of ringing artifacts and noise A method of reducing ringing artifacts in image data that has been filtered with a high frequency emphasis filter. For each filtered data value, a local... |
US-7,970,121 |
Tone, modulated tone, and saturated tone detection in a voice activity
detection device In a voice activity detection (VAD) device a method for defining tone signals comprises defining a threshold for zero amplitude change, calculating a zero... |
US-7,970,082 |
Frequency offset correction when decoding a packet encoded in a frequency
modulated signal Embodiments include frequency offset correction when decoding a packet encoded in a frequency modulated signal. Different symbols encoded in the packet may be... |
US-7,969,334 |
Apparatus for correcting setting error in an MDAC amplifier Multiplying digital-to-analog converters (MDACs), which are generally employed in pipelined analog-to-digital converters (ADCs), can have a settling error... |
US-7,969,274 |
Method to improve inductance with a high-permeability slotted plate core
in an integrated circuit An inductor structure (102) formed in an integrated circuit (100) is disclosed, and includes a first isolation layer (106) and a first core plate (104) disposed... |
US-7,969,219 |
Wide range delay cell A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell,... |
US-7,968,974 |
Scribe seal connection A feedthrough in an IC scribe seal is disclosed. The feedthrough is structured to maintain isolation of components in the IC from mechanical damage and chemical... |
US-7,968,950 |
Semiconductor device having improved gate electrode placement and
decreased area design A semiconductor device includes a gate electrode having ends that overlap isolation regions, wherein the gate electrode is located over an active region located... |
US-7,968,936 |
Quasi-vertical gated NPN-PNP ESD protection device Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well... |
US-7,968,878 |
Electrical test structure to detect stress induced defects using diodes A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate... |
US-7,968,443 |
Cross-contamination control for processing of circuits comprising MOS
devices that include metal comprising... A cross method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor wafer having a topside semiconductor surface, a bevel... |
US-7,968,415 |
Transistor with reduced short channel effects and method A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a... |
US-7,967,448 |
Optical system for a thin, low-chin, projection television A micro-mirror based projection display system in an enclosure with minimum chin and depth measurements is disclosed. A light source, such as a solid state... |
US-RE42,494 |
Preventing drain to body forward bias in a MOS transistor A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M.sub.1, M.sub.2, M.sub.3 connected in parallel for respectively driving a... |
US-7,966,533 |
Register device and methods for using such Various systems and methods for registering data are disclosed herein. For example, test enabled flip-flop devices are provided. Such devices include a test... |
US-7,966,528 |
Watchdog mechanism with fault escalation A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a... |
US-7,966,527 |
Watchdog mechanism with fault recovery A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a... |
US-7,966,183 |
Multiplying confidence scores for utterance verification in a mobile
telephone Automatic speech recognition verification using a combination of two or more confidence scores based on UV features which reuse computations of the original... |
US-7,965,798 |
Robust packet detection, symbol timing, channel length estimation and
channel response estimation for wireless... A method. The method includes producing a first signal match indication based on at least one match indication indicative of a match between at least one signal... |
US-7,965,797 |
Method, system and apparatus for generating constant amplitude zero
autocorrelation sequences A method, system and apparatus for generating a constant amplitude zero autocorrelation (CAZAC) sequence to be transmitted on a wireless communication channel... |
US-7,965,657 |
Sounding reference signal cell specific sub-frame configuration A method of wireless communication including a plurality of fixed basestations and a plurality of mobile user equipment with each basestation transmitting to... |
US-7,965,280 |
Wait mode pen-touch detection and method for touch screen controller A touch screen controller (1A) includes circuitry (2B) for generating a pen touch detection signal (PENTOUCH) having a first level if a touch point (Q) of a... |
US-7,965,218 |
SAR ADC An electronic device is provided for analog to digital conversion using successive approximation. The device comprises a first ADC stage. The first ADC stage... |
US-7,965,139 |
Amplifier offset and noise reduction in a multistage system Conventional multistage amplifiers oftentimes employ trim circuits or highly matched components to combat noise and offset contributions. Having trim circuitry... |
US-7,965,103 |
Quad to binary converter with directly connected and coupled outputs Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring... |
US-7,965,100 |
Transmitter with internal compensation for variance in differential data
line impedance In at least some embodiments, an electronic device includes a first data endpoint and differential data transceiver coupled to the first data endpoint. The... |
US-7,965,071 |
DC-DC boost converter A DC-DC boost converter is provided that generally maintains discontinuous mode operation in a generally efficient manner. To accomplish this, a clamp... |
US-7,965,067 |
Dynamic compensation for a pre-regulated charge pump An apparatus is provided. The apparatus comprises an error amplifier that amplifies the difference between a reference voltage and a feedback voltage, a first... |
US-7,964,919 |
Thin film resistors integrated at two different metal single die An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer... |
US-7,964,517 |
Use of a biased precoat for reduced first wafer defects in high-density
plasma process According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition... |
US-7,962,872 |
Timing analysis when integrating multiple circuit blocks while balancing
resource requirements and accuracy An aspect of the present invention provides for timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy. In... |
US-7,962,818 |
Reduced signaling interface method and apparatus This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial... |
US-7,962,817 |
IEEE 1149.1 and P1500 test interfaces combined circuits and processes In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture,... |
US-7,962,816 |
I/O switches and serializer for each parallel scan register An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning... |
US-7,962,815 |
Tap demultiplexer with select and select one outputs for HTML An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these... |
US-7,962,814 |
Mode selection based on special sequence of state machine states A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states... |
US-7,962,813 |
1149.1 tap linking modules IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for... |
US-7,962,812 |
Scan controller control input to sequential core without scan path Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing... |
US-7,962,183 |
Apparatus for and method of managing peak current consumption of multiple
subsystems in a mobile handset A novel and useful mechanism for regulating and managing the peak current consumption of the subsystems in a mobile handset device. The mechanism of the present... |
US-7,962,139 |
Reduction of handover latencies in a wireless communication system Systems and methods for reduction of handover latencies in wireless communication systems are described herein. Some illustrative embodiments include a wireless... |
US-7,962,112 |
Heterodyne receiver A heterodyne receiver comprising a gain controllable RF mixer (14) which has a first input connected to a first local oscillator (16) and a second input... |
US-7,961,892 |
Apparatus and method for monitoring speaker cone displacement in an audio
speaker An apparatus for monitoring speaker cone displacement in an audio speaker includes: (a) an electromagnetic coil structure; (b) a ferrous core structure; the... |