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Patent # Description
US-7,674,707 Manufacturable reliable diffusion-barrier
Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal...
US-7,674,682 Capacitor integration at top-metal level with a protective cladding for copper surface protection
An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and...
US-7,673,294 Mechanism for pipelining loops with irregular loop control
This invention modifies an irregular software pipelined loop conditioned upon data in a condition register in a compiler scheduled very long instruction word...
US-7,673,120 Inter-cluster communication network and heirarchical register files for clustered VLIW processors
A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files...
US-7,673,119 VLIW optional fetch packet header extends instruction set space
This invention is useful in a very long instruction word data processor that fetches a predetermined plural number of instructions each operation cycle. A...
US-7,673,101 Re-assigning cache line ways
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
US-7,673,091 Method to hide or reduce access latency of a slow peripheral in a pipelined direct memory access system
A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent...
US-7,673,076 Concurrent read response acknowledge enhanced direct memory access unit
An enhanced direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response...
US-7,672,102 Electrical overstress protection
In one aspect, a method for protection of an integrated circuit device includes but is not limited to detecting a first current in the integrated circuit device,...
US-7,671,667 Rapidly activated current mirror system
One embodiment of the invention includes a current mirror system. The system comprises a master circuit configured to conduct a first current in response to an...
US-7,671,663 Tunable voltage controller for a sub-circuit and method of operating the same
The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a ...
US-7,671,633 Glitch free 2-way clock switch
The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate...
US-7,671,445 Versatile system for charge dissipation in the formation of semiconductor device structures
The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200),...
US-7,671,428 Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from...
US-7,671,408 Vertical drain extended MOSFET transistor with vertical trench field plate
A vertical drain extended metal-oxide semiconductor field effect (MOSFET) transistor or a vertical double diffused metal-oxide semiconductor (VDMOS) transistor...
US-7,670,952 Method of manufacturing metal silicide contacts
A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also...
US-7,670,920 Methods and apparatus for forming a polysilicon capacitor
An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a...
US-7,670,917 Semiconductor device made by using a laser anneal to incorporate stress into a channel region
In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming...
US-7,670,913 Method for forming ultra-thin low leakage multiple gate devices using a masking layer over the semiconductor...
The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment,...
US-7,670,892 Nitrogen based implants for defect reduction in strained silicon
A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain...
US-7,670,890 Silicide block isolated junction field effect transistor source, drain and gate
An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain...
US-7,670,888 Low noise JFET
Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the...
US-7,669,313 Method for fabricating a thin film resistor semiconductor structure
A method is provided of fabricating a thin film resistor semiconductor structure. In one aspect of the invention, the method includes forming a dielectric layer...
US-7,669,243 Method and system for detection and neutralization of buffer overflow attacks
A method for detecting a stack buffer overflow attack is provided that includes receiving a memory access request from a processor core of a system, and...
US-7,669,109 Hardware-efficient low density parity check code for digital communications
A low density parity check (LDPC) code for a belief propagation decoder circuit is disclosed. LDPC code is arranged as a macro matrix (H) representing block...
US-7,669,099 Optimized JTAG interface
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
US-7,668,564 Slow uplink power control
Embodiments of the invention provide embodiments of the invention provide and method, network entity and user equipment for slow uplink power control of user...
US-7,668,321 Automatic power foldback for audio applications
A power foldback circuit to automatically control the power of an audio amplifier by using the volume inputs to a pre-amp source which drives the audio...
US-7,668,313 Recipient-encrypted session key cryptography
A method for protecting secret keys, such as HDCP device key sets, during the manufacturing process is disclosed. In particular, the present invention comprises...
US-7,668,265 Ultra wideband interference cancellation for orthogonal frequency division multiplex transmitters by...
A method of wirelessly communicating is disclosed. The method comprises determining a matrix W based in part on limiting a plurality of active interference...
US-7,668,251 Scalable post-channel estimate phase corrector, method of correction and MIMO communication system employing...
The present invention provides a post-channel estimate phase corrector for use with a multiple-input, multiple-output (MIMO) receiver employing M receive...
US-7,668,248 High-performance LDPC coding for digital communications in a multiple-input, multiple-output environment
Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is...
US-7,668,247 Methods and systems for performing an overlap-and-add operation
A system is provided that includes a first device 110A that transmits an information symbol with a zero-padded suffix (ZPS) and a second device 110B that...
US-7,668,243 Audio and video clock synchronization in a wireless network
System and method for synchronizing clocks and maintaining packet timing relationships in a wireless communications system. A preferred embodiment further...
US-7,668,232 System and method to determine power cutback in communication systems
A system and method for adaptively determining power cutback in communication system is described. According to an embodiment, the receiver determines noise on...
US-7,668,224 Encoding for digital communications in a multiple-input, multiple-output environment
Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is...
US-7,668,199 Methods and systems for communicating using transmitted symbols associated with multiple time durations
In at least some embodiments, a system may comprise one or more devices configurable to communicate according to a first protocol that permits interpretation of...
US-7,668,126 Beacon coordination and medium access
Each of a plurality of nodes in a wireless network is capable of generating, transmitting, and receiving beacons in a distribute fashion. Each beacon contains...
US-7,668,075 Versatile system for dual carrier transformation in orthogonal frequency division multiplexing
Embodiments of the invention provide a versatile system for selectively spreading carrier data across multiple carrier paths within an Orthogonal Frequency...
US-7,668,022 Integrated circuit for clock generation for memory devices
A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data...
US-7,667,997 Method to improve ferroelectronic memory performance and reliability
One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method...
US-7,667,548 Oscillation maintenance circuit for half duplex transponder
An oscillation maintenance circuit for a half-duplex transponder that has an LC resonant circuit, a storage capacitor and a rectifier connected to charge the...
US-7,667,540 Class-AB driver design with improved frequency response
A class-AB driver design with improved frequency response is disclosed. In one embodiment, the class-AB driver includes a push-pull output stage, a trans-linear...
US-7,667,539 Low-voltage wide-range linear transconductor cell
An improved low-voltage, low-power, wide range, and linear Gm Cell is disclosed. In one embodiment, a method of linearizing output current with an input voltage...
US-7,667,525 Bus switch circuit with back-gate control during power down
The bus switch with back gate control circuit includes: an NMOS transistor coupled between a first port and a second port; a PMOS transistor coupled in parallel...
US-7,667,519 Biasing circuit for pass transistor for voltage level translator circuit
A pass transistor signal level translator between a first voltage level and a higher second voltage level having a bias circuit for the pass transistor including...
US-7,667,511 Efficient pulse amplitude modulation transmit modulation
Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408...
US-7,667,505 Quadrature divide-by-three frequency divider and low voltage muller C element
A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with...
US-7,667,501 Correlated double sampling technique
A sampling circuit according to correlated double sampling to generate a difference of two voltages at a sampling node, with the second voltage representing the...
US-7,667,441 Inductive element for a multi-phase interleaved power supply and apparatus and method using the same
An inductive element for transforming and/or regulating voltage input from a multi-phase, interleaved power supply system into an output voltage to a load is...
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