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Patent # Description
US-7,739,669 Paced trace transmission
The trace interface and the trace receiver may be synchronized by the trace receiver controlling the pace of trace generation. The interface generates a clock...
US-7,739,668 Method and system of profiling applications that use virtual memory
A method and system of profiling applications that use virtual memory. At least some of the illustrative embodiments are methods comprising executing a traced...
US-7,739,569 Boundary scan path method and system with functional and non-functional scan cell memories
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a...
US-7,739,525 Device and system for controlling parallel power sources coupled to a load
A device and system for controlling current from plural parallel power sources having inrush current hot-swapping capabilities to a load are disclosed. The...
US-7,739,453 Providing information associated with a cache
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
US-7,739,440 ATA HDD interface for personal media player with increased data transfer throughput
This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media...
US-7,739,435 System and method for enhancing I2C bus data rate
A system for, and method of, enhancing I2C bus data rate and an electronic assembly including the system or the method. In one embodiment, the system includes:...
US-7,738,655 Interference canceller tap sharing in a communications transceiver
A novel mechanism for sharing filter taps across a plurality of interference cancellers. Each interference canceller may be directed to impairment, such as...
US-7,738,567 Baseline wander correction for communication receivers
A novel and useful baseline wander correction mechanism for use with transformer coupled baseband communication receivers. Parametric estimation of the...
US-7,738,154 Lubricating micro-machined devices using fluorosurfactants
A method of lubricating MEMS devices using fluorosurfactants 42. Micro-machined devices, such as a digital micro-mirror device (DMD.TM.) 940, which make repeated...
US-7,738,038 Content-dependent scan rate converter with adaptive noise reduction
A content-dependent scan rate converter with adaptive noise reduction that provides a highly integrated, implementation efficient de-interlacer. By identifying...
US-7,737,989 System and method for computing color correction coefficients
System and method for computing coefficients for color correcting rendered colors used in displaying images. A preferred embodiment comprises measuring color...
US-7,737,986 Methods and systems for tiling video or still image data
The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing...
US-7,737,791 Spread spectrum clocking in fractional-N PLL
In applications that use fractional-N phase locked loops (PLLs), the use of spread spectrum clocking (SSC) to reduced electromagnetic interference (EMI) would be...
US-7,737,747 Scheme for controlling rise-fall times in signal transitions
A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a...
US-7,737,717 Current-voltage-based method for evaluating thin dielectrics based on interface traps
A method for evaluating gate dielectrics (100) includes providing a test structure (101). The test structure includes a gate stack that includes a gate electrode...
US-7,737,679 Poly phase solid state watt hour meters
An electronic energy meter includes a first sigma delta modulator having an electrically isolated digital data output. A power supply stage coupled to a first...
US-7,737,671 System and method for implementing high-resolution delay
A system and method is provided for providing a deadband switching time delay. One embodiment of the present invention includes a switching regulator system. The...
US-7,737,016 Two-print two-etch method for enhancement of CD control using ghost poly
According to various embodiments, two-print two-etch methods and devices are disclosed that can be used to form features, such as ghost features, on a substrate....
US-7,737,015 Formation of fully silicided gate with oxide barrier on the source/drain silicide regions
A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a...
US-7,736,986 Integrated stacked capacitor and method of fabricating same
An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide, a second capacitor film (48) and a first dielectric (26)...
US-7,736,983 High threshold NMOS source-drain formation with As, P and C to reduce damage
Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in...
US-7,736,961 High voltage depletion FET employing a channel stopping implant
A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well...
US-7,736,026 Lamp reflector cooling air deflector
To improve the cooling efficiency and ensure uniform cooling of all portions of the inside back surface of the reflector, a deflector (108) has been developed....
US-7,735,056 Automated circuit design dimension change responsive to low contrast condition determination in photomask phase...
The present application is directed to methods of forming a phase pattern for an integrated circuit feature described in a design database as having a first...
US-7,734,971 Scan output connection in tap and scan test port
Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves...
US-7,734,044 Method and apparatus for synchronous stream cipher encryption with reserved codes
A method and apparatus for a signal encryption device constructed to perform synchronous stream cipher encryption for a sequence of input words with restricted...
US-7,733,763 Memory-efficient ADSL transmission in the presence of TCM-ISDN interferers
A method of communicating data across a channel that experiences near-end cross talk (NEXT) interference and far-end cross talk (FEXT) interference in alternate...
US-7,733,686 Pulse width control for read and write assist for SRAM circuits
An exemplary system and methods implementing pulse width control in SRAM bit cell arrays that vary in size are described.
US-7,733,682 Plateline driver for a ferroelectric memory
One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory...
US-7,733,424 Method and apparatus for analog graphics sample clock frequency verification
A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for sampling...
US-7,733,261 Hybrid analog to digital converter circuit and method
A hybrid analog to digital converter circuit for a feedback input to a digital controller of a power supply includes a high resolution, analog to digital...
US-7,733,180 Amplifier for driving external capacitive loads
An apparatus having a zero-pole that is dependant on an equivalent series resistance (ESR) and a load is provided. The apparatus comprises an amplifier stage...
US-7,733,179 Combination trim and CMFB circuit and method for differential amplifiers
A differential amplifier (10-1,2) includes an input stage (7) including first (M1) and second (M2) input transistors and first (4A) and second (4B) load devices....
US-7,733,177 Method and system for calculating the pre-inverse of a nonlinear system
An apparatus is provided to determine pre-distortion for a nonlinear system. The apparatus comprises a datapath and a power amplifier. The datapath employs...
US-7,733,174 Feedback controlled power limiting for signal amplifiers
An apparatus is provided. The apparatus includes an amplifier, differential amplifiers, and FETs. The amplifier has an intermediate node and an output node, and...
US-7,733,169 Slew rate and settling time improvement circuitry and method for 3-stage amplifier
An operational amplifier (1B) amplifies an input signal (Vin) to produce an output signal (Vout), and includes a 3-stage amplifier (1C) including a first...
US-7,733,151 Operating clock generation system and method for audio applications
A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency...
US-7,733,135 High side boosted gate drive circuit
A high-side boosted gate drive circuit is disclosed. In a particular example, an output driver is described, comprising a switching device configured to...
US-7,733,110 Parallel scan distributors and collectors and process of testing integrated circuits
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-7,733,072 Step-down/step-up DC/DC converter apparatus and method with inductor current threshold value adjusting
The invention provides a switching power supply device that can restrain the variation in the ripple of the output voltage corresponding to the variation in the...
US-7,732,863 Laterally diffused MOSFET
A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS...
US-7,732,345 Method for using a modified post-etch clean rinsing agent
The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a...
US-7,732,324 Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer
One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor...
US-7,732,313 FUSI integration method using SOG as a sacrificial planarization layer
A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from...
US-7,732,312 FUSI integration method using SOG as a sacrificial planarization layer
A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from...
US-7,732,284 Post high-k dielectric/metal gate clean
A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal...
US-7,732,225 Method for measuring contamination in liquids at PPQ levels
A method of manufacturing a semiconductor device includes placing a sample of a liquid chemical containing a contaminant on a substantially impurity-free surface...
US-7,730,377 Layered decoding of low density parity check (LDPC) codes
A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a...
US-7,730,374 Self test circuit for a semiconductor intergrated circuit
A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105...
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