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Patent # Description
US-9,468,107 Interdigitated chip capacitor assembly
A method of registering terminals on an interdigitated chip capacitor ("IDC") with a plurality of contact pads on a substrate. At least one vertically extending...
US-9,468,087 Power module with improved cooling and method for making
Disclosed examples include power modules and fabrication methods therefor in which one or more power device dies include a switching device and a second device...
US-9,468,065 Combined hybrid and local dimming control of light emitting diodes
An LED backlight controller combines global/hybrid and local brightness/dimming control for an LED backlight illuminator with local regions illuminated by...
US-9,467,703 Signaling signed band offset values for sample adaptive offset (SAO) filtering in video coding
A method for signaling sample adaptive offset (SAO) band offset syntax elements in a video encoder is provided that includes receiving a plurality of band...
US-9,467,394 Time and frequency diversity modulation system and method
A method of encoding a set of L bits for transmission on a transmission band through a transmission medium is provided, wherein L is a positive integer that is...
US-9,467,164 Apparatus and method for supporting polar code designs
A method includes simulating transmission of multiple symbols representing multiple bits over at least one communication channel, where the multiple symbols are...
US-9,467,128 Linearization circuit for high frequency signal phase adjustment
A circuit includes a phase adjustment capacitor (PAC) coupled to a signal path and configured to adjust a phase of a signal on the signal path. A transistor...
US-9,467,109 Differential amplifier with high-speed common mode feedback
The differential signals at the outputs of a differential amplifier quickly change in response to common mode changes in the output differential signals. The...
US-9,467,097 Edge correction to mitigate total harmonic distortion in class D amplifier
A circuit includes an amplifier output stage that includes a high switch and a low switch that generates a pulse width modulated (PWM) output signal to provide...
US-9,467,096 Amplifier system
One example includes an amplifier system. The system includes a precision amplifier portion comprising a first input stage configured to receive an input...
US-9,467,049 Control for switching between PWM and PFM operation in a buck converter
A buck switching voltage regulator, with high side and low side switching transistors, includes mode control circuitry for switching between PWM and PFM modes...
US-9,466,572 Ultraviolet energy shield for non-volatile charge storage memory
An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing....
US-9,466,520 Localized region of isolated silicon over recessed dielectric layer
An integrated circuit is formed by forming an isolation recess in a single crystal substrate which includes silicon, filling the isolation recess with isolation...
US-9,466,356 Array power supply-based screening of static random access memory cells for bias temperature instability
A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory...
US-9,466,288 Comparing differential ZC count to database to detect expected sound
A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. Sparse sound parameter information is...
US-9,465,904 Device pin mux configuration solving and code generation via Boolean satisfiability
This invention is a signal input/output design tool for integrated circuit input/output design. The connectivity capacity of at least multiplexer connecting...
US-9,465,767 Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and...
This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous...
US-9,465,759 Universal serializer architecture
Systems and methods for a universal Serializer-Deserializer (SerDes) architecture are described. In various implementations, a transceiver may include: a first...
US-9,465,753 Memory management unit that applies rules based on privilege identifier
A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on...
US-9,465,742 Synchronizing barrier support with zero performance impact
The barrier-aware bridge tracks all outstanding transactions from the attached master. When a barrier transaction is sent from the master, it is tracked by the...
US-9,465,741 Multi processor multi domain conversion bridge with out of order return buffering
An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each...
US-9,462,956 Calculating heart rate from acceleration signals containing cardiac activity signals
A heart monitor includes a single chest accelerometer (210), an analog signal conditioning and sampling section (215) responsive to said accelerometer to...
US-9,461,861 Time-domain windowing function
A smart utility network (SUN) device that includes an orthogonal frequency-division multiplexing (OFDM)-based transmitter. The OFDM-based transmitter including...
US-9,461,628 Single ended charge to voltage front-end circuit
Charge to voltage conversion integrator circuitry for data acquisition front-end and other applications to provide a single-ended up a voltage using an input...
US-9,461,439 Optoelectronic packages having magnetic field cancelation
A stacked optoelectronic packaged device includes a bottom die having a top surface including bottom electrical traces and a light source die coupled to...
US-9,461,131 High quality deep trench oxide
An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio...
US-9,461,060 Feed-forward bidirectional implanted split-gate flash memory cell
A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second...
US-9,461,046 LDMOS device with graded body doping
A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is...
US-9,461,035 High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit
A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding...
US-9,461,032 Bipolar ESD protection device with integrated negative strike diode
A bipolar ESD protection device includes a substrate having a p-type epi layer thereon including an epi region over an n-buried layer (NBL). An n-type isolation...
US-9,460,962 Substrate contact etch process
A semiconductor device with a deep trench has a dielectric liner formed on sidewalls and a bottom of the deep trench. A pre-etch deposition step of a two-step...
US-9,460,720 Powering-up AFE and microcontroller after comparing analog and truncated sounds
A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. The received analog signal is evaluated using...
US-9,459,886 Autonomous sleep mode
A system and method is disclosed that enables a peripheral or slave device to seamlessly transition in and out of sleep state while remaining completely...
US-9,459,352 Multi-sensor proximity sensing using a near zone light sensor and a far zone light sensor
An apparatus includes a light source to generate source light through an optically transmissive medium to an object. A receiver includes a near zone light...
US-9,459,339 Kalman filter for indoor positioning
A position estimation method for indoor positioning includes filtering an initial position estimate that includes a corresponding covariance that reflects the...
US-9,456,432 Clock synchronization and centralized guard time provisioning
Embodiments of the invention provide a method to accommodate clock drift and guard time in a centralized fashion. In one embodiment, a device is adapted to...
US-9,456,257 Device for transferring power from a first circuit to a second circuit
A power transfer system for transferring power from a first circuit to a second circuit by a differential signal generated in the first circuit includes a first...
US-9,455,851 Efficient encoding/decoding algorithm for MTS constrained MFSK communications
A method of encoding a data signal is disclosed. The method includes selecting a set of M ultrasonic frequencies, wherein each of the M ultrasonic frequencies...
US-9,455,721 FLL oscillator/clock with an FLL control loop including a switched capacitor resistive divider
An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an...
US-9,455,720 Universal oscillator
The disclosure provides a universal oscillator. The oscillator includes an amplifier array. The amplifier array includes one or more amplifiers. A control logic...
US-9,455,332 LDMOS transistor and method of forming the LDMOS transistor with improved Rds*Cgd
The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a...
US-9,455,312 Multiple depth vias in an integrated circuit
An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with...
US-9,455,252 Combining ZTCR resistor with laser anneal for high performance PMOS transistor
An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with...
US-9,455,222 IC having failsafe fuse on field dielectric
A fuse circuit includes a substrate, a top semiconductor layer doped a first conductivity type having a well doped a second conductivity type formed therein...
US-9,455,021 Array power supply-based screening of static random access memory cells for bias temperature instability
A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory...
US-9,454,437 Non-volatile logic based processing device
A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a...
US-9,454,203 Method, system and computer program product for reducing consumption of battery power
An information handling system is powered by a battery. In response to determining that a remaining amount of power within the battery has fallen below a first...
US-9,454,135 Manufactureable long cell with enhanced sensitivity and good mechanical strength
A method of providing a manufactureable long vapor cell with enhanced sensitivity and good mechanical strength, wherein the method provides a structure that...
US-9,454,003 Lense module
A lens assembly includes a first lens and a transducer attached to the first lens. A method of cleaning a lens includes vibrating the lens with a transducer...
US-9,453,882 Scan paths with gating, enable, and select decode control circuits
An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the...
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