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Patent # Description
US-9,494,656 Systems and methods for determining battery state of charge
Systems (50, 200) and methods for determining a state of charge of a battery (52, 102, 150, 202) are provided. The system (50, 200) includes a power source (56,...
US-9,494,648 Comparator with load signal output connected to timestamp value register
This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined...
US-9,494,643 Bi-directional TCK lead carrying TCK and frame data in/out signal
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication...
US-9,494,640 Parallel scan distributors and collectors and process of testing integrated circuits
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-9,491,838 LED matrix manager
Circuits for controlling a plurality of LEDs connected in series are disclosed herein. The circuit includes a plurality of switches, wherein each switch is...
US-9,491,573 Communication device for providing value-added information based upon content and/or context information
A communication device, for use in a communication network, provides value-added information to a user of the communication device. The communication device...
US-9,491,375 Method, system and computer program product for reducing a delay from panning a camera system
For reducing a delay from panning a camera system, an estimate is received of a physical movement of the camera system. In response to the estimate, a...
US-9,491,012 Direct over-sampled pulse shaping circuit with flip flops and LUT
Example embodiments of systems and methods of direct oversampled low PAR pulse shaping encapsulating DSSS spreading are disclosed herein. Pulse-shaping of a...
US-9,490,967 Communication system and method
A communication system includes a receiver for decoding data having three states of -1, 0, and 1. The receiver includes a first input coupled to a first data...
US-9,490,783 Area efficient multi bit flip flop topologies
The invention is an intelligent connection of the internal scan logic in a multi-bit flip-flop register. Individual bits in this register are connected in a...
US-9,490,747 Re-configurable single transformer quadrature voltage controlled oscillator
A quadrature voltage controlled oscillator (QVCO). The QVCO includes a first node for providing a first quadrature signal, a second node for providing a second...
US-9,490,518 System for launching a signal into a dielectric waveguide
A system is provided for transmitting sub-terahertz electro-magnetic radio frequency (RF) signals using a dielectric waveguide (DWG) having a dielectric core...
US-9,490,162 Use of dielectric slots for reducing via resistance in dual damascene process
An integrated circuit may include dual damascene interconnects formed using a via-first dual damascene process or a trench-first dual damascene process. The...
US-9,490,143 Method of fabricating semiconductors
A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The...
US-9,489,925 Using natural movements of a hand-held device to manipulate digital content
A mobile device, such as a smart phone, is provided with a camera. Digital content displayed on display screen of the mobile device may be manipulated in...
US-9,489,332 System and method for virtual hardware memory protection
A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus...
US-9,489,314 Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC
This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip...
US-9,489,307 Multi domain bridge with auto snoop response
An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each...
US-9,489,208 Operating a pipeline flattener in order to track instructions for complex breakpoints
A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a...
US-9,489,197 Highly efficient different precision complex multiply accumulate to enhance chip rate functionality in DSSS...
This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using...
US-9,489,098 Method, apparatus and system for level shifting of common mode voltage from input to output for capacitive...
A circuit for a level shifting of common mode voltage. The circuit includes a first amplifier, wherein the input of the first amplifier is coupled to a voltage...
US-9,489,093 Capacitive sensing apparatus and methods
One or more waveform generators impose an input waveform across touch sensor components. Phase shift detection logic measures a phase shift between the input...
US-9,487,397 Coatings for relatively movable surfaces
A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating...
US-9,485,520 Parallel motion estimation in video coding
Methods for improved parallel motion estimation are provided that decouple the merging candidate list derivation and motion estimation for merge mode and skip...
US-9,485,506 Method and system for constraining slice header processing overhead in video coding
A method for encoding a picture of a video sequence in a bit stream that constrains slice header processing overhead is provided. The method includes computing...
US-9,484,979 Switching between transmit and receive modes in a wireless transceiver
A wireless transceiver decodes a receive signal to extract data contained in the receive signal. A processing block contained in the wireless transceiver then...
US-9,484,921 LVDS input circuit with comparators, or gate, and multiplexer
First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an...
US-9,484,913 Emulation of LED input characteristics in BICMOS process
An LED input emulator to interface a signal source designed for use with an LED optocoupler, to capacitive or other galvanic isolation circuitry, emulating LED...
US-9,484,858 Inductive coupled pass transistor quadrature voltage controlled oscillator
A quadrature voltage controlled oscillator (QVCO) for providing an oscillating output signal. The QVCO includes a first oscillating circuit for producing a...
US-9,484,630 Chip to dielectric waveguide interface for sub-millimeter wave communications link
In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue....
US-9,484,614 Dielectric waveguide signal divider
A dielectric waveguide (DWG) has a longitudinal core member with a first dielectric constant value surrounded by a cladding with a cladding dielectric constant...
US-9,484,450 Integrated channel diode
A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over...
US-9,484,435 MOS transistor with varying channel width
One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the...
US-9,484,095 TCAM providing efficient move contents operation
An embodiment of the invention includes a Ternary Content Addressable Memory (TCAM) that includes a group of TCAM block. Each TCAM block stores a number of...
US-9,483,638 Method and system for preventing unauthorized processor mode switches
A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing...
US-9,483,429 Unified input/output controller for integrated wireless devices
A novel and useful apparatus for and method of a unified IO controller well suited for use in integrated wireless devices incorporating multiple functions. The...
US-9,483,065 Power regulation with load detection
One embodiment of the present invention includes a power regulator system. The system includes a power stage configured to provide an output voltage to a load...
US-9,482,718 Integrated circuit
Integrated circuits and methods for testing integrated circuits are disclosed herein. An embodiment of an integrated circuit includes a microprocessor and...
US-9,482,717 Wafer scale testing using a 2 signal JTAG interface
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-9,481,572 Optical electronic device and method of fabrication
An optical electronic device and method that forms cavities through an interposer wafer after bonding the interposer wafer to a window wafer. The cavities are...
US-RE46,193 Distributed power control for controlling power consumption based on detected activity of logic blocks
An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller...
US-9,479,932 ID-based control unit-key fob pairing
A key fob includes a transceiver to send and receive signals, a memory to store a key fob identification (KFID), and a processor coupled to said transceiver and...
US-9,479,882 Initial command to switch transistors disconnecting keys from microphone line
An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in...
US-9,479,867 Method and circuitry for direction of arrival estimation using microphone array with a sharp null
A device is configured for identifying a direction of a sound. The device includes a controller comprising circuitry. The circuitry is configured to receive a...
US-9,479,366 IIR DFE updating gain and time constants using LMS equations
A method for adapting a mixed signal Infinite Impulse Response (IIR) Decision Feedback Equalizer (DFE) using pivot taps and monitor taps is disclosed. The...
US-9,479,186 Gain and offset correction in an interpolation ADC
In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a...
US-9,479,134 Position detecting system
A position detecting system detects and responds to the movement of a target through a sensing domain area of a plane. The movement causes the amount of the...
US-9,478,510 Self-aligned under bump metal
An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with...
US-9,477,626 2-pin interface with data input, data output, address match input
A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One...
US-9,477,246 Low dropout voltage regulator circuits
In an embodiment, a voltage regulator is disclosed. The voltage regulator circuit includes a switch, a first feedback circuit and a second feedback circuit. The...
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