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Stack register reference control bit in source operand of instruction
A processor is disclosed herein that may execute an instruction that includes an immediate value and a reference to a register accessible to the processor. The...
Propagation of data throughout an area using distributed transponders and
scanners with relative movement
A method is provided for propagating data among multiple locations in an area. The method includes using a plurality of transponders distributed throughout the...
Preamble for a TFI-OFDM communications system
System and method for simplifying preamble detection and reducing power consumption in receivers. A preferred embodiment comprises a preamble made up of two...
Beam forming for transmit using bluetooth modified hopping sequences
A communication circuit (28) is designed with a signal processing circuit (370) arranged to produce a first plurality of data signals and receive a second...
An amplifier comprising an analog amplifier which outputs a first current and a second current. The amplifier also comprises a first digital amplifier coupled to...
Audio amplifier and methods of generating audio signals
Audio amplifiers and methods of generating audio signals are disclosed. A disclosed example amplifier comprises a first driver to receive a first signal; a...
System and method for reducing power-on-transient current magnitude
System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch...
Low drop voltage regulator with instant load regulation and method
An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying...
Supervising and sequencing commonly driven power supplies with digital
Methods and apparatus for power monitoring with sequencing and supervision are disclosed. An example method disclosed herein includes supervising a first power...
Simultaneous primary, secondary, and tertiary synchronization codes over
A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a...
MAC aggregation frame with MSDU and fragment of MSDU
Apparatus and methods implement aggregation frames and allocation frames. The aggregation frames include a plurality of MSDUs or fragments thereof aggregated or...
Dual mode SRAM architecture for voltage scaling and power management
The present disclosure provides a dual-mode voltage controller, a method of supplying voltage to SRAM periphery circuits and an integrated circuit. In one...
Decoder based set associative repair cache systems and methods
The present invention facilitates memory devices and operation thereof by employing a repair cache system 600 to correct or repair identified faulty memory...
Methods and systems for accessing memory
One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method...
Two-dimensional blazed MEMS granting
A method for assuring a blazed condition in a DMD device used in telecommunications applications. By meeting certain conditions in the fabrication and operation...
Non-contacting electrostatically driven MEMS device
A microelectromechanical device has a movable first electrode and stationary second and third electrodes oriented parallel with the substrate. The first...
Interferometers of high resolutions
The present invention provides a microstructure device comprising multiple substrates with the components of the device formed on the substrates. In order to...
Methods and apparatus to control current steering digital to analog
Methods and apparatus to control current steering digital to analog converters are described herein. In one example, a digital to analog converter includes a...
Parallel scan distributors and collectors and process of testing
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
Method and system to dynamically compensate for probe tip misalignement
when testing integrated circuits
Method for dynamically compensating probe tip misalignment with a semiconductor wafer. The wafer is located on a handler and the wafer is adjusted to a first...
Plastic semiconductor package having improved control of dimensions
A device with a semiconductor chip assembled on a planar substrate and encapsulation compound surrounding the assembled chip and a portion of the substrate near...
Doped WGe to form dual metal gates
A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body,...
Method for making a micromechanical device by using a sacrificial
A method is disclosed for forming a micromechanical device. The method includes fully or partially forming one or more micromechanical structures multiple times...
Solid state heat pump
In accordance with the invention, there are methods for transferring heat, for heating and cooling, and there is a solid state heat pump. The solid state heat...
Expanded memory for communications controller
One embodiment of the present invention includes a communication system. The system comprises a communications controller configured to control transmission and...
Apparatus and method for driving a pulse width modulation reference signal
An apparatus for driving a pulse width modulation reference signal includes: (a) A converting unit receiving an input signal at an input locus and presenting an...
Adaptive voltage control for SRAM
The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM...
Systems and devices for implementing sub-threshold memory devices
Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory...
Transistor overcurrent detection circuit with improved response time
A circuit and method for determining overcurrent in a FET detects an output voltage of the FET in both a positive and negative polarity. The related positive or...
Feed-forward circuitry and corresponding error cancellation circuit for
cascaded delta-sigma modulator
A cascaded delta-sigma modulator includes a first stage delta-sigma modulator (10A) having first adder (2) followed by first (3) and second (6) integrators, a...
Pulse-width modulation of pulse-code modulated signals at selectable or
dynamically varying sample rates
Digital audio circuitry including modulation circuitry (35; 135) for generating a pulse-width modulated (PWM) signal from processed pulse-code modulated (PCM)...
Common-mode bandwidth reduction circuit and method for differential
An amplifier driver circuit (10) includes first (11-1) and second (11-2) feedback amplifiers including first (14-1) and second (14-2) upper current mirrors,...
Circuit assembly for converting a differential input clock signal pair
into a single-ended output clock signal
A circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal comprises a NMOS differential amplifier (20)...
Semiconductor device with an improved solder joint
A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and...
Methods and systems to mitigate etch stop clipping for shallow trench
The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape...
Method and system of control flow graph construction
A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch...
Scan based testing of an integrated circuit containing circuit portions
operable in different clock domains...
An integrated circuit containing an encoder which avoids setup/hold violation in a memory element of one clock domain, when receiving data from another memory...
IEEE 1149.1 and P1500 test interfaces combined circuits and processes
In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally...
Sampling mixer with asynchronous clock and signal domains
A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having...
System and method for displaying images
System and method for enhancing image quality in a display system. A preferred embodiment comprises a variable light source capable of producing a light of...
Weight level generating method and device utilizing plural weights at
different time rates
A weight level generator is provided. Weight level generator W has plural weight generators 5-1-5-j. At least one of said plural weight generators is used at at...
Power savings with a level-shifting boundary isolation flip-flop (LSIFF)
and a clock controlled data retention...
An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An...
Method for contaminant removal
Method for removing contaminants from a surface during semiconductor fabrication. A preferred embodiment comprises developing a resist layer on a top surface of...
IP core design supporting user-added scan register option
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test...
Image and audio transform methods
Inverse discrete cosine transform (type-III DCT), used in video/image and audio coding, is implemented in the form of FFT to lower computational complexity.
Integrated circuit having a supply voltage controller capable of floating
a variable supply voltage
An integrated circuit includes a supply voltage controller operable to receive a plurality of control signals and at least one circuit supply voltage and to...
Soft-start circuit for power regulators
One embodiment of the present invention includes a system for providing a soft-start for a power regulator comprising a differential transistor pair that...
Variable capacitor single-electron transistor including a P-N junction
The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a...
Imaging device and imaging device drive method
The problem of the invention is to improve S/N and provide a high-sensitivity imaging device. The CMOS image sensor includes multiple pixels arranged in a...
Non-uniformly doped high voltage drain-extended transistor and method of
The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure...