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Method and apparatus for managing energy in plural energy storage units
A system for managing energy stored in a plurality of series connected energy storage units has a plurality of energy storage unit controllers, each controller...
Versatile system for optimizing current gain in bipolar transistor
Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and...
Activation of CMOS source/drain extensions by ultra-high temperature
A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over...
Open source/drain junction field effect transistor
The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET)...
Thick oxide film for wafer backside prior to metalization loop
A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick...
TAP domain selection circuit with AUXI/O1 or TDI lead
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
Scaled time trace
The trace logic are separate from the clocks that operate the system logic. This allows the chip to be placed in a special mode where the functional logic is...
Encrypted and other keys in public and private battery memories
Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In...
Partial register forwarding for CPUs with unequal delay functional units
A data processing apparatus includes a register file and a plurality of functional units. At least one and not all the plurality of the functional units is a...
Mobile receiver phase correction circuit
A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (r.sub.j(i+.tau..sub.j), i=0-N-1) during a first...
Calibration circuitry and delay cells in rectilinear RF power amplifier
Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high...
Simultaneous LVDS I/O signaling method and apparatus
First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an...
Semiconductor device with improved contact fuse
One aspect of the invention provides an integrated circuit(IC) [400b]. The IC comprises transistors [410b] and contact fuses [422b]. The contact fuses each...
Package for an integrated circuit
According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of...
Thermally enhanced single inline package (SIP)
In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A...
Structure for dual work function metal gate electrodes by control of
Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or...
Optimized circuit design layout for high performance ball grid array
A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a...
Transistors, integrated circuits, systems, and processes of manufacture
with improved work function modulation
A process (200) for making integrated circuits with a gate, uses a doped precursor (124, 126N and/or 126P) on barrier material (118) on gate dielectric (116)....
Semiconductor device manufactured using a laminated stress layer
There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a...
Illumination aperture for projection display
An optical system and method of increasing the contrast of a projected image. The optical system (1800) comprises a combination of aperture stops (1810, 1812) in...
Select and enable leads connecting IC taps and embedded controller
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
Program counter range comparator with equality, greater than, less than
and non-equal detection modes
An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators...
Multi-carrier transmitter for ultra-wideband (UWB) systems
System and method for a multi-carrier ultra-wideband (UWB) transmitter. A preferred embodiment comprises an UWB transmitter (for example, transmitter 300) taking...
Method and apparatus for spatial and temporal dithering
An apparatus and method for spatially and temporally dithering pixels. A pixel comprising at least one color component of a first size is provided. A dither...
Aluminum leadframes for semiconductor QFN/SON devices
A post-mold plated semiconductor device has an aluminum leadframe (105) with a structure including a chip mount pad and a plurality of lead segments without...
Non-pull back pad package with an additional solder standoff
Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback...
Removable and replaceable tap domain selection circuitry
Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is...
Method and system of identifying overlays
A method and system of identifying overlays. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system...
Merging branch information with sync points
A method for merging branch information with sync points is disclosed herein. The method comprises determining whether a sync point is to be generated concurrent...
Dynamic clock switch mechanism for memories to improve performance
This invention improves cache operation by dynamically extending one state of a clock signal supplied to a cache on operation cycles when a cache fill operation...
Context save and restore with a stack-based memory structure
A multi-threaded processor adapted to couple to external memory comprises a controller and data storage operated by the controller. The data storage comprises a...
Layered celp system and method with varying perceptual filter or
short-term postfilter strengths
Layered code-excited linear prediction (CELP) speech encoders have progressively weaker perceptual weighting filters for each of the successive enhancement...
Programmable extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least...
Process of increasing source rate on acceptable side of threshold
A process (111,101) of sending packets of real-time information at a sender (311) includes initially generating packets of real-time information with a source...
Stabilization for devices such as hand-held camcorders segments a low-resolution frame into a region of reliable estimation, refines the motion vectors of that...
Data encoding in a clocked data interface
One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over...
Systems and methods for kickback reduction in an ADC
Various systems and methods for analog to digital conversion are disclosed. For example, some embodiments of the present invention provide analog to digital...
All digital phase locked loop system and method
An all digital PLL system generates an analog oscillator signal at intermediate frequencies to achieve averaged oscillator frequencies at an extremely high...
Low glitch offset correction circuit for auto-zero sensor amplifiers and
An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero...
Switching power supply device
This invention prevents undershoot, etc., occurring in the output during the transition from intermittent control mode to continuous control mode to hinder...
Distributed high voltage JFET
A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially...
Method and system for debugging a software program
A profiling system. At least some of the illustrative embodiments are integrated circuit devices comprising a processing circuit configured to execute a target...
Prioritizing caches having a common cache level
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
Hardware configurable hub interface unit
A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application...
Processes, circuits, devices, and systems for encryption and decryption
and other purposes, and processes of making
A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a...
Reconfigurable topology for switching and linear voltage regulators
A configurable voltage regulator (28; 128) operable in either of two selectable modes or topologies is disclosed. In one disclosed embodiment, the voltage...
Drive circuit and drain extended transistor for use therein
A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also...
Method for conditioning a microelectronics device deposition chamber
The present invention provides, in one aspect, the present invention provides, in one embodiment, a method of conditioning a deposition chamber 100. This method...
Semiconductive device fabricated using subliming materials to form
The invention provides a method of fabricating a semiconductive device . In this embodiment, the method comprises depositing a hydrocarbon layer  over...
Device comprising an ohmic via contact, and method of fabricating thereof
Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a...