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Defect control in gate dielectrics
A method for improving high-.kappa. gate dielectric film (104) properties. The high-.kappa. film (104) is subjected to a two step anneal sequence. The first...
Work function control of metals
Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a `mid gap` metal, is manipulated in...
Integration of pre-S/D anneal selective nitride/oxide composite cap for
improving transistor performance
The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility...
Apparatus and method for identifying proper orientation and electrical
conductivity between a semiconductor...
A semiconductor device with a semiconductor die thereon and a contactor board are electrically coupled when the electrically conductive elements on the...
Method of processing semiconductor wafers
A method of processing semiconductor wafers comprises forming a pattern of recesses in an exposed surface of each wafer in a lot, prior to an epitaxy step. At...
Ultra dark polymer
A method and a material for creating an antireflective coating on an integrated circuit. A preferred embodiment comprises applying a dark polymer material on a...
Sparse maximum likelihood decoder for block codes
A method is provided to decode data encoded by any block code in a manner that substantially improves the error correction capability of the block codes, and...
Method for synchronizing an image data source and a resonant mirror system
to generate images
System and method for synchronizing the low speed mirror movement of a mirror display system with incoming frame or video signals, and synchronizing buffered...
Process, supply, and temperature insensitive integrated time reference
Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations...
Signal driver having selectable aggregate slew rate to compensate for
varying process, voltage or temperature...
A signal driver having a selectable aggregate slew rate, a method of driving a signal driver and a signal driver incorporating the driver or the method. The...
Routing engine, method of routing a test probe and testing system
employing the same
Embodiments of the present disclosure provide a routing engine, a method of routing a test probe and a testing system employing the router or the method. In one...
Low noise vertical variable gate control voltage JFET device in a BiCMOS
process and methods to build this device
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It...
Adjustable lithography blocking device and method
The present invention provides, in one embodiment, a method (100) of manufacturing a semiconductor device. A conventionally formed reticle is positioned over a...
System and method to increase die stand-off height
In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of...
System and method for inhibiting and containing resin bleed-out from
adhesive materials used in assembly of...
System and method for preventing resin-based adhesive from contacting a substrate to minimize resin bleed-out and contamination. A preferred embodiment comprises...
Automating optimal placement of macro-blocks in the design of an
Automating optimal placement of macro-blocks in the design of an integrated circuit. A first set of placements is generated and corresponding measures of...
Distributed element generator, method of generating distributed elements
and an electronic design automation...
The present invention provides a distributed element generator for use with an electronic design automation tool. In one embodiment, the distributed element...
Digital storage element architecture comprising dual scan clocks and gated
A digital storage element (e.g., a flip-flop or a latch) includes a master transparent latch that receives functional data from a data input port and scan data...
Efficient trace triggering
A system comprising a processor core adapted to execute software code and a trace logic coupled to the processor core and comprising a storage. The storage...
Layered CELP system and method
Layered (embedded) code-excited linear prediction (CELP) speech encoders/decoders with adaptive plus algebraic codebooks applied in each layer with fixed...
Method and apparatus for cassette integrity testing using a wafer sorter
A system and methods for the evaluation of the integrity of a wafer cassette and the disposition thereof are based upon evaluation of wafer measurement data...
Circuit to reduce internal ESD stress on device having multiple power
An ESD protection circuit is designed on an integrated circuit (100) having a first power supply bus (106) and a second power supply bus (108). The circuit...
Bracket for piezoelectric drive torsional hinge mirror
A combination pivoting mirror and support bracket has a bracket for supporting a pivoting mirror assembly and for attaching the combination to a using device....
Electro-optical, tunable, broadband color modulator
A display system for creating a full-color projected image. Light from a white light source passes through a color modulator (106). The color modulator (106) is...
Correcting offset errors associated with a sub-ADC in pipeline analog to
An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could...
Comparator and method with controllable threshold and hysteresis
A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first...
Electronic device and method for on chip skew measurement
The invention relates to an integrated electronic device for digital signal processing, which includes a phase locked loop for generating an output clock signal...
Low-delay complimentary metal-oxide semiconductor (CMOS) to
emitter-coupled logic (ECL) converters, methods and...
Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed...
Method to accurately estimate the source and drain resistance of a MOSFET
Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series...
Power-over-ethernet isolation loss detector
An AC generator has a first terminal coupled through an Isolation Loss Detect (ILD) capacitor to the positive bus of a Power-Over-Ethernet (POE) system, and has...
Slope compensation for switching regulator
In one embodiment, a switching regulator comprises a control circuit that activates and deactivates at least one power switch to control a voltage of a switching...
Feed-forward circuit for adjustable output voltage controller circuits
A feedback loop in a variable power supply has an adjustable response speed based on operating conditions of the power supply. The response speed can be...
Control circuit for a polarity inverting buck-boost DC-DC converter
A control circuit for a polarity inverting buck-boost DC-DC converter, includes an operational trans-conductance amplifier that has inputs to which a sensed...
Systems and methods for providing over-current protection in a switching
A system and method is provided for providing integrated over-current protection in a switching power supply. In one embodiment, a switching power supply could...
Integrated circuit capacitor having antireflective dielectric
A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom...
Semiconductor device having a gate electrode material feature located
adjacent a gate width side of its gate...
The present invention provides a semiconductor device, a method of manufacture therefore and an integrated circuit including the same. The semiconductor device...
Viterbi pretraceback for partial cascade processing
This invention modifies Viterbi decoding to improve BER. Within the state metric unit cascade block, this invention forces the unused ACS units decision bits to...
Emulation export sequence with distributed control
Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into...
Video encoding using parallel processors
A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus...
Common mode feedback for large output swing and low differential error
A differential amplifier includes a differential input pair (2A) coupled to a folded cascode stage (2B) and a common mode feedback circuit (34) including a...
Minimizing the number of external terminals required when compensation is
to be provided for signal drop in...
Compensation is provided for signal drop in bond wires of an integrated circuit (IC) while minimizing the number of external terminals in the IC package. A...
Apparatus to compare an input voltage with a threshold voltage
Apparatus to compare an input signal to a threshold level are disclosed. An example circuit described herein includes a Widlar bandgap circuit to receive the...
Integrated low power received signal strength indicator (RSSI) with linear
An RSS indicator with a linear characteristic that is of a simple configuration, low current consumption and small die area requirements, comprises a pair of...
Versatile system for charge dissipation in the formation of semiconductor
The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200),...
Recovery from corruption using event offset format in data trace
A method of tracing data processor activity with recover from detection of trace stream corruption. If the first trace data following detection of corruption is...
Using a chip as a simulation engine
The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock...
Tap and linking module for scan access of multiple cores with IEEE 1149.1
test access ports
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
Method of translating system events into signals for activity monitoring
Disclosed herein is a system and method for receiving encoded events from a system that is being debugged or profiled. The encoded events are input to a decoder...
Recording control point in trace receivers
A trace receiver with multiple recording interfaces may be used to record the same input. The historical control point for starting and stopping trace recording...
Method and system of profiling real-time streaming channels
A method and system of profiling streaming channels. At least some of the illustrative embodiments are methods comprising executing a traced program on a target...