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Processor with summation instruction using overflow counter
Performing a sum of numbers operation in a variable bit-length environment of a processor in response to a summation instruction, comprising a) adding a least...
Memory optimization packet loss concealment in a voice over packet network
A method to reduce memory requirements for a packet loss concealment algorithm in the event of packet loss in a receiver of pulse code modulated voice signals. A...
One time operating state detecting method and apparatus
A method and apparatus for detecting a change in an electrical property between contacts. A one-time operating state detection device includes a member coupling...
Poly-phase electric energy meter
A poly-phase electric energy meter comprises a front-end that converts analog current input signals and analog voltage input signals to digital current and...
Power LDMOS transistor
A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the...
Surveillance implementation in managed VOP networks
A procedure for accomplishing surveillance within a managed VoP network when end-user encryption/decryption and NAT are in place. The procedure comprises first...
Integrated circuit having electrically isolatable test circuitry
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test....
Scan testing using response pattern as stimulus pattern after reset
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one...
System and method for performing concurrent mixed signal testing on a
The present application describes a system and method for testing semiconductor devices and specifically for testing mixed signal semiconductor devices. The test...
Method and system for processing a "WIDE" opcode when it is not used as a
prefix for an immediately following...
Methods and systems are provided for the selective use of a Java WIDE opcode as a prefix as defined in the instruction set of the Java virtual machine or...
Pipelined access by FFT and filter units in co-processor and system bus
slave to memory blocks via switch...
A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry...
Methods of inter-integrated circuit addressing and devices for performing
Inter-integrated circuit-capable devices for use on an inter-integrated circuit bus are disclosed. The inter-integrated circuit-capable devices include...
Full/selector output from one of plural flag generation count outputs
A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a "high water mark" to different levels for different...
Power control with standby, wait, idle, and wakeup signals
An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a...
Concealment of frame erasures and method
A decoder for code excited LP encoded frames with both adaptive and fixed codebooks; erased frame concealment uses repetitive excitation plus a smoothing of...
Systems and methods for low power clock generation
Various systems and methods for low power identification are described herein. For example, a radio frequency device including a radio frequency energy receiver....
Interleaver memory selectably receiving PN or counter chain read address
A method and apparatus for interleaving multiple frames of data as disclosed provide for an extremely streamlined approach to achieving both methods of...
Methods for depositing, releasing and packaging micro-electromechanical
devices on wafer substrates
A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from...
Audio MEMS mirror feedback
A mirror device and a method for audio feedback of a MEMS mirror device are presented. The mirror device includes a mirror with a reflective surface located to...
Pre-power amplifier of load, switch array, and impedance compensation
A novel and useful load compensation circuit and associated pre-power amplifier constructed therefrom. The load compensation circuit functions to maintain a...
Simultaneous filtering and compensation circuitry and method in chopping
A chopper-stabilized amplifier (1B) having a first output (25) includes an input chopper (9) for chopping an input signal and applying it to the input of a first...
Systems for providing a constant resistance
A system for providing a desired substantially constant resistance includes a first transistor interconnected between a first node and a second node. The system...
CMOS integrated circuit for correction of duty cycle of clock signal
A CMOS integrated circuit (12) for correction of the duty cycle of a clock signal has a correction amplifier (16) to which a clock signal (14) is applied. The...
Method of forming a fully silicided semiconductor device with independent
gate and source/drain doping and...
A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative...
System and method for noisy automatic speech recognition employing joint
compensation of additive and...
A system for, and method of, noisy automatic speech recognition employing joint compensation of additive and convolutive distortions and a digital signal...
Method and apparatus for transmit power control in wireless data
The distance between a first Multi Band Orthogonal Frequency Division Multiplex (MB-OFDM) data transceiver and a second or more such transceiver is determined...
Versatile system for interference tolerant packet detection in wireless
The present invention provides a system for obviating interference effects in packet detection within a wireless communications network. A plurality of reference...
Adaptive transmit window control mechanism for packet transport in a
universal port or multi-channel environment
The transmit window size of a Simple Packet Relay Transport protocol packet transmission system can determine the efficiency of transmission and the memory...
Oscillator with multi-tap inductor, capacitors, and negative-Gm stages
System and method for increasing the frequency tuning range of a RF/microwave LC oscillator. An electronic communications device includes a controller to...
The present invention relates to a CMOS buffer circuit for liquid crystal display (LCD) drivers, which includes a single stage operational transconductance...
Self-oscillating regulated low-ripple charge pump and method
Charge pump circuitry (30) compares bottom plate voltages of first (C1) and second (C2) flying capacitors in a current mode charge pump (1B) to a reference value...
Vertically integrated system-in-a-package
According to one embodiment of the invention, a method of forming a system-in-a-package includes providing a first substrate, coupling a first die to a top...
Dual metal gates for mugfet device
Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the...
Simplified decoding using structured and punctured LDPC codes
A communications transceiver for transmitting and receiving coded communications, with the coding corresponding to a low-density parity check code, is disclosed....
Distinguishing between two classes of trace information
A method of tracing activity of a data processor generates a trace data stream during a normal background mode and a foreground mode while servicing a real time...
Software source transfer selects instruction word sizes
This invention employs a 16-bit instruction set that has a subset of the functionality of the 32-bit instruction set. In this invention 16-bit instructions and...
A single bus apparatus enables the simultaneous execution of both high-speed data transfer, which requires real time operation, and low-speed data transfer. At...
Processor with scaled sum-of-product instructions
A method of performing a scaled sum-of-product operation in a processor in response to multiply-and-accumulate (MAC) instructions. The method includes accessing...
Processor with maximum and minimum instructions
A method of operating a processor in a variable bit-length environment by performing a maximum limit function and minimum limit function. The method comprises...
Discrete-time convolution cycle reduction with programmable digital signal
A programming algorithm reduces from .theta. (2N.sup.2) to .theta. (N.sup.2) the number of multiply-and-accumulate (MAC) instructions required to perform a...
Test protocol manager for massive multi-site test
Disclosed herein is a massive multi-site (MMS) testing architecture. The MMS architecture includes a MMS interface on each of a plurality of devices under test....
Method of adjusting process variables in a processing flow
A method of adjusting process variables in a processing flow is disclosed. Processed samples are tested to determine sample parameters of the tested samples. The...
Fixed-size cross-correlation computation method for audio time scale
A time-domain time-scale modification method based on the synchronous overlap-and-add method consists of a generalization of the envelope-matching time-scale...
Clock recovery apparatus having an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein the early/late voter...
DAC architecture for an ADC pipeline
A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one...
Semiconductor device and inspection method thereof
A semiconductor device is disclosed. The device has a photodiode isolated by element isolating regions (Ia, 14a, 14b) characterized by the following facts: on...
Automatic page sequencing and other feedback action based on analysis of
audio performance data
Speech or musical performance is electronically analyzed using DSP techniques and is compared to a stored text script or musical score, to enable display of and...
Bond capillary design for ribbon wire bonding
A device (100) and method (200) for bonding a ribbon wire (104) to a workpiece (106) comprising feeding the ribbon wire through a passageway (116) of an...
Updating embedded firmware in a video system
An electronic device (18). The device comprises an analog (16) interface for receiving an analog waveform. The device also comprises an image screen (20) and...
Independent source read and destination write enhanced DMA
The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and...