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Patent # Description
US-7,611,981 Optimized circuit design layout for high performance ball grid array packages
A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a...
US-7,611,943 Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation
A process (200) for making integrated circuits with a gate, uses a doped precursor (124, 126N and/or 126P) on barrier material (118) on gate dielectric (116)....
US-7,611,939 Semiconductor device manufactured using a laminated stress layer
There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a...
US-7,611,247 Illumination aperture for projection display
An optical system and method of increasing the contrast of a projected image. The optical system (1800) comprises a combination of aperture stops (1810, 1812) in...
US-7,610,536 Select and enable leads connecting IC taps and embedded controller
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-7,610,518 Program counter range comparator with equality, greater than, less than and non-equal detection modes
An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators...
US-7,609,612 Multi-carrier transmitter for ultra-wideband (UWB) systems
System and method for a multi-carrier ultra-wideband (UWB) transmitter. A preferred embodiment comprises an UWB transmitter (for example, transmitter 300) taking...
US-7,609,277 Method and apparatus for spatial and temporal dithering
An apparatus and method for spatially and temporally dithering pixels. A pixel comprising at least one color component of a first size is provided. A dither...
US-7,608,916 Aluminum leadframes for semiconductor QFN/SON devices
A post-mold plated semiconductor device has an aluminum leadframe (105) with a structure including a chip mount pad and a plurality of lead segments without...
US-7,608,484 Non-pull back pad package with an additional solder standoff
Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback...
US-7,607,058 Removable and replaceable tap domain selection circuitry
Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is...
US-7,607,047 Method and system of identifying overlays
A method and system of identifying overlays. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system...
US-7,606,999 Merging branch information with sync points
A method for merging branch information with sync points is disclosed herein. The method comprises determining whether a sync point is to be generated concurrent...
US-7,606,991 Dynamic clock switch mechanism for memories to improve performance
This invention improves cache operation by dynamically extending one state of a clock signal supplied to a cache on operation cycles when a cache fill operation...
US-7,606,977 Context save and restore with a stack-based memory structure
A multi-threaded processor adapted to couple to external memory comprises a controller and data storage operated by the controller. The data storage comprises a...
US-7,606,703 Layered celp system and method with varying perceptual filter or short-term postfilter strengths
Layered code-excited linear prediction (CELP) speech encoders have progressively weaker perceptual weighting filters for each of the successive enhancement...
US-7,606,696 Programmable extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least...
US-7,606,164 Process of increasing source rate on acceptable side of threshold
A process (111,101) of sending packets of real-time information at a sender (311) includes initially generating packets of real-time information with a source...
US-7,605,845 Motion stabilization
Stabilization for devices such as hand-held camcorders segments a low-resolution frame into a region of reliable estimation, refines the motion vectors of that...
US-7,605,737 Data encoding in a clocked data interface
One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over...
US-7,605,732 Systems and methods for kickback reduction in an ADC
Various systems and methods for analog to digital conversion are disclosed. For example, some embodiments of the present invention provide analog to digital...
US-7,605,664 All digital phase locked loop system and method
An all digital PLL system generates an analog oscillator signal at intermediate frequencies to achieve averaged oscillator frequencies at an extremely high...
US-7,605,646 Low glitch offset correction circuit for auto-zero sensor amplifiers and method
An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero...
US-7,605,576 Switching power supply device
This invention prevents undershoot, etc., occurring in the output during the transition from intermittent control mode to continuous control mode to hinder...
US-7,605,412 Distributed high voltage JFET
A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially...
US-7,603,589 Method and system for debugging a software program
A profiling system. At least some of the illustrative embodiments are integrated circuit devices comprising a processing circuit configured to execute a target...
US-7,603,521 Prioritizing caches having a common cache level
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
US-7,603,487 Hardware configurable hub interface unit
A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application...
US-7,602,905 Processes, circuits, devices, and systems for encryption and decryption and other purposes, and processes of making
A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a...
US-7,602,167 Reconfigurable topology for switching and linear voltage regulators
A configurable voltage regulator (28; 128) operable in either of two selectable modes or topologies is disclosed. In one disclosed embodiment, the voltage...
US-7,602,019 Drive circuit and drain extended transistor for use therein
A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also...
US-7,601,639 Method for conditioning a microelectronics device deposition chamber
The present invention provides, in one aspect, the present invention provides, in one embodiment, a method of conditioning a deposition chamber 100. This method...
US-7,601,629 Semiconductive device fabricated using subliming materials to form interlevel dielectrics
The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over...
US-7,601,624 Device comprising an ohmic via contact, and method of fabricating thereof
Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a...
US-7,601,578 Defect control in gate dielectrics
A method for improving high-.kappa. gate dielectric film (104) properties. The high-.kappa. film (104) is subjected to a two step anneal sequence. The first...
US-7,601,577 Work function control of metals
Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a `mid gap` metal, is manipulated in...
US-7,601,575 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility...
US-7,601,559 Apparatus and method for identifying proper orientation and electrical conductivity between a semiconductor...
A semiconductor device with a semiconductor die thereon and a contactor board are electrically coupled when the electrically conductive elements on the...
US-7,601,549 Method of processing semiconductor wafers
A method of processing semiconductor wafers comprises forming a pattern of recesses in an exposed surface of each wafer in a lot, prior to an epitaxy step. At...
US-7,601,486 Ultra dark polymer
A method and a material for creating an antireflective coating on an integrated circuit. A preferred embodiment comprises applying a dark polymer material on a...
US-7,600,179 Sparse maximum likelihood decoder for block codes
A method is provided to decode data encoded by any block code in a manner that substantially improves the error correction capability of the block codes, and...
US-7,599,011 Method for synchronizing an image data source and a resonant mirror system to generate images
System and method for synchronizing the low speed mirror movement of a mirror display system with incoming frame or video signals, and synchronizing buffered...
US-7,598,822 Process, supply, and temperature insensitive integrated time reference circuit
Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations...
US-7,598,772 Signal driver having selectable aggregate slew rate to compensate for varying process, voltage or temperature...
A signal driver having a selectable aggregate slew rate, a method of driving a signal driver and a signal driver incorporating the driver or the method. The...
US-7,598,759 Routing engine, method of routing a test probe and testing system employing the same
Embodiments of the present disclosure provide a routing engine, a method of routing a test probe and a testing system employing the router or the method. In one...
US-7,598,547 Low noise vertical variable gate control voltage JFET device in a BiCMOS process and methods to build this device
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It...
US-7,598,507 Adjustable lithography blocking device and method
The present invention provides, in one embodiment, a method (100) of manufacturing a semiconductor device. A conventionally formed reticle is positioned over a...
US-7,598,124 System and method to increase die stand-off height
In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of...
US-7,598,119 System and method for inhibiting and containing resin bleed-out from adhesive materials used in assembly of...
System and method for preventing resin-based adhesive from contacting a substrate to minimize resin bleed-out and contamination. A preferred embodiment comprises...
US-7,596,773 Automating optimal placement of macro-blocks in the design of an integrated circuit
Automating optimal placement of macro-blocks in the design of an integrated circuit. A first set of placements is generated and corresponding measures of...
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