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Patent # Description
US-7,629,190 Method for making a micromechanical device by using a sacrificial substrate
A method is disclosed for forming a micromechanical device. The method includes fully or partially forming one or more micromechanical structures multiple times...
US-7,628,021 Solid state heat pump
In accordance with the invention, there are methods for transferring heat, for heating and cooling, and there is a solid state heat pump. The solid state heat...
US-7,627,700 Expanded memory for communications controller
One embodiment of the present invention includes a communication system. The system comprises a communications controller configured to control transmission and...
US-7,627,053 Apparatus and method for driving a pulse width modulation reference signal
An apparatus for driving a pulse width modulation reference signal includes: (a) A converting unit receiving an input signal at an input locus and presenting an...
US-7,626,852 Adaptive voltage control for SRAM
The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM...
US-7,626,850 Systems and devices for implementing sub-threshold memory devices
Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory...
US-7,626,793 Transistor overcurrent detection circuit with improved response time
A circuit and method for determining overcurrent in a FET detects an output voltage of the FET in both a positive and negative polarity. The related positive or...
US-7,626,525 Feed-forward circuitry and corresponding error cancellation circuit for cascaded delta-sigma modulator
A cascaded delta-sigma modulator includes a first stage delta-sigma modulator (10A) having first adder (2) followed by first (3) and second (6) integrators, a...
US-7,626,519 Pulse-width modulation of pulse-code modulated signals at selectable or dynamically varying sample rates
Digital audio circuitry including modulation circuitry (35; 135) for generating a pulse-width modulated (PWM) signal from processed pulse-code modulated (PCM)...
US-7,626,458 Common-mode bandwidth reduction circuit and method for differential applications
An amplifier driver circuit (10) includes first (11-1) and second (11-2) feedback amplifiers including first (14-1) and second (14-2) upper current mirrors,...
US-7,626,437 Circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal
A circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal comprises a NMOS differential amplifier (20)...
US-7,626,274 Semiconductor device with an improved solder joint
A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and...
US-7,625,807 Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication
The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape...
US-7,624,382 Method and system of control flow graph construction
A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch...
US-7,624,322 Scan based testing of an integrated circuit containing circuit portions operable in different clock domains...
An integrated circuit containing an encoder which avoids setup/hold violation in a memory element of one clock domain, when receiving data from another memory...
US-7,624,321 IEEE 1149.1 and P1500 test interfaces combined circuits and processes
In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally...
US-7,623,838 Sampling mixer with asynchronous clock and signal domains
A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having...
US-7,623,286 System and method for displaying images
System and method for enhancing image quality in a display system. A preferred embodiment comprises a variable light source capable of producing a light of...
US-7,623,055 Weight level generating method and device utilizing plural weights at different time rates
A weight level generator is provided. Weight level generator W has plural weight generators 5-1-5-j. At least one of said plural weight generators is used at at...
US-7,622,955 Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention...
An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An...
US-7,622,244 Method for contaminant removal
Method for removing contaminants from a surface during semiconductor fabrication. A preferred embodiment comprises developing a resist layer on a top surface of...
US-7,620,867 IP core design supporting user-added scan register option
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test...
US-7,620,675 Image and audio transform methods
Inverse discrete cosine transform (type-III DCT), used in video/image and audio coding, is implemented in the form of FFT to lower computational complexity.
US-7,619,947 Integrated circuit having a supply voltage controller capable of floating a variable supply voltage
An integrated circuit includes a supply voltage controller operable to receive a plurality of control signals and at least one circuit supply voltage and to...
US-7,619,397 Soft-start circuit for power regulators
One embodiment of the present invention includes a system for providing a soft-start for a power regulator comprising a differential transistor pair that...
US-7,619,241 Variable capacitor single-electron transistor including a P-N junction gate electrode
The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a...
US-7,619,198 Imaging device and imaging device drive method
The problem of the invention is to improve S/N and provide a high-sensitivity imaging device. The CMOS image sensor includes multiple pixels arranged in a...
US-7,618,870 Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof
The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure...
US-7,617,440 Viterbi traceback initial state index initialization for partial cascade processing
This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations...
US-7,617,430 Local and global address compare with tap interface TDI/TDO lead
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,617,429 Automatable scan partitioning for low power using external control
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
US-7,615,966 Method and apparatus for managing energy in plural energy storage units
A system for managing energy stored in a plurality of series connected energy storage units has a plurality of energy storage unit controllers, each controller...
US-7,615,805 Versatile system for optimizing current gain in bipolar transistor structures
Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and...
US-7,615,458 Activation of CMOS source/drain extensions by ultra-high temperature anneals
A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over...
US-7,615,425 Open source/drain junction field effect transistor
The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET)...
US-7,615,386 Thick oxide film for wafer backside prior to metalization loop
A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick...
US-7,613,970 TAP domain selection circuit with AUXI/O1 or TDI lead
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,613,951 Scaled time trace
The trace logic are separate from the clocks that operate the system logic. This allows the chip to be placed in a special mode where the functional logic is...
US-7,613,924 Encrypted and other keys in public and private battery memories
Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In...
US-7,613,905 Partial register forwarding for CPUs with unequal delay functional units
A data processing apparatus includes a register file and a plurality of functional units. At least one and not all the plurality of the functional units is a...
US-7,613,259 Mobile receiver phase correction circuit
A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (r.sub.j(i+.tau..sub.j), i=0-N-1) during a first...
US-7,612,612 Calibration circuitry and delay cells in rectilinear RF power amplifier
Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high...
US-7,612,584 Simultaneous LVDS I/O signaling method and apparatus
First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an...
US-7,612,454 Semiconductor device with improved contact fuse
One aspect of the invention provides an integrated circuit(IC) [400b]. The IC comprises transistors [410b] and contact fuses [422b]. The contact fuses each...
US-7,612,440 Package for an integrated circuit
According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of...
US-7,612,437 Thermally enhanced single inline package (SIP)
In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A...
US-7,612,422 Structure for dual work function metal gate electrodes by control of interface dipoles
Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or...
US-7,611,981 Optimized circuit design layout for high performance ball grid array packages
A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a...
US-7,611,943 Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation
A process (200) for making integrated circuits with a gate, uses a doped precursor (124, 126N and/or 126P) on barrier material (118) on gate dielectric (116)....
US-7,611,939 Semiconductor device manufactured using a laminated stress layer
There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a...
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