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| Patent # | Description |
|---|---|
| US-7,957,178 |
Storage cell having buffer circuit for driving the bitline An integrated circuit includes a memory array including a plurality of memory cells, the memory cells include a core storage element having at least a first... |
| US-7,956,941 |
Method and apparatus for reducing speckle in coherent light According to one embodiment, a method for reducing speckle in an image produced from a coherent light source includes directing a beam of coherent light at an... |
| US-7,956,878 |
Pulse width modulation algorithm In display systems employing spatial light modulators, the OFF-state light from OFF-state pixels of the spatial light modulator can be captured and directed... |
| US-7,956,456 |
Thermal interface material design for enhanced thermal performance and
improved package structural integrity An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device... |
| US-7,956,445 |
Packaged integrated circuit having gold removed from a lead frame A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top... |
| US-7,956,357 |
Test pads coupled with leads unconnected with die pads Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding... |
| US-7,955,956 |
Method for recycling/reclaiming a monitor wafer The invention provides a method for recycling/reclaiming a monitor or test wafer and a method for testing an integrated circuit manufacturing process. After a... |
| US-7,955,041 |
Quick changeover apparatus and methods for wafer handling Quick changeover apparatus for wafer handlers capable of handling at least two sizes of wafer frames and methods of using such apparatus are disclosed. |
| US-7,954,030 |
Automatable scan partitioning for low power using external control Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan... |
| US-7,954,027 |
Reduced signaling interface method and apparatus This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial... |
| US-7,954,026 |
TAM controller connected with TAM and functional core wrapper circuit A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard... |
| US-7,954,024 |
Selecting scan test/TAP with FF receiving lock in and update-IR A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an... |
| US-7,952,378 |
Tunable stress technique for reliability degradation measurement Apparatus and methods are disclosed for examining how reliability in an RF power amplifier circuit changes as a function of variation of the input to output... |
| US-7,952,178 |
Package for an integrated circuit According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of... |
| US-7,952,145 |
MOS transistor device in common source configuration A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the... |
| US-7,949,920 |
DFT techniques to reduce test time and power for SoCs A technique for reducing the overhead of daisy chain test mode in divide-and-conquer testing using intermediate test modes that do not span all cores or all... |
| US-7,949,917 |
Maintaining data coherency in multi-clock systems A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a... |
| US-7,949,323 |
Local oscillator leakage counterbalancing in a receiver The present invention provides a local oscillator (LO) leakage controller for use with a receiver. In one embodiment, the LO leakage controller includes a... |
| US-7,949,064 |
Codebook and pre-coder selection for closed-loop mimo A method of transmitting a communication signal (FIG. 1) is disclosed. The method includes receiving a data signal (102). The method further includes receiving... |
| US-7,948,866 |
Low complexity design of primary synchronization sequence for OFDMA The present disclosure provides a base station transmitter, a user equipment receiver and methods of operating a base station transmitter and a user equipment... |
| US-7,948,499 |
Color control algorithm for use in display systems A color control algorithm compensates variations in the display system so as to maintain color consistency in the projected images on the screen by constructing... |
| US-7,948,410 |
Multibit recyclic pipelined ADC architecture An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit... |
| US-7,948,319 |
Current-mirroring systems and methods One embodiment of the invention includes a current-mirror system. The system includes a current-mirror circuit configured to conduct an input current through a... |
| US-7,948,316 |
Low bias current amplifier An amplifier is provided that includes an output portion that sources and sinks current associated with an output load and an amplification portion that is... |
| US-7,948,199 |
Single-ended gain stage and disk drive An electrical apparatus comprising an amplifier having a first input, a second input, and an output. The apparatus further comprises a first electrical path... |
| US-7,947,602 |
Conductive pattern formation method The objective of the present invention is to offer a method for forming a conductive pattern on a substrate and solder protrusions on the conductive pattern.... |
| US-7,945,875 |
Methodology for hierarchy separation at asynchronous clock domain
boundaries for multi-voltage optimization... This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and... |
| US-7,945,838 |
Parity check decoder architecture A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder... |
| US-7,945,832 |
Interface to full and reduced pin JTAG devices The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced... |
| US-7,945,831 |
Gating TDO from plural JTAG circuits Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan... |
| US-7,945,008 |
Systems and methods for lattice enumeration-aided detection Embodiments provide systems and methods for improved multiple-input, multiple-output (MIMO) detection comprising generating at least one list of candidate... |
| US-7,944,904 |
Systems and methods for managing timing functions in multiple timing
protocols One embodiment of the present invention includes a system for managing timing functions associating with at least one timing protocol. The system comprises a... |
| US-7,944,819 |
System and method for transmission and acknowledgment of blocks of data
frames in distributed wireless networks The present application describes a system and method for transmitting and acknowledging a block of frames in a wireless network. According to an embodiment, a... |
| US-7,944,503 |
Interlaced-to-progressive video processing An edge direction vector determination, which can be used for video interlaced-to-progressive conversion by motion-adaptive interpolation, has a coarse edge... |
| US-7,944,379 |
SAR ADC and method with INL compensation An apparatus for analog-to-digital conversion using successive approximation is provided. There is a successive approximation register or SAR controller for... |
| US-7,944,348 |
Tire monitoring device and tire problem detecting device A device to accurately identify the wheel position where each tire has a radio wave transmitter installed without special means or operation during application... |
| US-7,944,319 |
Clock spreading systems and methods Clock spreading systems and methods are disclosed. In one embodiment of the invention, a clock spreading system is provided in an integrated transceiver system... |
| US-7,944,287 |
Low-noise, wide offset range, programmable input offset amplifier front
end and method A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first... |
| US-7,944,252 |
High performance LVDS driver for scalable supply Traditionally, complementary metal oxide semiconductor (CMOS) and bipolar transistors have been separately employed in low voltage differential signal (LVDS)... |
| US-7,944,034 |
Array molded package-on-package having redistribution lines A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to... |
| US-7,943,514 |
Integrated circuits having TSVs including metal gettering dielectric
liners An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit... |
| US-7,943,499 |
FUSI integration method using SOG as a sacrificial planarization layer A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from... |
| US-7,943,489 |
Bonded wafer assembly system and method A system and method for the removal of superfluous material in a bonded wafer assembly. The method includes cutting a plurality of parallel cuts in a top wafer,... |
| US-7,943,479 |
Integration of high-k metal gate stack into direct silicon bonding (DSB)
hybrid orientation technology (HOT)... A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a... |
| US-7,943,472 |
CoSi2 Schottky diode integration in BiSMOS process Cobalt silicide (CoSi2) Schottky diodes fabricated per the current art suffer from excess leakage currents in reverse bias. In this invention, an floating... |
| US-7,943,456 |
Selective wet etch process for CMOS ICs having embedded strain inducing
regions and integrated circuits therefrom A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes providing a substrate having a semiconductor surface including PMOS regions... |
| US-7,943,451 |
Integration scheme for reducing border region morphology in hybrid
orientation technology (HOT) using direct... Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary... |
| US-7,943,450 |
Gated resonant tunneling diode A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably... |
| US-7,943,425 |
Semiconductor wafer sawing system and method Semiconductor wafer sawing systems and methods are described in which a wafer may be secured in a sawing position having a surface exposed to incur sawing with... |
| US-7,941,790 |
Data processing apparatus, system and method A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a... |
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