Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching: texas instruments
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,884,009 |
Semiconductor device with an improved solder joint A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and... |
| US-7,883,977 |
Advanced CMOS using super steep retrograde wells The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer... |
| US-7,883,973 |
Method of forming semiconductor wells A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a... |
| US-7,883,955 |
Gate dielectric/isolation structure formation in high/low voltage regions
of semiconductor device A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed... |
| US-7,883,936 |
Multi layer low cost cavity substrate fabrication for PoP packages In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to... |
| US-7,883,909 |
Method to measure ion beam angle A device and method for measuring ion beam angle with respect to a substrate is disclosed. The method includes forming a plurality of shadowing structures... |
| US-7,883,822 |
Graded lithographic mask In one aspect there is provided a gray scale lithographic mask that comprises a transparent substrate and a metallic layer located over the substrate, wherein... |
| US-7,883,573 |
Method for preparing a source material for ion implantation The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method... |
| US-7,883,219 |
System and method for displaying images System and method for thin projection display systems. An embodiment comprises a light source, an array of light modulators optically coupled to the light... |
| US-7,882,625 |
Transfer mask in micro ball mounter The objective of this invention is to provide a transfer mask that is able to accurately pass micro-balls onto terminal areas on a substrate. A thin plate... |
| US-7,879,642 |
Solid-state sensor and manufacturing method thereof A sensor having photodiodes whose sensitivity and storage capacity can be increased is provided. The sensor is formed by arranging the photodiodes in an array... |
| US-7,877,658 |
IEEE 1149.1 and P1500 test interfaces combined circuits and processes In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally... |
| US-7,877,654 |
Selectable JTAG or trace access with data store and output An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and... |
| US-7,877,653 |
Address and TMS gating circuitry for TAP control circuit The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a... |
| US-7,877,651 |
Dual mode test access port method and apparatus Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves... |
| US-7,877,650 |
Core circuit test architecture A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections.... |
| US-7,877,536 |
Scalable distributed routing scheme for PCI express switches A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first... |
| US-7,876,856 |
Quadrature receiver with correction engine, coefficient controller and
adaptation engine Methods and apparatus to compensate for I/Q mismatch in quadrature receivers are disclosed. An example apparatus disclosed herein comprises a correction engine... |
| US-7,876,854 |
High data rate closed loop MIMO scheme combining transmit diversity and
data multiplexing Closed loop multiple-antenna wireless communications system with antenna weights determined by maximizing a composite channel signal-to-interference-plus-noise... |
| US-7,876,726 |
Adaptive allocation of communications link channels to I- or Q-subchannel System and method for adaptively allocating channels to subchannels and maintain balance on the subchannels. A preferred embodiment comprises an assignment unit... |
| US-7,876,696 |
Adaptive upstream bandwidth estimation and shaping One embodiment of the present invention includes a method for adaptively estimating available upstream bandwidth in a network. The method comprises monitoring... |
| US-7,876,340 |
Pulse width modulation algorithm In display systems employing spatial light modulators, the OFF-state light from OFF-state pixels of the spatial light modulator can be captured and directed back... |
| US-7,876,298 |
Control timing for spatial light modulator A spatial light modulator clocking method, called fast-clear, which employs embedded clear hardware in the SLM to enable the fast-clear bit to generate... |
| US-7,876,242 |
Method and apparatus for unit interval calculation of displayport
auxilliary channel without CDR A method for decoding a Manchester-II encoded DISPLAYPORT compatible signal is provided. In this method, several counters are reset. A unit interval (UI) counter... |
| US-7,876,112 |
Parallel scan distributors and collectors and process of testing
integrated circuits An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)... |
| US-7,873,889 |
JTAG bus communication method and apparatus The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication... |
| US-7,873,886 |
PC-connectivity for on-chip memory An interface for converting a traditional scan-chain interface into one where locations in the scan-chain can be read or written to from an addressed interface... |
| US-7,872,841 |
In package ESD protections of IC using a thin film polymer A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear... |
| US-7,872,486 |
Wing-shaped support members for enhancing semiconductor probes and methods
to form the same Example wing-shaped support members for enhancing semiconductor device probes and methods to form the same are disclosed. A disclosed example semiconductor... |
| US-7,872,456 |
Discontinuous conduction mode pulse-width modulation One embodiment of the invention includes a power regulator system. The system includes a switching system configured to generate an output voltage across a load... |
| US-7,872,338 |
Microelectromechanical device packages with integral heaters A microelectromechanical device package with integral a heater and a method for packaging the microelectromechanical device are disclosed in this invention. The... |
| US-7,872,336 |
Low cost lead-free preplated leadframe having improved adhesion and
solderability A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack... |
| US-7,871,931 |
Method for chemical mechanical planarization of a metal layer located over
a photoresist layer and a method for... The present invention provides a method for planarizing a metal layer, and a method for manufacturing a micro pixel array. The method for planarizing the metal... |
| US-7,871,864 |
Locking feature and method for manufacturing transfer molded IC packages The invention discloses integrated circuits (ICs), molded IC packages, and to leadframe arrays, package arrays and methods for their manufacture. Leadframe... |
| US-7,870,451 |
Automatable scan partitioning for low power using external control Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan... |
| US-7,870,450 |
High speed double data rate JTAG interface A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface... |
| US-7,869,231 |
System and method for synchronous rectifier drive that enables converters
to operate in transition and... A synchronous rectifier is switched in accordance with a primary switch transition and a reference signal representing current in a current storage device to... |
| US-7,869,145 |
System and method for illuminating a target According to one embodiment of the present invention, a system for illuminating a target includes a light source configured to emit one or more light beams with... |
| US-7,868,794 |
Methods and apparatus to test and compensate multi-channel
digital-to-analog converters Methods and apparatus to test and compensate multi-channel digital-to-analog converters (DACs) are described. In some examples, a multi-channel digital-to-analog... |
| US-7,868,690 |
Comparator with sensitivity control A comparator has a differential input stage, a current source coupled to the differential input stage for providing a tail current to one side of the... |
| US-7,868,670 |
Phase-locked loop (PLL) circuit and method A phase-locked loop (PLL) circuit includes a reference clock divider with a reference clock input, a phase-frequency detector, a charge pump, a loop filter, a... |
| US-7,868,599 |
Method of optimum current blanking time implementation in current sense
circuit In a method and system for sensing current in a switching regulator (SWR) operating in a current mode, a power switch is coupled to receive the current from a... |
| US-7,866,852 |
Heat sinks for cooling LEDs in projectors According to certain embodiments, an apparatus for cooling light emitting diodes (LEDs) in projectors includes one or more first LEDs, one or more first heat... |
| US-7,866,036 |
Method of fabricating micromirror device A micromirror device and a method of making the same are disclosed herein. The micromirror device comprises a mirror plate, hinge, and post each having an... |
| US-7,865,849 |
System and method for estimating test escapes in integrated circuits A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for... |
| US-7,865,791 |
Reduced signaling interface method and apparatus This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial... |
| US-7,864,661 |
Time-switched preamble generator, method of generating and multiple-input,
multiple-output communication system... The present invention is directed to a time-switched preamble generator and method of generating a time-switched preamble for use with a multiple-input,... |
| US-7,864,600 |
Memory cell employing reduced voltage A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and... |
| US-7,864,494 |
Methodology to guard ESD protection circuits against precharge effects An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge... |
| US-7,864,191 |
Techniques for efficient dithering A system comprising a storage including an image file associated with a plurality of pixels and processing logic coupled to the storage. The processing logic is... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.