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Searching: texas instruments
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| Patent # | Description |
|---|---|
| US-7,821,333 |
High-voltage differential amplifier and method using low voltage amplifier
and dynamic voltage selection A differential amplifier (1D) includes circuitry (5,R1,R2,52) coupling a common mode component of an input voltage (Vin.sup.+-Vin.sup.-) to a maximum voltage... |
| US-7,821,328 |
Dynamic charge pump system for front end protection circuit Various apparatuses, methods and systems for a front end protection circuit with a dynamic charge pump system are disclosed herein. For example, some embodiments... |
| US-7,821,307 |
Bandgap referenced power on reset (POR) circuit with improved area and
power performance In an apparatus for monitoring a supply voltage, a current mirror coupled to the supply voltage provides a pair of matching currents. A resistor divider that... |
| US-7,821,113 |
Leadframe having delamination resistant die pad A lead frame (410) including a die pad (100) for mounting at least one integrated circuit (405) thereon and a plurality of lead fingers (413). The die pad (100)... |
| US-7,821,111 |
Semiconductor device having grooved leads to confine solder wicking A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes... |
| US-7,820,924 |
Multi-direction switch for a cursor device A directional controller for a device is provided. The directional controller consists of keypad contacts, a keyboard, and a button. The keypad contacts are on a... |
| US-7,820,063 |
Micromirror device and a method of making the same A reflective and deformable micromirror device comprises a reflective micromirror plate attached to a deformable hinge that is formed on and held by a hinge post... |
| US-7,818,711 |
System and method for making photomasks The present application is directed a method for determining the position of photomask patterns in a mask making process. The method comprises providing one or... |
| US-7,818,641 |
Interface to full and reduce pin JTAG devices The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced... |
| US-7,818,604 |
Pipelined clock stretching circuitry and method for I2C logic system A system for increasing the data throughput of an I2C bus including a serial clock conductor (3) for conducting a serial clock signal (SCK) and a serial data... |
| US-7,818,468 |
Method and system for processing control information In one aspect, an integrated circuit device including a first-level module configurable to receive and transmit control information, said first level module... |
| US-7,817,747 |
Precise delay alignment between amplitude and phase/frequency modulation
paths in a digital polar transmitter A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides... |
| US-7,817,736 |
Correcting for carrier frequency offset in multi-carrier communication
systems A multi-carrier (MC) receiver receives a multi-carrier signal containing data symbols as well as pilot symbols. The MC receiver estimates a carrier frequency... |
| US-7,817,490 |
Low-power operation of static memory in a read-only mode A static random access memory (SRAM) operable that is biased at lower power supply voltages in a read-only mode than in a read/write mode. The SRAM can be... |
| US-7,817,393 |
Power distribution switch circuits with fast responses to hard
short-circuits Methods and apparatus to provide power distribution switch circuits with fast responses to hard short-circuits are disclosed. In one example, a power... |
| US-7,817,341 |
Integrated TIR prism and lens element Disclosed is an optical component, which comprises a prism element adjacent to a lens element, where the two elements are separated by a small air gap. In... |
| US-7,817,323 |
Optical structure and an imaging system using the same An optical architecture comprises an optical scanning mechanism for use in imaging systems. With the optical scanning mechanism, illumination light from an... |
| US-7,816,740 |
Memory cell layout structure with outer bitline An integrated circuit (IC) includes a memory cell having source/drain regions for defining source/drains of a first pull-up or pull-down (PU/PD) transistor for a... |
| US-7,815,738 |
Deposition tool cleaning process having a moving plasma zone The present invention provides, in one embodiment, a process for cleaning a deposition chamber (100). The process includes a step (100) of forming a reactive... |
| US-RE41,830 |
Oversampling analog-to-digital converter and method with reduced chopping
residue noise A delta-sigma modulator includes a chopper-stabilized integrator, a quantizer having an input coupled to an output of the integrator, an input signal acquiring... |
| US-7,814,478 |
Methods and apparatus for use in updating application programs in memory
of a network device An illustrative method of the present application is for use in updating an application program in memory of a network device. An application program having a... |
| US-7,814,450 |
Active skew control of a digital phase-lock loop using delay lock-loops Systems and methods for transmitting a signal having a desired phase at the device are disclosed. The systems and methods further include determining a signal... |
| US-7,814,386 |
Built in self test for input/output characterization A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage... |
| US-7,814,258 |
PCI bus burst transfer sizing Various apparatuses, methods and systems for specifying memory transaction sizes on a PCI bus are disclosed herein. For example, some embodiments of the present... |
| US-7,813,601 |
Reconfigurable optical add/drop multiplexer Disclosed is an add-drop multiplexer that receives an optical signal having a plurality of channels. The multiplexer spatially separates the channels, and a... |
| US-7,813,567 |
Method of CABAC significance MAP decoding suitable for use on VLIW data
processors This invention decodes a next significance symbol using a selected context. The invention operates in a loop for each symbol decode for a whole block until the... |
| US-7,813,462 |
Method of defining semiconductor fabrication process utilizing transistor
inverter delay period A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on... |
| US-7,813,198 |
System and method for reading memory One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to... |
| US-7,813,193 |
Ferroelectric memory brake for screening and repairing bits A method (300) of identifying failing bits in a ferroelectric memory device including at least one ferroelectric capacitor includes (302) writing same state data... |
| US-7,813,177 |
Analog single-poly EEPROM incorporating two tunneling regions for
programming the memory device A single-poly EEPROM memory device comprises a control gate isolated within a well of a first conductivity type in a semiconductor body of a second conductivity... |
| US-7,813,068 |
Degauss control for magnetic disk-drive preamplifier One embodiment of the invention includes a preamplifier system for a magnetic disk-drive. The system includes a current distributor configured to generate a... |
| US-7,812,830 |
Touch-initiated power-saving clock system and method for touch screen
controller A touch screen controller circuit (1A) including means for generating a first and second levels of a pen touch signal (PENTOUCH) if a touch point (Q) is present... |
| US-7,812,649 |
Low power, power on reset circuit with accurate supply voltage detection The power on reset circuit includes: a comparator; a resistor string having a first end coupled to a first supply node of the comparator, a first tap point node... |
| US-7,812,646 |
Low-leakage switch for sample and hold An integrated electronic device includes a sample and hold stage. The sample and hold stage has a sampling capacitor (C) for an input voltage at an input node... |
| US-7,812,401 |
MOS device and process having low resistance silicide interface using
additional source/drain implant An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source... |
| US-7,811,942 |
Tri-layer plasma etch resist rework Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch... |
| US-7,811,917 |
Systems and methods for maintaining performance at a reduced power Systems and methods are provided for maintaining performance of an integrated circuit at a reduced power. The systems and methods employ a performance monitor... |
| US-7,811,893 |
Shallow trench isolation stress adjuster for MOS transistor The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an... |
| US-7,811,882 |
Hardmask manufacture in ferroelectric capacitors A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming... |
| US-7,810,001 |
Parallel test system A method and a system for defining groups of tests that may be concurrently performed or overlapped are provided. Channel-independent test groups are determined... |
| US-7,809,987 |
Accepting link ID upon supplied and sampled bits matching An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality... |
| US-7,809,961 |
Standby mode for power management An apparatus and method for controlling standby mode in an electronic device. In standby mode, power and clock signals are reduced or stopped to conserve power.... |
| US-7,809,934 |
Security measures for preventing attacks that use test mechanisms A system comprising processing logic adapted to determine a type of boot performed by the system and a storage coupled to the processing logic. The processing... |
| US-7,809,927 |
Computation parallelization in software reconfigurable all digital phase
lock loop A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit... |
| US-7,809,889 |
High performance multilevel cache hierarchy A digital system is provided with a hierarchical memory system having at least a first and second level cache and a higher level memory. If a requested data item... |
| US-7,809,346 |
Digital audio receiver with reduced AM interference A digital audio system including a digital audio amplifier with reduced AM interference. The digital audio amplifier includes a pulse-width-modulation (PWM)... |
| US-7,809,338 |
Local oscillator with non-harmonic ratio between oscillator and RF
frequencies using wideband modulation... A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF... |
| US-7,809,188 |
Digital camera and method Digital camera contrast enhancement with piecewise-linear transform with lower and upper cutoffs for the transform determined from histogram analysis with a... |
| US-7,809,082 |
GMSK/EDGE modulator with switching transition smoothing To minimize abrupt changes in modulated signal amplitude when switching between modulation types in a multi-modulation system, a "smoothing" circuit is used.... |
| US-7,808,449 |
Method and system for multi-channel viewing applications Methods and apparatus for rendering plural channels on a common display are provided. In a method embodiment, a method for allowing sharing of a display by a... |
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