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Patent # Description
US-7,605,732 Systems and methods for kickback reduction in an ADC
Various systems and methods for analog to digital conversion are disclosed. For example, some embodiments of the present invention provide analog to digital...
US-7,605,664 All digital phase locked loop system and method
An all digital PLL system generates an analog oscillator signal at intermediate frequencies to achieve averaged oscillator frequencies at an extremely high...
US-7,605,646 Low glitch offset correction circuit for auto-zero sensor amplifiers and method
An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero...
US-7,605,576 Switching power supply device
This invention prevents undershoot, etc., occurring in the output during the transition from intermittent control mode to continuous control mode to hinder...
US-7,605,412 Distributed high voltage JFET
A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially...
US-7,603,589 Method and system for debugging a software program
A profiling system. At least some of the illustrative embodiments are integrated circuit devices comprising a processing circuit configured to execute a target...
US-7,603,521 Prioritizing caches having a common cache level
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is...
US-7,603,487 Hardware configurable hub interface unit
A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application...
US-7,602,905 Processes, circuits, devices, and systems for encryption and decryption and other purposes, and processes of making
A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a...
US-7,602,167 Reconfigurable topology for switching and linear voltage regulators
A configurable voltage regulator (28; 128) operable in either of two selectable modes or topologies is disclosed. In one disclosed embodiment, the voltage...
US-7,602,019 Drive circuit and drain extended transistor for use therein
A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also...
US-7,601,639 Method for conditioning a microelectronics device deposition chamber
The present invention provides, in one aspect, the present invention provides, in one embodiment, a method of conditioning a deposition chamber 100. This method...
US-7,601,629 Semiconductive device fabricated using subliming materials to form interlevel dielectrics
The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over...
US-7,601,624 Device comprising an ohmic via contact, and method of fabricating thereof
Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a...
US-7,601,578 Defect control in gate dielectrics
A method for improving high-.kappa. gate dielectric film (104) properties. The high-.kappa. film (104) is subjected to a two step anneal sequence. The first...
US-7,601,577 Work function control of metals
Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a `mid gap` metal, is manipulated in...
US-7,601,575 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility...
US-7,601,559 Apparatus and method for identifying proper orientation and electrical conductivity between a semiconductor...
A semiconductor device with a semiconductor die thereon and a contactor board are electrically coupled when the electrically conductive elements on the...
US-7,601,549 Method of processing semiconductor wafers
A method of processing semiconductor wafers comprises forming a pattern of recesses in an exposed surface of each wafer in a lot, prior to an epitaxy step. At...
US-7,601,486 Ultra dark polymer
A method and a material for creating an antireflective coating on an integrated circuit. A preferred embodiment comprises applying a dark polymer material on a...
US-7,600,179 Sparse maximum likelihood decoder for block codes
A method is provided to decode data encoded by any block code in a manner that substantially improves the error correction capability of the block codes, and...
US-7,599,011 Method for synchronizing an image data source and a resonant mirror system to generate images
System and method for synchronizing the low speed mirror movement of a mirror display system with incoming frame or video signals, and synchronizing buffered...
US-7,598,822 Process, supply, and temperature insensitive integrated time reference circuit
Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations...
US-7,598,772 Signal driver having selectable aggregate slew rate to compensate for varying process, voltage or temperature...
A signal driver having a selectable aggregate slew rate, a method of driving a signal driver and a signal driver incorporating the driver or the method. The...
US-7,598,759 Routing engine, method of routing a test probe and testing system employing the same
Embodiments of the present disclosure provide a routing engine, a method of routing a test probe and a testing system employing the router or the method. In one...
US-7,598,547 Low noise vertical variable gate control voltage JFET device in a BiCMOS process and methods to build this device
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It...
US-7,598,507 Adjustable lithography blocking device and method
The present invention provides, in one embodiment, a method (100) of manufacturing a semiconductor device. A conventionally formed reticle is positioned over a...
US-7,598,124 System and method to increase die stand-off height
In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of...
US-7,598,119 System and method for inhibiting and containing resin bleed-out from adhesive materials used in assembly of...
System and method for preventing resin-based adhesive from contacting a substrate to minimize resin bleed-out and contamination. A preferred embodiment comprises...
US-7,596,773 Automating optimal placement of macro-blocks in the design of an integrated circuit
Automating optimal placement of macro-blocks in the design of an integrated circuit. A first set of placements is generated and corresponding measures of...
US-7,596,771 Distributed element generator, method of generating distributed elements and an electronic design automation...
The present invention provides a distributed element generator for use with an electronic design automation tool. In one embodiment, the distributed element...
US-7,596,732 Digital storage element architecture comprising dual scan clocks and gated scan output
A digital storage element (e.g., a flip-flop or a latch) includes a master transparent latch that receives functional data from a data input port and scan data...
US-7,596,725 Efficient trace triggering
A system comprising a processor core adapted to execute software code and a trace logic coupled to the processor core and comprising a storage. The storage...
US-7,596,491 Layered CELP system and method
Layered (embedded) code-excited linear prediction (CELP) speech encoders/decoders with adaptive plus algebraic codebooks applied in each layer with fixed...
US-7,596,456 Method and apparatus for cassette integrity testing using a wafer sorter
A system and methods for the evaluation of the integrity of a wafer cassette and the disposition thereof are based upon evaluation of wafer measurement data...
US-7,595,968 Circuit to reduce internal ESD stress on device having multiple power supply domains
An ESD protection circuit is designed on an integrated circuit (100) having a first power supply bus (106) and a second power supply bus (108). The circuit...
US-7,595,924 Bracket for piezoelectric drive torsional hinge mirror
A combination pivoting mirror and support bracket has a bracket for supporting a pivoting mirror assembly and for attaching the combination to a using device....
US-7,595,771 Electro-optical, tunable, broadband color modulator
A display system for creating a full-color projected image. Light from a white light source passes through a color modulator (106). The color modulator (106) is...
US-7,595,744 Correcting offset errors associated with a sub-ADC in pipeline analog to digital converters
An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could...
US-7,595,676 Comparator and method with controllable threshold and hysteresis
A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first...
US-7,595,670 Electronic device and method for on chip skew measurement
The invention relates to an integrated electronic device for digital signal processing, which includes a phase locked loop for generating an output clock signal...
US-7,595,660 Low-delay complimentary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and...
Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed...
US-7,595,649 Method to accurately estimate the source and drain resistance of a MOSFET
Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series...
US-7,595,644 Power-over-ethernet isolation loss detector
An AC generator has a first terminal coupled through an Isolation Loss Detect (ILD) capacitor to the positive bus of a Power-Over-Ethernet (POE) system, and has...
US-7,595,624 Slope compensation for switching regulator
In one embodiment, a switching regulator comprises a control circuit that activates and deactivates at least one power switch to control a voltage of a switching...
US-7,595,619 Feed-forward circuit for adjustable output voltage controller circuits
A feedback loop in a variable power supply has an adjustable response speed based on operating conditions of the power supply. The response speed can be...
US-7,595,616 Control circuit for a polarity inverting buck-boost DC-DC converter
A control circuit for a polarity inverting buck-boost DC-DC converter, includes an operational trans-conductance amplifier that has inputs to which a sensed...
US-7,595,615 Systems and methods for providing over-current protection in a switching power supply
A system and method is provided for providing integrated over-current protection in a switching power supply. In one embodiment, a switching power supply could...
US-7,595,525 Integrated circuit capacitor having antireflective dielectric
A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom...
US-7,595,245 Semiconductor device having a gate electrode material feature located adjacent a gate width side of its gate...
The present invention provides a semiconductor device, a method of manufacture therefore and an integrated circuit including the same. The semiconductor device...
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