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| Patent # | Description |
|---|---|
| US-7,790,509 |
Method for fine-pitch, low stress flip-chip interconnect Attaching a semiconductor chip to a substrate by applying mechanical vibrations (150) to a polymeric compound (130) and the contacting areas (114, 124) of a... |
| US-7,790,507 |
Semiconductor die collet and method Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of... |
| US-7,788,800 |
Method for fabricating a leadframe A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (402) and a plurality of... |
| US-7,788,645 |
Method for guaranteeing timing precision for randomly arriving
asynchronous events The timing stream is used to capture pipeline advances and to record stall cycles. Timing streams may be in standard or compressed formats. The stalls are traced... |
| US-7,788,642 |
Displaying cache information using mark-up techniques An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is... |
| US-7,788,559 |
Test access mechanisms, associated controllers and a selector A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE... |
| US-7,788,538 |
Event and stall selection A method comprising generating status signals comprising stall and event information associated with a hardware system. The method also comprises multiplexing... |
| US-7,788,511 |
Method for measuring utilization of a power managed CPU An extremely low overhead method calculates CPU load in the presence of both CPU idling and frequency scaling. The method measures time the CPU is idled while... |
| US-7,788,422 |
Interface and interrupt circuitry coupling data to host DMA circuitry A method includes generating a transfer configuration descriptor ("TCD"), the TCD includes information pertaining to data to be transferred. The method further... |
| US-7,788,091 |
Methods, devices and systems for improved pitch enhancement and
autocorrelation in voice codecs An electronic circuit includes a storage circuit and a microprocessor operable together with the storage circuit as a speech coder. The speech coder has a... |
| US-7,787,630 |
FM stereo decoder incorporating Costas loop pilot to stereo component
phase correction A novel system and method for correcting the residual phase offset between a recovered pilot signal and the received stereo signal. The invention uses a Costas... |
| US-7,787,563 |
Transmitter for wireless applications incorporation spectral emission
shaping sigma delta modulator A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of... |
| US-7,787,560 |
Smart antenna interface using only digital I/O supporting both mode A and
mode B antenna operation as per CEA... This invention samples and transmits the CEA-909 standard smart antenna analog pulse train waveforms using only a digital I/O pin for both mode A and mode B... |
| US-7,787,558 |
Rapid re-synchronization of communication channels A method of synchronizing a receiver with a transmitter. The method includes determining number of bits, j, for adjusting a bit stream, where the bit stream is... |
| US-7,787,550 |
Combined frame alignment and timing recovery in digital subscriber line
(DSL) communications systems Timing recovery circuitry for a digital subscriber line (DSL) modem, including a combined frame and timing function for adjusting frame alignment, and for... |
| US-7,787,541 |
Dynamic pre-filter control with subjective noise detector for video
compression Pre filtering is commonly used in video encoding to remove undesirable noise from video sources. Without a pre filter, the noise degrades the performance of a... |
| US-7,787,499 |
Maintaining synchronization of multiple data channels with a common clock
signal Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g.,... |
| US-7,787,369 |
Flexible Ethernet bridge Congestion is minimized on a desired port in an Ethernet bridge. A packet with a destination address and a source address is received on an incoming port. An... |
| US-7,787,263 |
Methods and apparatus to control a digital power supply Methods and apparatus to control a digital power supply are disclosed. An example method includes controlling a power factor controller by: receiving a first... |
| US-7,787,170 |
Micromirror array assembly with in-array pillars The present invention provides a microstructure device comprising multiple substrates with the components of the device formed on the substrates. In order to... |
| US-7,787,021 |
Programmable architecture for flexible camera image pipe processing This invention is a programmable image pipe processing architecture that offers full software flexibility to implement latest and greatest algorithms at fully... |
| US-7,786,920 |
Method and device for controlling a successive approximation register
analog to digital converter A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator... |
| US-7,786,915 |
Adaptive digital audio pre-distortion in an audio digital to analog
converter An adaptive digital pre-distortion block is used to cancel device nonlinearities to improve the overall linearity of a Delta-Sigma DAC system. In particular, the... |
| US-7,786,913 |
Digital phase locked loop with dithering An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked... |
| US-7,786,909 |
Analog to digital converter with improved input overload recovery With high speed analog to digital converters (ADCs), components within the ADC can enter a saturation region when an input exceeded the input range of the ADC,... |
| US-7,786,758 |
Asynchronous clock gate with glitch protection A tristate buffer circuit includes a tristate buffer switchable into a high impedance state in response to configuration signal, a delay stage delays the an... |
| US-7,786,747 |
Microdisplay assemblies and methods of packaging microdisplays Microdisplay assemblies, methods of packaging microdisplays, and methods of testing microdisplays are disclosed. In accordance with one embodiment, a... |
| US-7,786,662 |
Display using a movable electron field emitter and method of manufacture
thereof A field emission device 100 comprises an anode 105 and a cathode 110 separated by a distance 115 from the anode. At least one of the anode or cathode is... |
| US-7,786,599 |
Semiconductor device with an improved solder joint A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and... |
| US-7,786,518 |
Growth of unfaceted SiGe in MOS transistor fabrication Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable... |
| US-7,786,507 |
Symmetrical bi-directional semiconductor ESD protection device A 2-terminal (i.e., anode, cathode) symmetrical bi-directional semiconductor electrostatic discharge (ESD) protection device is disclosed. The symmetrical... |
| US-7,786,475 |
In-line test circuit and method for determining interconnect electrical
properties and integrated circuit... A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated... |
| US-7,785,974 |
Methods of employing a thin oxide mask for high dose implants A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide... |
| US-7,785,970 |
Method of forming source and drain regions utilizing dual capping layers
and split thermal processes Source and drain regions are formed in a first-type semiconductor device. Then, a high tensile stress capping layer is formed over the source and drain regions.... |
| US-7,785,957 |
Post metal gate VT adjust etch clean A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS... |
| US-7,785,906 |
Method to detect poly residues in LOCOS process A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and... |
| US-7,784,015 |
Method for generating a mask layout and constructing an integrated circuit Methods are disclosed for the layout and manufacture of microelectronic circuits. The methods employ the monitoring of the placement of macros within circuit... |
| US-7,783,948 |
Removeable and replaceable tap domain selection circuitry Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is... |
| US-7,783,947 |
Controller applying stimulus data while continuously receiving serial
stimulus data An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning... |
| US-7,783,925 |
Receiving control, data, and control segments of communication scan
packets A system and method for improved performance and optimization of data exchanges over a communications link is described, including a method for communicating... |
| US-7,783,576 |
Secure distribution of digital data A secure digital data distribution system (100) for preventing unauthorized access to digital data. The system utilizes an identification system module (116)... |
| US-7,783,263 |
Simplified digital predistortion in a time-domain duplexed transceiver A transceiver for time-domain duplexed (TDD) communications, for example in connection with wireless broadband data communications, is disclosed. The transceiver... |
| US-7,782,932 |
Circuit and method for evaluating the performance of an adaptive decision
feedback equalizer-based serializer... A circuit and method for evaluating serializer deserializer (SERDES) performance that is particularly advantageous when the SERDES has a decision feedback... |
| US-7,782,930 |
Optimized short initialization after low power mode for digital subscriber
line (DSL) communications A digital subscriber line (DSL) system that provides fast exit from an idle state includes a central office (CO) modem for communicating with a customer premises... |
| US-7,782,822 |
Reducing collisions in beamforming wireless systems A device comprising transceiver logic and control logic coupled to the transceiver logic. The control logic is adapted to use the transceiver logic to broadcast... |
| US-7,782,800 |
Discovery, detection, and management of daisy-chain system topology Devices and methods are disclosed for detection and management of daisy-chain system topologies. A method is disclosed for auto-discovery and auto-enumeration.... |
| US-7,782,521 |
System and method for displaying images A system and method for reducing visible speckle in images displayed using coherent light. In an embodiment, a system for displaying images includes a light... |
| US-7,782,389 |
System and method for varying exposure time for different parts of a field
of view while acquiring an image A system and method for exposing different parts of a single field of view for various and differing lengths of time while capturing an image is provided. For... |
| US-7,782,341 |
In place rotation of images for low memory systems Rotation in the storage domain is a one-one function with the domain equal to the range. This permits an image to be rotated in place. Each image size implies at... |
| US-7,782,141 |
Adaptive signal-feed-forward circuit and method for reducing amplifier
power without signal distortion Digital amplifying circuitry delays a digital data signal (IN.sub.R) to produce an output signal (Vout.sub.R). The delayed digital data signal is converted to an... |
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