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Patent # Description
US-7,577,565 Adaptive voice playout in VOP
Packetized CELP-encoded speech playout with frame truncation during silence and frame expansion method dependent upon voicing classification with voiced frame...
US-7,577,248 Method and apparatus for echo cancellation, digit filter adaptation, automatic gain control and echo...
Hands-free phones with voice activity detection using a comparison of frame power estimate with an adaptive frame noise power estimate, automatic gain control...
US-7,576,902 Spatial light modulator mirror metal having enhanced reflectivity
In accordance with the teachings of the present invention, a spatial light modulator mirror metal having enhanced reflectivity is provided. In a particular...
US-7,576,797 Automatic white balancing via illuminant scoring autoexposure by neural network mapping
Automatic white balancing and/or autoexposure as useful in a digital camera extracts color channel gains from comparisons of image colors with reference colors...
US-7,576,759 Parallel dithering contour mitigation
A method of producing an image. Image data word comprising image data bits for a portion of the image is received at a first frame rate. At least two threshold...
US-7,576,758 Using super-pixels for efficient in-place rotation of images
Rotation in the storage domain is a one-one function with the domain equal to the range. This permits an image to be rotated in place. Each image size implies at...
US-7,576,668 Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC)
A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which...
US-7,576,595 Buffer circuit
The objective of the present invention is to present a buffer circuit by which a load can be driven at a high speed while restraining an increase in power...
US-7,576,594 Method and device for reducing influence of early effect
A method is provided for improving the performance of a circuit containing a three-terminal device. In the operation of a circuit containing three-terminal...
US-7,576,568 Self-selecting precharged domino logic circuit
A domino logic circuit having an input terminal and a precharge node. A first switch is responsive to a second switch sensing one of a high or low voltage at the...
US-7,575,969 Buried layer and method
A high resistivity silicon for RF passive operation including CMOS structures with implanted CMOS wells and a buried layer under the wells formed by deep...
US-7,575,147 Compliant wirebond pedestal
A wire bonder (900) with a rigid pedestal (902) having resilient inserts (920). A package (904) placed on the pedestal (902) contains an electrical device (906)....
US-7,574,641 Probeless testing of pad buffers on wafer
The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
US-7,574,586 Efficient transfer of branch information
A system comprising a processor adapted to execute software code comprising branch instructions and a trace logic coupled to the processor and adapted to...
US-7,574,584 Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa...
In some embodiments, a processor includes fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and...
US-7,574,351 Arranging CELP information of one frame in a second packet
Packets of real-time information are sent with a source rate greater than zero kilobits per second, and a time or path or combined time/path diversity rate...
US-7,574,278 Scheduling system and method
A method and apparatus for scheduling in a wafer fab. The method comprising means for weighting inventories according to at least one of logpoints or reticle,...
US-7,574,181 System and method for preprocessing a signal for transmission by a power amplifier
System and method for preprocessing a signal for transmission by a power amplifier. In a preferred embodiment a multiple input multiple output processor is...
US-7,573,960 Narrow band interference cancellation technique for OFDM transmitters
A computational algorithm provides new and effective interference cancellation of the in-band spurious signals for the Orthogonal Frequency Division Multiplex...
US-7,573,884 Cable modem downstream channel bonding re-sequencing mechanism
A novel apparatus and method of packet re-sequencing applicable to systems wherein packets are assigned sequence numbers and transmitted over multiple channels...
US-7,573,830 Integrated programmable device for safety critical applications
An integrated programmable device has a plurality of signal inputs (P1, P2, P3) connected to respective ones of a plurality of switching elements (S1, S2, S3)....
US-7,573,414 Maintaining a reference voltage constant against load variations
A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at...
US-7,573,405 System updating accumulated statistics coding variable values after multiple encodings
A system for, and method of, entropy coding. In one embodiment, the system includes: (1) a memory configured to contained initialized accumulated statistics...
US-7,573,325 CMOS reference current source
A CMOS reference current source comprises two circuit branches connected in parallel between supply terminals. The first circuit branch includes a series...
US-7,573,307 Systems and methods for reduced area delay locked loop
Various systems and methods for signal synchronization are disclosed. For example, some embodiments of the present invention provide methods for reduced area...
US-7,573,139 Packed system of semiconductor chips having a semiconductor interposer
A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the...
US-7,573,137 Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices
A device has a first semiconductor chip (101) with contact pads in an interior first set (102) and a peripheral second set (103). A deformed sphere (104) of...
US-7,573,111 Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from...
US-7,573,086 TaN integrated circuit (IC) capacitor
A capacitor is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor generally comprises a top conductive plate, a...
US-7,572,735 Blanket resist to protect active side of semiconductor
Yield loss in semiconductor processing is mitigated by forming a resist over an active side of a semiconductor workpiece or wafer, as well as around the edge of...
US-7,572,733 Gas switching during an etch process to modulate the characteristics of the etch
Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein...
US-7,572,716 Semiconductor doping with improved activation
A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active...
US-7,572,698 Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean
A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A...
US-7,572,693 Methods for transistor formation using selective gate implantation
Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate...
US-7,572,679 Heat extraction from packaged semiconductor chips, scalable with chip area
A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more...
US-7,572,677 Arrangement in semiconductor packages for inhibiting adhesion of lid to substrate while providing compression...
In a semiconductor flip-chip package having a semiconductor die as part of a substrate assembly, a lid (or lid assembly) and substrate are supported to prevent...
US-7,571,419 Methods and systems for performing design checking using a template
A design application improves design checking by utilizing a template. During the checking process, the design application divides the design layout into...
US-7,571,366 Sequential signals selecting mode and stopping transfers of interface adaptor
A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states...
US-7,571,365 Wafer scale testing using a 2 signal JTAG interface
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-7,571,364 Selectable JTAG or trace access with data store and output
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and...
US-7,571,094 Circuits, processes, devices and systems for codebook search reduction in speech coders
An electronic circuit includes storage circuitry and a speech coder coupled with the storage circuitry to have a codebook with sets of track location numbers for...
US-7,570,646 Apparatus and method for an interface unit for data transfer between a host processing unit and a multi-target...
A slave interface unit controls the exchange of data between a master processing unit and a plurality of slave processing units operating in the asynchronous...
US-7,570,527 Static random-access memory having reduced bit line precharge voltage and method of operating the same
A bit line precharge circuit, a method of precharging a bit line and an SRAM device incorporating the circuit or the method. In one embodiment, the bit line...
US-7,570,410 High brightness display systems using multiple spatial light modulators
The display system separates reflected and transmitted light from a color wheel of the display system; and modulates the separated reflected and transmitted...
US-7,570,182 Adaptive spectral noise shaping to improve time to digital converter quantization resolution using dithering
A novel and useful apparatus for and method of improving the quantization resolution of a time to digital converter in a digital PLL using noise shaping. The TDC...
US-7,570,113 Overload recovery circuit for folded cascode amplifiers
In a method and apparatus for rapidly recovering an improved amplifier from an overload condition, a cascode amplifier (CASA) having a pair of inputs and an...
US-7,570,108 Apparatus for regulating voltage
An apparatus for regulating voltage for at least one differential transistor pair having a voltage follower buffer, the voltage follower section having a first...
US-7,570,100 Potential and rate adjust header switch circuitry reducing transient current
System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as...
US-7,570,076 Segmented programmable capacitor array for improved density and reduced leakage
A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal (100), a...
US-7,570,043 Switches bidirectionally connecting external lead to PLL voltage tune line
An integrated circuit, a phase locked loop, a voltage tune probe and a method of screening an integrated circuit employing a phase locked loop thereof. In one...
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