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Patent # Description
US-7,596,491 Layered CELP system and method
Layered (embedded) code-excited linear prediction (CELP) speech encoders/decoders with adaptive plus algebraic codebooks applied in each layer with fixed...
US-7,596,456 Method and apparatus for cassette integrity testing using a wafer sorter
A system and methods for the evaluation of the integrity of a wafer cassette and the disposition thereof are based upon evaluation of wafer measurement data...
US-7,595,968 Circuit to reduce internal ESD stress on device having multiple power supply domains
An ESD protection circuit is designed on an integrated circuit (100) having a first power supply bus (106) and a second power supply bus (108). The circuit...
US-7,595,924 Bracket for piezoelectric drive torsional hinge mirror
A combination pivoting mirror and support bracket has a bracket for supporting a pivoting mirror assembly and for attaching the combination to a using device....
US-7,595,771 Electro-optical, tunable, broadband color modulator
A display system for creating a full-color projected image. Light from a white light source passes through a color modulator (106). The color modulator (106) is...
US-7,595,744 Correcting offset errors associated with a sub-ADC in pipeline analog to digital converters
An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could...
US-7,595,676 Comparator and method with controllable threshold and hysteresis
A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first...
US-7,595,670 Electronic device and method for on chip skew measurement
The invention relates to an integrated electronic device for digital signal processing, which includes a phase locked loop for generating an output clock signal...
US-7,595,660 Low-delay complimentary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and...
Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed...
US-7,595,649 Method to accurately estimate the source and drain resistance of a MOSFET
Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series...
US-7,595,644 Power-over-ethernet isolation loss detector
An AC generator has a first terminal coupled through an Isolation Loss Detect (ILD) capacitor to the positive bus of a Power-Over-Ethernet (POE) system, and has...
US-7,595,624 Slope compensation for switching regulator
In one embodiment, a switching regulator comprises a control circuit that activates and deactivates at least one power switch to control a voltage of a switching...
US-7,595,619 Feed-forward circuit for adjustable output voltage controller circuits
A feedback loop in a variable power supply has an adjustable response speed based on operating conditions of the power supply. The response speed can be...
US-7,595,616 Control circuit for a polarity inverting buck-boost DC-DC converter
A control circuit for a polarity inverting buck-boost DC-DC converter, includes an operational trans-conductance amplifier that has inputs to which a sensed...
US-7,595,615 Systems and methods for providing over-current protection in a switching power supply
A system and method is provided for providing integrated over-current protection in a switching power supply. In one embodiment, a switching power supply could...
US-7,595,525 Integrated circuit capacitor having antireflective dielectric
A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom...
US-7,595,245 Semiconductor device having a gate electrode material feature located adjacent a gate width side of its gate...
The present invention provides a semiconductor device, a method of manufacture therefore and an integrated circuit including the same. The semiconductor device...
US-7,594,162 Viterbi pretraceback for partial cascade processing
This invention modifies Viterbi decoding to improve BER. Within the state metric unit cascade block, this invention forces the unused ACS units decision bits to...
US-7,593,841 Emulation export sequence with distributed control
Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into...
US-7,593,580 Video encoding using parallel processors
A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus...
US-7,592,867 Common mode feedback for large output swing and low differential error
A differential amplifier includes a differential input pair (2A) coupled to a folded cascode stage (2B) and a common mode feedback circuit (34) including a...
US-7,592,860 Minimizing the number of external terminals required when compensation is to be provided for signal drop in...
Compensation is provided for signal drop in bond wires of an integrated circuit (IC) while minimizing the number of external terminals in the IC package. A...
US-7,592,859 Apparatus to compare an input voltage with a threshold voltage
Apparatus to compare an input signal to a threshold level are disclosed. An example circuit described herein includes a Widlar bandgap circuit to receive the...
US-7,592,794 Integrated low power received signal strength indicator (RSSI) with linear characteristic
An RSS indicator with a linear characteristic that is of a simple configuration, low current consumption and small die area requirements, comprises a pair of...
US-7,592,252 Versatile system for charge dissipation in the formation of semiconductor device structures
The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200),...
US-7,590,974 Recovery from corruption using event offset format in data trace
A method of tracing data processor activity with recover from detection of trace stream corruption. If the first trace data following detection of corruption is...
US-7,590,912 Using a chip as a simulation engine
The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock...
US-7,590,910 Tap and linking module for scan access of multiple cores with IEEE 1149.1 test access ports
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
US-7,590,894 Method of translating system events into signals for activity monitoring
Disclosed herein is a system and method for receiving encoded events from a system that is being debugged or profiled. The encoded events are input to a decoder...
US-7,590,893 Recording control point in trace receivers
A trace receiver with multiple recording interfaces may be used to record the same input. The historical control point for starting and stopping trace recording...
US-7,590,892 Method and system of profiling real-time streaming channels
A method and system of profiling streaming channels. At least some of the illustrative embodiments are methods comprising executing a traced program on a target...
US-7,590,677 Processor with summation instruction using overflow counter
Performing a sum of numbers operation in a variable bit-length environment of a processor in response to a summation instruction, comprising a) adding a least...
US-7,590,047 Memory optimization packet loss concealment in a voice over packet network
A method to reduce memory requirements for a packet loss concealment algorithm in the event of packet loss in a receiver of pulse code modulated voice signals. A...
US-7,589,533 One time operating state detecting method and apparatus
A method and apparatus for detecting a change in an electrical property between contacts. A one-time operating state detection device includes a member coupling...
US-7,589,516 Poly-phase electric energy meter
A poly-phase electric energy meter comprises a front-end that converts analog current input signals and analog voltage input signals to digital current and...
US-7,589,378 Power LDMOS transistor
A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the...
US-7,587,757 Surveillance implementation in managed VOP networks
A procedure for accomplishing surveillance within a managed VoP network when end-user encryption/decryption and NAT are in place. The procedure comprises first...
US-7,587,648 Integrated circuit having electrically isolatable test circuitry
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test....
US-7,587,644 Scan testing using response pattern as stimulus pattern after reset
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one...
US-7,587,642 System and method for performing concurrent mixed signal testing on a single processor
The present application describes a system and method for testing semiconductor devices and specifically for testing mixed signal semiconductor devices. The test...
US-7,587,583 Method and system for processing a "WIDE" opcode when it is not used as a prefix for an immediately following...
Methods and systems are provided for the selective use of a Java WIDE opcode as a prefix as defined in the instruction set of the Java virtual machine or...
US-7,587,577 Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch...
A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry...
US-7,587,539 Methods of inter-integrated circuit addressing and devices for performing the same
Inter-integrated circuit-capable devices for use on an inter-integrated circuit bus are disclosed. The inter-integrated circuit-capable devices include...
US-7,587,532 Full/selector output from one of plural flag generation count outputs
A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a "high water mark" to different levels for different...
US-7,587,525 Power control with standby, wait, idle, and wakeup signals
An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a...
US-7,587,315 Concealment of frame erasures and method
A decoder for code excited LP encoded frames with both adaptive and fixed codebooks; erased frame concealment uses repetitive excitation plus a smoothing of...
US-7,587,190 Systems and methods for low power clock generation
Various systems and methods for low power identification are described herein. For example, a radio frequency device including a radio frequency energy receiver....
US-7,586,993 Interleaver memory selectably receiving PN or counter chain read address
A method and apparatus for interleaving multiple frames of data as disclosed provide for an extremely streamlined approach to achieving both methods of...
US-7,586,668 Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from...
US-7,586,659 Audio MEMS mirror feedback
A mirror device and a method for audio feedback of a MEMS mirror device are presented. The mirror device includes a mirror with a reflective surface located to...
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