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Patent # Description
US-7,667,349 Providing power to a load by controlling a plurality of generating devices
An apparatus for controlling provision of power to a load by a plurality of generating devices in a plurality of phased signals during a first operating...
US-7,667,275 Using oxynitride spacer to reduce parasitic capacitance in CMOS devices
A complementary metal oxide semiconductor (CMOS) device has a substrate 100, a gate structure 108 disposed atop the substrate, and spacers 250, deposited on...
US-7,667,243 Local ESD protection for low-capicitance applications
A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power...
US-7,666,748 Method of forming amorphous source/drain extensions
A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations and depositing...
US-7,666,729 Method for improving the thermal stability of silicide
An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer 110. The method may include forming an...
US-7,665,850 Prism for high contrast projection
Prism elements having TIR surfaces placed in close proximity to the active area of a SLM device to separate unwanted off-state and/or flat-state light from the...
US-7,664,808 Efficient real-time computation of FIR filter coefficients
Systems and methods for determining coefficients of an Finite Impulse Response (FIR) filter are disclosed. The FIR filter coefficients are computed by...
US-7,663,516 Scheme for non-linearity correction of residue amplifiers in a pipelined analog-to-digital converter (ADC)
In a method and apparatus for compensating non-linearity of a gain of a residual amplifier (RA), a pipelined analog-to-digital converter (ADC) converts an analog...
US-7,663,424 Circuit and method for reducing charge injection and clock feed-through in switched capacitor circuits
A low charge injection, low clock feed-through switch (1) has an input signal (Vin) applied both to the sources of first (S1) and second (2) switching...
US-7,663,417 Phase-locked loop circuit
A phase-locked loop circuit comprises a phase frequency detector, a charge pump associated with a loop capacitance, and a voltage controlled oscillator. The...
US-7,663,379 Capacitance-to-voltage conversion method and apparatus
A method of capacitance-to-voltage conversion with an external sensor capacitor (C.sub.P) and a capacitance-to-voltage converter (14) implemented on an...
US-7,663,351 Synchronization circuitry for multiple power converters coupled at a common node
Synchronization circuitry and synchronization system for synchronizing converters/controllers that are electrically-coupled to a common synchronization node. The...
US-7,662,690 Method of preparing a semiconductor substrate utilizing plural implants under an isolation region to isolate...
Multiple blanket implantations of one or more p type dopants into a semiconductor substrate are performed to facilitate isolation between nwell regions...
US-7,662,688 Application of different isolation schemes for logic and embedded memory
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and...
US-7,661,049 Integrated circuit with JTAG port, TAP linking module, and off-chip TAP interface port
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP...
US-7,660,419 System and method for security association between communication devices within a wireless personal and local...
The present application describes a method and system for discovering and authenticating communication devices within a wireless network. According to an...
US-7,660,364 Method of transmitting serial bit-stream and electronic transmitter for transmitting a serial bit-stream
The present invention relates to an electronic transmitter for serially transmitting bit sequences. The electronic transmitter includes a detection device 10 and...
US-7,660,229 Pilot design and channel estimation
Embodiments of the invention provide method and apparatus for generating a structure in an orthogonal frequency division multiplexing OFDM communication system...
US-7,660,150 Memory cell having improved write stability
A method is provided for writing to a memory cell having a read access circuit that is separate and isolatable from a write access circuit. The method comprises...
US-7,659,918 Apparatus and methods for adjusting the rotational frequency of a scanning device
The present invention provides methods and apparatus for adjusting the resonant frequency, scan velocity or other parameters of a pivotally functional surface...
US-7,659,754 CMOS power switching circuit usable in DC-DC converter
A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in...
US-7,659,741 Parallel scan distributors and collectors and process of testing integrated circuits
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-7,657,811 Low power testing of very large circuits
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...
US-7,657,810 Scan testing using scan frames with embedded commands
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test...
US-7,657,808 Propagation test strobe circuitry with boundary scan circuitry
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits...
US-7,657,806 Position independent testing of circuits
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing...
US-7,657,790 Scan frame based test access mechanisms
Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The...
US-7,656,934 Wireless communications system with secondary synchronization code based on values in primary synchronization code
A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting...
US-7,656,695 Electronic fuse system and methods
An electronic fuse system and method are disclosed employing a fuse ROM having one or more blocks of memory. Each block of memory comprises a plurality of words...
US-7,656,224 Power efficient dynamically biased buffer for low drop out regulators
The buffer circuit includes a first transistor MP1 having a first end coupled to an output node N2 and a control node coupled to an input node N1; a second...
US-7,655,946 IC with comparator receiving expected and mask data from pads
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the...
US-7,655,555 In-situ co-deposition of Si in diffusion barrier material depositions with improved wettability, barrier...
A copper interconnect having a transition metal-silicon-nitride barrier (106). A transition metal-nitride is co-deposited with Si by reactive sputtering in a Si...
US-7,655,553 Microstructure sealing tool and methods of using the same
A method of packing electronic devices and an apparatus thereof are disclosed herein. The method allows for usage of solder materials with a melting temperature...
US-7,655,552 Double density method for wirebond interconnect
A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a...
US-7,655,523 Advanced CMOS using super steep retrograde wells
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer...
US-7,655,492 Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from...
US-7,654,677 Yokeless hidden hinge digital micromirror device
A micromirror array 110 fabricated on a semiconductor substrate 11. The array 110 is comprised of three operating layers 12, 13, 14. An addressing layer 12 is...
US-7,653,758 Memory system with memory controller and board comprising a digital buffer wherein input/output data and clock...
A digital registered data buffer is disclosed that has data paths each with a data input for receiving a digital data input signal (Dn), a clock input for...
US-7,653,632 File system for storing multiple files as a single compressed file
A file archive system for storing multiple files and directories as a single file. The file archive system could be used on a hand-held computer or other...
US-7,653,240 Color filter array and method
Color filter array demosaicing as is useful in digital cameras, still and video, using a single sensor includes blending of directional and non-directional...
US-7,653,045 Reconstruction excitation with LPC parameters and long term prediction lags
A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice...
US-7,652,657 Method and system for determining characteristics of optical signals on spatial light modulator surfaces
The present application describes a system and method for determining characteristics (e.g., exact band location, orientation and height and the spot shape and...
US-7,652,537 Amplifier with programmable input impedance
One embodiment of the invention includes an amplifier system. The amplifier system comprises an amplifier stage configured to receive an input signal at an...
US-7,652,513 Slave latch controlled retention flop with lower leakage and higher performance
In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input...
US-7,652,461 High efficiency power converter operating free of an audible frequency range
A DC-DC converter operates outside of an audible frequency range under light current load conditions with reduced switching frequency by reducing supply current...
US-7,652,445 On-chip compensation for a fully differential voice coil motor control
A disk drive controller including a differential voice coil motor control function is disclosed. The differential voice coil motor control function includes an...
US-7,651,734 Micromechanical device fabrication
A method of fabricating a micromechanical device. Several of the micromechanical devices are fabricated 20 on a common wafer. After the devices are fabricated,...
US-7,651,227 Projection system and method including spatial light modulator and compact diffractive optics
A method and apparatus for a projection display system includes a spatial light modulator and a volume illumination hologram. The spatial light modulator...
US-7,650,549 Digital design component with scan clock generation
A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode...
US-7,650,528 Fuse farm redundancy method and system
A system and method for making efficient use of fuse ROM redundancy to increase yield and security. Some embodiments provide a memory repair system including a...
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