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Potential and rate adjust header switch circuitry reducing transient
System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as...
Segmented programmable capacitor array for improved density and reduced
A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal (100), a...
Switches bidirectionally connecting external lead to PLL voltage tune line
An integrated circuit, a phase locked loop, a voltage tune probe and a method of screening an integrated circuit employing a phase locked loop thereof. In one...
Semiconductor package-on-package system including integrated passive
A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more...
Test pads on leads unconnected with die pads
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test...
Semiconductor device made by multiple anneal of stress inducing layer
The invention provides a method of fabricating a semiconductor device. In one aspect, the method comprises forming a stress inducing layer over a semiconductor...
Spin on glass (SOG) etch improvement method
A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first...
Method for manufacturing a semiconductor device having improved across
chip implant uniformity
The present invention provides a method for manufacturing a semiconductor device, which includes forming a gate structure over a substrate, and forming a stack...
Gate critical dimension variation by use of ghost features
According to various embodiments, the present teachings include various methods for forming a semiconductor device, computer readable medium for forming a...
Boundary scan path method and system with functional and non-functional
scan cell memories
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a...
Method and apparatus for synchronizing signals in a testing system
The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal...
System and method of communicating using combined signal parameter
A system and method of data communication uses variable transmit antenna delays based on communication signal uplink measurements. The signals for each channel...
Data transmission scheme using channel group and DOCSIS implementation
A novel apparatus for and a method of data transmission whereby an input data stream is distributed over a plurality of physical channels within a logical...
Color adjustment for clipped pixels
A control module for use in an image display system includes a gain module operable to amplify a signal received by the control module and to communicate an...
Single-electron injection/extraction device for a resonant tank circuit
and method of operation thereof
A system for reducing phase-noise in a resonant tank circuit. The system includes a single-electron device configured to inject a single electron into the...
System and method for synchronizing multiple oscillators
A system and method for synchronizing an oscillator with multiple phases at a desired phase angle difference. A relative measure of a phase angle difference...
Voltage converting circuit and battery device
A voltage converting circuit and a battery device, aimed at the problem that the breakdown voltage required for the driving input of the selected switch element...
High speed controller area network receiver having improved EMI immunity
A CAN receiver architecture design that provides better immunity against EMI interference than conventional designs is disclosed herein. This CAN receiver...
Electrically inactive via for electromigration reliability improvement
A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second...
Air gap in integrated circuit inductor fabrication
In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of...
Method of making and using guardringed SCR ESD protection cell
Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an...
Roller wire brake for wire bonding machine
While fabricating a packaged semiconductor chip, a wire is bonded on a chip contact pad using a wire bonding machine. A bond head of the wire bonding machine is...
Embedded garbage collection
An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection...
Telecommunications receiver with automatic gain control
A receiver 30 has an adjustable gain control circuit 32 that provides gain control base on the magnitude of the signal at the input of an analog-to-digital...
Single-antenna interference cancellation receiver in time slot
A receiver (MST) for use in a modulated communications system wherein data is communicated in a time-slotted format. The receiver comprises circuitry (22) for...
Apparatus for and method of detection of powered devices over a network
A novel mechanism for detecting the presence of powered devices over a network. A unique, infinite pseudo-random sequence of pulses are generated and transmitted...
Configuration DSL transceiver
A DSL modem (21) including a configurable digital transceiver (30) is disclosed. The digital transceiver (30) includes a configuration register (43), or other...
Apparatus for and method of synchronization and beaconing in a WLAN mesh
A novel and useful synchronization mechanism that functions to provide a uniform time base for mesh points in a WLAN mesh based network. The invention enables...
SRAM bias for read and write
An integrated circuit includes a SRAM array including a plurality of SRAM cells arranged in a plurality of rows and columns and having a plurality of word lines...
Sigma delta modulator summing input, reference voltage, and feedback
A multibit sigma delta modulator for conveting an analog input signal (Vin) into a multibit digital output signal is disclosed. In one embodiment, the multibit...
Discrete-time, single-amplifier, second-order, delta-sigma
analog-to-digital converter and method of operation...
A discrete-time, single-amplifier, second-order, delta-sigma analog-to-digital converter (DT-SADS ADC) and a method of operating the same. The DT-SADS ADC...
Performance and area scalable cell architecture technology
An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The...
Audio effect rendering based on graphic polygons
A method to supply audio effects to video games employs graphics information of sound source objects and sound interacting objects in a real time physical model...
Method and system for firmware downloads
A method and system for downloading firmware by a device controller from a data source while connected to a host. The device controller connects to the host and...
Method and process for generating an optical proximity correction model
based on layout density
A method (300) for generating an optical proximity correction model for a mask layout having an asymmetric feature structure includes fabricating a mask (310)...
Edge recognition based high voltage pseudo layer verification methodology
for mix signal design layout
Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage...
Distributed depth trace receiver
Input processing limitations may be solved by placing multiple units in series, with each unit recording some portion of the incoming data. This requires the...
Programmable extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least...
High bandwidth high gain receiver equalizer
A receiver equalizer with a first equalizer unit having a basic equalizer stage and a negative impedance cell connected to the basic equalizer stage. Preferably...
Reconfigurable chip level equalizer architecture for multiple antenna
A system comprising a plurality of adaptive equalizers adapted to couple to a plurality of receive antennas, each of the antennas capable of receiving a...
Systems and methods for multiplexing and demultiplexing multiple data
The present disclosure describes systems and methods for multiplexing multiple data sources Some illustrative embodiments include a method for combining multiple...
Ferroelectric memory array for implementing a zero cancellation scheme to
reduce plateline voltage in...
Memory devices are provided, having a ferroelectric memory array and a zero cancellation system with one or more zero cancellation circuits for coupling a...
Apparatus and method for a clip device for coupling a heat sink plate
system with a burn-in board system
In a burn-in test configuration wherein a chip board having a plurality of semiconductor chips engages a heat sink board having a plurality of heat sinks. When...
Gate driver circuit for power transistor
A circuit arrangement with a gate driver circuit for a power transistor is disclosed which is suitable for low voltage applications, permitting a rail-to-rail...
Methods and apparatus to reduce propagation delay of circuits
Methods and apparatus to reduce propagation delay of circuits are disclosed. A disclosed apparatus to reduce propagation delay of a circuit comprises a level...
Generating an output signal with a frequency that is a non-integer
fraction of an input signal
Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero...
Chip scale power LDMOS device
A semiconductor device includes at least one macro-cell device, the macro-cell device comprising a plurality of LDMOS devices. A first conductive layer is formed...
Reliable high voltage gate dielectric layers using a dual nitridation
Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor...
Method for forming a mixed voltage circuit having complementary devices
A mixed voltage circuit is formed by providing a substrate (12) having a first region (20) for forming a first device (106), a second region (22) for forming a...
Etching systems and processing gas specie modulation
A method and system for etching a substrate control selectivity of the etch process by modulating the gas specie of the reactants. The gas specie selectively...